1package top 2 3import chisel3._ 4import chisel3.util._ 5 6import bus.simplebus._ 7import device._ 8 9class SimMMIO extends Module { 10 val io = IO(new Bundle { 11 val rw = Flipped(new SimpleBusUC) 12 val mtip = Output(Bool()) 13 }) 14 15 val devAddrSpace = List( 16 (0x40600000L, 0x10L), // uart 17 (0x40700000L, 0x10L), // timer 18 (0x40000000L, 0x400000L), // vmem 19 (0x40800000L, 0x8L) // vga ctrl 20 ) 21 22 val xbar = Module(new SimpleBusCrossbar(1, devAddrSpace)) 23 xbar.io.in(0) <> io.rw 24 25 val uart = Module(new AXI4UART) 26 val timer = Module(new AXI4Timer(sim = true)) 27 val vga = Module(new AXI4VGA(sim = true)) 28 uart.io.in <> xbar.io.out(0).toAXI4Lite() 29 timer.io.in <> xbar.io.out(1).toAXI4Lite() 30 vga.io.in.fb <> xbar.io.out(2).toAXI4Lite() 31 vga.io.in.ctrl <> xbar.io.out(3).toAXI4Lite() 32 vga.io.vga := DontCare 33 34 io.mtip := timer.io.extra.get.mtip 35} 36