1package top 2 3import chisel3._ 4import chipsalliance.rocketchip.config 5import device._ 6import freechips.rocketchip.amba.axi4.AXI4Xbar 7import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 8 9class SimMMIO()(implicit p: config.Parameters) extends LazyModule { 10 11 val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x10000000L, 0xfffffff)))) 12 val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xf)))) 13 val vga = LazyModule(new AXI4VGA( 14 sim = false, 15 fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)), 16 ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L)) 17 )) 18 val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff)))) 19 20 val axiBus = AXI4Xbar() 21 22 uart.node := axiBus 23 vga.node :*= axiBus 24 flash.node := axiBus 25 sd.node := axiBus 26 27 lazy val module = new LazyModuleImp(this){ 28 val io = IO(new Bundle() { 29 val uart = new UARTIO 30 }) 31 io.uart <> uart.module.io.extra.get 32 } 33 34} 35 36 37//class SimMMIO(para: TLParameters) extends Module { 38// val io = IO(new Bundle { 39// val rw = Flipped(TLCached(para)) 40// val uart = new UARTIO 41// }) 42// 43// val devAddrSpace = List( 44// (0x40600000L, 0x10L), // uart 45// (0x50000000L, 0x400000L), // vmem 46// (0x40001000L, 0x8L), // vga ctrl 47// (0x40000000L, 0x1000L), // flash 48// (0x40002000L, 0x1000L) // dummy sdcard 49// ) 50// 51// val xbar = Module(new NaiveTL1toN(devAddrSpace, io.rw.params)) 52// xbar.io.in <> io.rw 53// 54// val axiOut = xbar.io.out.map(tl => AXI4ToAXI4Lite(MMIOTLToAXI4(tl))) 55// 56// val uart = Module(new AXI4UART) 57// val vga = Module(new AXI4VGA(sim = true)) 58// val flash = Module(new AXI4Flash) 59// val sd = Module(new AXI4DummySD) 60// 61// uart.io.in <> axiOut(0) 62// vga.io.in.fb <> axiOut(1) 63// vga.io.in.ctrl <> axiOut(2) 64// flash.io.in <> axiOut(3) 65// sd.io.in <> axiOut(4) 66// vga.io.vga := DontCare 67// io.uart <> uart.io.extra.get 68//} 69