1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chipsalliance.rocketchip.config 21import device._ 22import freechips.rocketchip.amba.axi4.{AXI4EdgeParameters, AXI4MasterNode, AXI4Xbar} 23import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp} 24import difftest._ 25 26class SimMMIO(edge: AXI4EdgeParameters)(implicit p: config.Parameters) extends LazyModule { 27 28 val node = AXI4MasterNode(List(edge.master)) 29 30 val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x10000000L, 0xfffffff)))) 31 val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xf)))) 32 val vga = LazyModule(new AXI4VGA( 33 sim = false, 34 fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)), 35 ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L)) 36 )) 37 val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff)))) 38 val intrGen = LazyModule(new AXI4IntrGenerator(Seq(AddressSet(0x40070000L, 0x0000ffffL)))) 39 40 val axiBus = AXI4Xbar() 41 42 uart.node := axiBus 43 vga.node :*= axiBus 44 flash.node := axiBus 45 sd.node := axiBus 46 intrGen.node := axiBus 47 48 axiBus := node 49 50 val io_axi4 = InModuleBody { 51 node.makeIOs() 52 } 53 54 lazy val module = new LazyModuleImp(this){ 55 val io = IO(new Bundle() { 56 val uart = new UARTIO 57 val interrupt = new IntrGenIO 58 }) 59 io.uart <> uart.module.io.extra.get 60 io.interrupt <> intrGen.module.io.extra.get 61 } 62 63} 64