1package top 2 3import chisel3._ 4import chisel3.util._ 5 6import bus.simplebus._ 7import device._ 8 9class DeviceHelper extends BlackBox { 10 val io = IO(new Bundle { 11 val clk = Input(Clock()) 12 val reset = Input(Bool()) 13 val reqValid = Input(Bool()) 14 val reqWen = Input(Bool()) 15 val reqAddr = Input(UInt(64.W)) 16 val reqWdata = Input(UInt(64.W)) 17 val reqWmask = Input(UInt(8.W)) 18 val respRdata = Output(UInt(64.W)) 19 }) 20} 21 22class SimMMIO extends Module { 23 val io = IO(new Bundle { 24 val rw = Flipped(new SimpleBusUC) 25 }) 26 27 val devAddrSpace = List( 28 (0x40600000L, 0x10L), // uart 29 (0x40700000L, 0x10L), // timer 30 (0x40000000L, 0x400000L), // vmem 31 (0x40800000L, 0x8L) // vga ctrl 32 ) 33 34 val xbar = Module(new SimpleBusCrossbar(1, devAddrSpace)) 35 xbar.io.in(0) <> io.rw 36 37 val uart = Module(new AXI4UART) 38 val timer = Module(new AXI4Timer) 39 val vga = Module(new AXI4VGA(sim = true)) 40 uart.io.in <> xbar.io.out(0).toAXI4Lite() 41 timer.io.in <> xbar.io.out(1).toAXI4Lite() 42 vga.io.in.fb <> xbar.io.out(2).toAXI4Lite() 43 vga.io.in.ctrl <> xbar.io.out(3).toAXI4Lite() 44 vga.io.vga := DontCare 45 46 //val helper = Module(new DeviceHelper) 47 //val helperIO = xbar.io.out(0) 48 //helper.io.clk := clock 49 //helper.io.reset := reset.asBool 50 //helper.io.reqValid := helperIO.req.valid 51 //helper.io.reqWen := helperIO.isWrite() 52 //helper.io.reqAddr := helperIO.req.bits.addr 53 //helper.io.reqWdata := helperIO.req.bits.wdata 54 //helper.io.reqWmask := helperIO.req.bits.wmask 55 //helperIO.resp.bits.rdata := helper.io.respRdata 56 //helperIO.resp.bits.cmd := 0.U 57 //helperIO.resp.bits.user := 0.U 58 59 //helperIO.req.ready := true.B 60 //helperIO.resp.valid := RegNext(helperIO.req.valid) 61} 62