1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import org.chipsalliance.cde.config 21import device._ 22import freechips.rocketchip.amba.axi4.{AXI4EdgeParameters, AXI4MasterNode, AXI4Xbar} 23import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp} 24import difftest._ 25import utility.AXI4Error 26 27class SimMMIO(edge: AXI4EdgeParameters)(implicit p: config.Parameters) extends LazyModule { 28 29 val node = AXI4MasterNode(List(edge.master)) 30 31 val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL) 32 // val uartRange = AddressSet(0x40600000, 0x3f) // ? 33 val flashRange = AddressSet(0x10000000L, 0xfffffff) 34 val sdRange = AddressSet(0x40002000L, 0xfff) 35 val intrGenRange = AddressSet(0x40070000L, 0x0000ffffL) 36 37 def subtract(x: AddressSet, y: Seq[AddressSet]): Seq[AddressSet] = { 38 if (y.length == 0) { Seq(x) } 39 else if (y.length == 1) { x.subtract(y.head) } 40 else { 41 x.subtract(y.head).flatMap(remain => subtract(remain, y.tail)) 42 } 43 } 44 45 val illegalRange = subtract(AddressSet(0x0, 0x7fffffff), Seq( 46 onChipPeripheralRange, 47 AddressSet(0x40600000L, 0xf), // UART 48 flashRange, 49 sdRange, 50 intrGenRange 51 )) 52 53 val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x10000000L, 0xfffffff)))) 54 val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xf)))) 55 // val vga = LazyModule(new AXI4VGA( 56 // sim = false, 57 // fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)), 58 // ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L)) 59 // )) 60 val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff)))) 61 val intrGen = LazyModule(new AXI4IntrGenerator(Seq(AddressSet(0x40070000L, 0x0000ffffL)))) 62 val error = LazyModule(new AXI4Error(illegalRange)) 63 64 val axiBus = AXI4Xbar() 65 66 uart.node := axiBus 67 // vga.node :*= axiBus 68 flash.node := axiBus 69 sd.node := axiBus 70 intrGen.node := axiBus 71 error.node := axiBus 72 73 axiBus := node 74 75 val io_axi4 = InModuleBody { 76 node.makeIOs() 77 } 78 79 class SimMMIOImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 80 val io = IO(new Bundle() { 81 val uart = new UARTIO 82 val interrupt = new IntrGenIO 83 }) 84 io.uart <> uart.module.io.extra.get 85 io.interrupt <> intrGen.module.io.extra.get 86 } 87 88 lazy val module = new SimMMIOImp(this) 89} 90