xref: /XiangShan/src/test/scala/top/SimMMIO.scala (revision 13cfb810f69eb8eb6e0e88373bfc763d35f9741c) 
1package top
2
3import chisel3._
4import chisel3.util._
5
6import bus.simplebus.SimpleBus
7
8class DeviceHelper extends BlackBox {
9  val io = IO(new Bundle {
10    val clk = Input(Clock())
11    val reqValid = Input(Bool())
12    val reqWen = Input(Bool())
13    val reqAddr = Input(UInt(32.W))
14    val reqWdata = Input(UInt(32.W))
15    val reqWmask = Input(UInt(4.W))
16    val respRdata = Output(UInt(32.W))
17  })
18}
19
20class SimMMIO extends Module {
21  val io = IO(new Bundle {
22    val rw = Flipped(new SimpleBus)
23    val mmioTrap = new Bundle {
24      val valid = Output(Bool())
25      val cmd = Output(UInt(3.W))
26      val rdata = Input(UInt(32.W))
27    }
28  })
29
30  val wen = io.rw.isWrite()
31  val wdataVec = VecInit.tabulate(4) { i => io.rw.req.bits.wdata(8 * (i + 1) - 1, 8 * i) }
32  val wmask = VecInit.tabulate(4) { i => io.rw.req.bits.wmask(i).toBool }
33
34  io.mmioTrap.valid := false.B
35  io.mmioTrap.cmd := 0.U
36
37  val helper = Module(new DeviceHelper)
38  helper.io.clk := clock
39  helper.io.reqValid := io.rw.req.valid
40  helper.io.reqWen := wen
41  helper.io.reqAddr := io.rw.req.bits.addr
42  helper.io.reqWdata := io.rw.req.bits.wdata
43  helper.io.reqWmask := io.rw.req.bits.wmask
44  io.rw.resp.bits.rdata := helper.io.respRdata
45
46  io.rw.req.ready := true.B
47  io.rw.resp.valid := RegNext(io.rw.req.valid)
48
49/*
50  when (io.rw.req.valid) {
51    switch (io.rw.req.bits.addr) {
52      is (0x40600008.U) {
53        // read uartlite stat register
54        io.mmioTrap.valid := true.B
55        io.mmioTrap.cmd := 0.U
56      }
57      is (0x4060000c.U) {
58        // read uartlite ctrl register
59        io.mmioTrap.valid := true.B
60        io.mmioTrap.cmd := 0.U
61      }
62      is (0x40600004.U) {
63        io.mmioTrap.valid := true.B
64        io.mmioTrap.cmd := 6.U
65        when (wen) { printf("%c", wdataVec(0)) }
66      }
67      is (0x40700000.U) {
68        // read RTC
69        io.mmioTrap.valid := true.B
70        io.mmioTrap.cmd := 1.U
71      }
72      is (0x40900000.U) {
73        // read key
74        io.mmioTrap.valid := true.B
75        io.mmioTrap.cmd := 2.U
76      }
77      is (0x40800000.U) {
78        // read screen size
79        io.mmioTrap.valid := true.B
80        io.mmioTrap.cmd := 3.U
81      }
82      is (0x40800004.U) {
83        // write vga sync
84        io.mmioTrap.valid := true.B
85        io.mmioTrap.cmd := 4.U
86      }
87    }
88
89    when (io.rw.req.bits.addr >= 0x40000000.U && io.rw.req.bits.addr < 0x40400000.U && wen) {
90      // write to vmem
91      io.mmioTrap.valid := true.B
92      io.mmioTrap.cmd := 5.U
93    }
94  }
95  */
96
97  //io.rw.req.ready := true.B
98  //io.rw.resp.bits.rdata := io.mmioTrap.rdata
99  //io.rw.resp.valid := io.mmioTrap.valid
100
101  //assert(!io.rw.req.valid || io.mmioTrap.valid, "bad addr = 0x%x", io.rw.req.bits.addr)
102}
103