xref: /XiangShan/src/test/scala/top/SimMMIO.scala (revision 0ccdef883ddc1d8a9558b2c486df3b51599fbc85) 
1package top
2
3import chisel3._
4import chipsalliance.rocketchip.config
5import device._
6import freechips.rocketchip.amba.axi4.{AXI4MasterParameters, AXI4MasterPortParameters, AXI4SlaveNode, AXI4SlavePortParameters, AXI4Xbar}
7import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
8import freechips.rocketchip.tilelink.{TLMasterParameters, TLXbar}
9
10class SimMMIO()(implicit p: config.Parameters) extends LazyModule {
11
12  val uart = LazyModule(new AXI4UART(AddressSet(0x40600000L, 0xf)))
13  val vga = LazyModule(new AXI4VGA(
14    sim = false,
15    fbAddress = AddressSet(0x50000000L, 0x3fffffL),
16    ctrlAddress = AddressSet(0x40001000L, 0x7L)
17  ))
18  val flash = LazyModule(new AXI4Flash(AddressSet(0x40000000L, 0xfff)))
19  val sd = LazyModule(new AXI4DummySD(AddressSet(0x40002000L, 0xfff)))
20
21  val axiBus = AXI4Xbar()
22
23  uart.node := axiBus
24  vga.node :*= axiBus
25  flash.node := axiBus
26  sd.node := axiBus
27
28  lazy val module = new LazyModuleImp(this){
29    val io = IO(new Bundle() {
30      val uart = new UARTIO
31    })
32    io.uart <> uart.module.io.extra.get
33  }
34
35}
36
37
38//class SimMMIO(para: TLParameters) extends Module {
39//  val io = IO(new Bundle {
40//    val rw = Flipped(TLCached(para))
41//    val uart = new UARTIO
42//  })
43//
44//  val devAddrSpace = List(
45//    (0x40600000L, 0x10L), // uart
46//    (0x50000000L, 0x400000L), // vmem
47//    (0x40001000L, 0x8L),  // vga ctrl
48//    (0x40000000L, 0x1000L),  // flash
49//    (0x40002000L, 0x1000L)  // dummy sdcard
50//  )
51//
52//  val xbar = Module(new NaiveTL1toN(devAddrSpace, io.rw.params))
53//  xbar.io.in <> io.rw
54//
55//  val axiOut = xbar.io.out.map(tl => AXI4ToAXI4Lite(MMIOTLToAXI4(tl)))
56//
57//  val uart = Module(new AXI4UART)
58//  val vga = Module(new AXI4VGA(sim = true))
59//  val flash = Module(new AXI4Flash)
60//  val sd = Module(new AXI4DummySD)
61//
62//  uart.io.in <> axiOut(0)
63//  vga.io.in.fb <> axiOut(1)
64//  vga.io.in.ctrl <> axiOut(2)
65//  flash.io.in <> axiOut(3)
66//  sd.io.in <> axiOut(4)
67//  vga.io.vga := DontCare
68//  io.uart <> uart.io.extra.get
69//}
70