xref: /XiangShan/src/main/scala/xiangshan/transforms/Helpers.scala (revision e3da8bad334fc71ba0d72f0607e2e93245ddaece)
1*e3da8badSTang Haojin/***************************************************************************************
2*e3da8badSTang Haojin* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3*e3da8badSTang Haojin* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4*e3da8badSTang Haojin* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*e3da8badSTang Haojin*
6*e3da8badSTang Haojin* XiangShan is licensed under Mulan PSL v2.
7*e3da8badSTang Haojin* You can use this software according to the terms and conditions of the Mulan PSL v2.
8*e3da8badSTang Haojin* You may obtain a copy of Mulan PSL v2 at:
9*e3da8badSTang Haojin*          http://license.coscl.org.cn/MulanPSL2
10*e3da8badSTang Haojin*
11*e3da8badSTang Haojin* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12*e3da8badSTang Haojin* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13*e3da8badSTang Haojin* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*e3da8badSTang Haojin*
15*e3da8badSTang Haojin* See the Mulan PSL v2 for more details.
16*e3da8badSTang Haojin***************************************************************************************/
17*e3da8badSTang Haojin
18*e3da8badSTang Haojinpackage xiangshan.transforms
19*e3da8badSTang Haojin
20*e3da8badSTang Haojinobject Helpers {
21*e3da8badSTang Haojin
22*e3da8badSTang Haojin  implicit class CircuitHelper(circuit: firrtl.ir.Circuit) {
23*e3da8badSTang Haojin    def mapModule(f: firrtl.ir.DefModule => firrtl.ir.DefModule): firrtl.ir.Circuit = circuit.copy(modules = circuit.modules.map(f))
24*e3da8badSTang Haojin  }
25*e3da8badSTang Haojin
26*e3da8badSTang Haojin  implicit class DefModuleHelper(defModule: firrtl.ir.DefModule) {
27*e3da8badSTang Haojin    def mapStmt(f: firrtl.ir.Statement => firrtl.ir.Statement): firrtl.ir.DefModule = defModule match {
28*e3da8badSTang Haojin      case firrtl.ir.Module(info, name, ports, body) => firrtl.ir.Module(info, name, ports, f(body))
29*e3da8badSTang Haojin      case firrtl.ir.DefClass(info, name, ports, body) => firrtl.ir.DefClass(info, name, ports, f(body))
30*e3da8badSTang Haojin      case other: firrtl.ir.DefModule => other
31*e3da8badSTang Haojin    }
32*e3da8badSTang Haojin
33*e3da8badSTang Haojin    def foreachStmt(f: firrtl.ir.Statement => Unit): Unit = defModule match {
34*e3da8badSTang Haojin      case firrtl.ir.Module(_, _, _, body) => f(body)
35*e3da8badSTang Haojin      case firrtl.ir.DefClass(_, _, _, body) => f(body)
36*e3da8badSTang Haojin      case _: firrtl.ir.DefModule =>
37*e3da8badSTang Haojin    }
38*e3da8badSTang Haojin  }
39*e3da8badSTang Haojin
40*e3da8badSTang Haojin  implicit class StatementHelper(statement: firrtl.ir.Statement) {
41*e3da8badSTang Haojin    def mapStmt(f: firrtl.ir.Statement => firrtl.ir.Statement): firrtl.ir.Statement = statement match {
42*e3da8badSTang Haojin      case firrtl.ir.Conditionally(info, pred, conseq, alt) => firrtl.ir.Conditionally(info, pred, f(conseq), f(alt))
43*e3da8badSTang Haojin      case firrtl.ir.Block(stmts) =>
44*e3da8badSTang Haojin        val res = new scala.collection.mutable.ArrayBuffer[firrtl.ir.Statement]()
45*e3da8badSTang Haojin        var its = stmts.iterator :: Nil
46*e3da8badSTang Haojin        while (its.nonEmpty) {
47*e3da8badSTang Haojin          val it = its.head
48*e3da8badSTang Haojin          if (it.hasNext) {
49*e3da8badSTang Haojin            it.next() match {
50*e3da8badSTang Haojin              case firrtl.ir.EmptyStmt => // flatten out
51*e3da8badSTang Haojin              case b: firrtl.ir.Block =>
52*e3da8badSTang Haojin                its = b.stmts.iterator :: its
53*e3da8badSTang Haojin              case other =>
54*e3da8badSTang Haojin                res.append(f(other))
55*e3da8badSTang Haojin            }
56*e3da8badSTang Haojin          } else {
57*e3da8badSTang Haojin            its = its.tail
58*e3da8badSTang Haojin          }
59*e3da8badSTang Haojin        }
60*e3da8badSTang Haojin        firrtl.ir.Block(res.toSeq)
61*e3da8badSTang Haojin      case other: firrtl.ir.Statement => other
62*e3da8badSTang Haojin    }
63*e3da8badSTang Haojin  }
64*e3da8badSTang Haojin}
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