1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27import xiangshan.backend.decode.{Imm, ImmUnion} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 def no = "b000".U // this src read no reg but cannot be Any value 37 38 // alias 39 def reg = this.xp 40 def DC = imm // Don't Care 41 def X = BitPat("b000") 42 43 def isPc(srcType: UInt) = srcType===pc 44 def isImm(srcType: UInt) = srcType===imm 45 def isReg(srcType: UInt) = srcType(0) 46 def isXp(srcType: UInt) = srcType(0) 47 def isFp(srcType: UInt) = srcType(1) 48 def isVp(srcType: UInt) = srcType(2) 49 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 50 def isNotReg(srcType: UInt): Bool = !srcType.orR 51 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 61 def isReady(state: UInt): Bool = state === this.rdy 62 def isBusy(state: UInt): Bool = state === this.busy 63 } 64 65 def FuOpTypeWidth = 9 66 object FuOpType { 67 def apply() = UInt(FuOpTypeWidth.W) 68 def X = BitPat("b00000000") 69 } 70 71 object VlduType { 72 // bit encoding: | padding (2bit) || mop (2bit) | lumop(5bit) | 73 // only unit-stride use lumop 74 // mop [1:0] 75 // 0 0 : unit-stride 76 // 0 1 : indexed-unordered 77 // 1 0 : strided 78 // 1 1 : indexed-ordered 79 // lumop[4:0] 80 // 0 0 0 0 0 : unit-stride load 81 // 0 1 0 0 0 : unit-stride, whole register load 82 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 83 // 1 0 0 0 0 : unit-stride fault-only-first 84 def vle = "b00_00_00000".U 85 def vlr = "b00_00_01000".U 86 def vlm = "b00_00_01011".U 87 def vleff = "b00_00_10000".U 88 def vluxe = "b00_01_00000".U 89 def vlse = "b00_10_00000".U 90 def vloxe = "b00_11_00000".U 91 92 def isStrided(fuOpType: UInt): Bool = fuOpType === vlse 93 def isIndexed(fuOpType: UInt): Bool = fuOpType === vluxe || fuOpType === vloxe 94 } 95 96 object VstuType { 97 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 98 // only unit-stride use sumop 99 // mop [1:0] 100 // 0 0 : unit-stride 101 // 0 1 : indexed-unordered 102 // 1 0 : strided 103 // 1 1 : indexed-ordered 104 // sumop[4:0] 105 // 0 0 0 0 0 : unit-stride load 106 // 0 1 0 0 0 : unit-stride, whole register load 107 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 108 def vse = "b00_00_00000".U 109 def vsr = "b00_00_01000".U 110 def vsm = "b00_00_01011".U 111 def vsuxe = "b00_01_00000".U 112 def vsse = "b00_10_00000".U 113 def vsoxe = "b00_11_00000".U 114 115 def isStrided(fuOpType: UInt): Bool = fuOpType === vsse 116 def isIndexed(fuOpType: UInt): Bool = fuOpType === vsuxe || fuOpType === vsoxe 117 } 118 119 object IF2VectorType { 120 // use last 2 bits for vsew 121 def iDup2Vec = "b1_00".U 122 def fDup2Vec = "b1_01".U 123 def immDup2Vec = "b1_10".U 124 def i2Vec = "b0_00".U 125 def f2Vec = "b0_01".U 126 def imm2Vec = "b0_10".U 127 def needDup(bits: UInt): Bool = bits(2) 128 def isImm(bits: UInt): Bool = bits(1) 129 } 130 131 object CommitType { 132 def NORMAL = "b000".U // int/fp 133 def BRANCH = "b001".U // branch 134 def LOAD = "b010".U // load 135 def STORE = "b011".U // store 136 137 def apply() = UInt(3.W) 138 def isFused(commitType: UInt): Bool = commitType(2) 139 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 140 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 141 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 142 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 143 } 144 145 object RedirectLevel { 146 def flushAfter = "b0".U 147 def flush = "b1".U 148 149 def apply() = UInt(1.W) 150 // def isUnconditional(level: UInt) = level(1) 151 def flushItself(level: UInt) = level(0) 152 // def isException(level: UInt) = level(1) && level(0) 153 } 154 155 object ExceptionVec { 156 val ExceptionVecSize = 16 157 def apply() = Vec(ExceptionVecSize, Bool()) 158 } 159 160 object PMAMode { 161 def R = "b1".U << 0 //readable 162 def W = "b1".U << 1 //writeable 163 def X = "b1".U << 2 //executable 164 def I = "b1".U << 3 //cacheable: icache 165 def D = "b1".U << 4 //cacheable: dcache 166 def S = "b1".U << 5 //enable speculative access 167 def A = "b1".U << 6 //enable atomic operation, A imply R & W 168 def C = "b1".U << 7 //if it is cacheable is configable 169 def Reserved = "b0".U 170 171 def apply() = UInt(7.W) 172 173 def read(mode: UInt) = mode(0) 174 def write(mode: UInt) = mode(1) 175 def execute(mode: UInt) = mode(2) 176 def icache(mode: UInt) = mode(3) 177 def dcache(mode: UInt) = mode(4) 178 def speculate(mode: UInt) = mode(5) 179 def atomic(mode: UInt) = mode(6) 180 def configable_cache(mode: UInt) = mode(7) 181 182 def strToMode(s: String) = { 183 var result = 0.U(8.W) 184 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 185 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 186 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 187 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 188 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 189 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 190 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 191 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 192 result 193 } 194 } 195 196 197 object CSROpType { 198 def jmp = "b000".U 199 def wrt = "b001".U 200 def set = "b010".U 201 def clr = "b011".U 202 def wfi = "b100".U 203 def wrti = "b101".U 204 def seti = "b110".U 205 def clri = "b111".U 206 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 207 } 208 209 // jump 210 object JumpOpType { 211 def jal = "b00".U 212 def jalr = "b01".U 213 def auipc = "b10".U 214// def call = "b11_011".U 215// def ret = "b11_100".U 216 def jumpOpisJalr(op: UInt) = op(0) 217 def jumpOpisAuipc(op: UInt) = op(1) 218 } 219 220 object FenceOpType { 221 def fence = "b10000".U 222 def sfence = "b10001".U 223 def fencei = "b10010".U 224 def nofence= "b00000".U 225 } 226 227 object ALUOpType { 228 // shift optype 229 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 230 def sll = "b000_0001".U // sll: src1 << src2 231 232 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 233 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 234 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 235 236 def srl = "b000_0101".U // srl: src1 >> src2 237 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 238 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 239 240 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 241 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 242 243 // RV64 32bit optype 244 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 245 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 246 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 247 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 248 249 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 250 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 251 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 252 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 253 254 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 255 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 256 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 257 def rolw = "b001_1100".U 258 def rorw = "b001_1101".U 259 260 // ADD-op 261 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 262 def add = "b010_0001".U // add: src1 + src2 263 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 264 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 265 266 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 267 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 268 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 269 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 270 271 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 272 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 273 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 274 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 275 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 276 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 277 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 278 279 // SUB-op: src1 - src2 280 def sub = "b011_0000".U 281 def sltu = "b011_0001".U 282 def slt = "b011_0010".U 283 def maxu = "b011_0100".U 284 def minu = "b011_0101".U 285 def max = "b011_0110".U 286 def min = "b011_0111".U 287 288 // branch 289 def beq = "b111_0000".U 290 def bne = "b111_0010".U 291 def blt = "b111_1000".U 292 def bge = "b111_1010".U 293 def bltu = "b111_1100".U 294 def bgeu = "b111_1110".U 295 296 // misc optype 297 def and = "b100_0000".U 298 def andn = "b100_0001".U 299 def or = "b100_0010".U 300 def orn = "b100_0011".U 301 def xor = "b100_0100".U 302 def xnor = "b100_0101".U 303 def orcb = "b100_0110".U 304 305 def sextb = "b100_1000".U 306 def packh = "b100_1001".U 307 def sexth = "b100_1010".U 308 def packw = "b100_1011".U 309 310 def revb = "b101_0000".U 311 def rev8 = "b101_0001".U 312 def pack = "b101_0010".U 313 def orh48 = "b101_0011".U 314 315 def szewl1 = "b101_1000".U 316 def szewl2 = "b101_1001".U 317 def szewl3 = "b101_1010".U 318 def byte2 = "b101_1011".U 319 320 def andlsb = "b110_0000".U 321 def andzexth = "b110_0001".U 322 def orlsb = "b110_0010".U 323 def orzexth = "b110_0011".U 324 def xorlsb = "b110_0100".U 325 def xorzexth = "b110_0101".U 326 def orcblsb = "b110_0110".U 327 def orcbzexth = "b110_0111".U 328 329 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 330 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 331 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 332 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 333 334 def apply() = UInt(FuOpTypeWidth.W) 335 } 336 337 object VSETOpType { 338 val setVlmaxBit = 0 339 val keepVlBit = 1 340 // destTypeBit == 0: write vl to rd 341 // destTypeBit == 1: write vconfig 342 val destTypeBit = 5 343 344 // vsetvli's uop 345 // rs1!=x0, normal 346 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 347 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 348 def uvsetvcfg_xi = "b1010_0000".U 349 def uvsetrd_xi = "b1000_0000".U 350 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 351 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 352 // uop1: w(rd) | vlmax, vtypei -> x[rd] 353 def uvsetvcfg_vlmax_i = "b1010_0001".U 354 def uvsetrd_vlmax_i = "b1000_0001".U 355 // rs1==x0, rd==x0, keep vl, set vtype 356 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 357 def uvsetvcfg_keep_v = "b1010_0010".U 358 359 // vsetvl's uop 360 // rs1!=x0, normal 361 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 362 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 363 def uvsetvcfg_xx = "b0110_0000".U 364 def uvsetrd_xx = "b0100_0000".U 365 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 366 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 367 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 368 def uvsetvcfg_vlmax_x = "b0110_0001".U 369 def uvsetrd_vlmax_x = "b0100_0001".U 370 // rs1==x0, rd==x0, keep vl, set vtype 371 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 372 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 373 def uvmv_v_x = "b0110_0010".U 374 def uvsetvcfg_vv = "b0111_0010".U 375 376 // vsetivli's uop 377 // uop0: w(vconfig) | vli, vtypei -> vconfig 378 // uop1: w(rd) | vli, vtypei -> x[rd] 379 def uvsetvcfg_ii = "b0010_0000".U 380 def uvsetrd_ii = "b0000_0000".U 381 382 def isVsetvl (func: UInt) = func(6) 383 def isVsetvli (func: UInt) = func(7) 384 def isVsetivli(func: UInt) = func(7, 6) === 0.U 385 def isNormal (func: UInt) = func(1, 0) === 0.U 386 def isSetVlmax(func: UInt) = func(setVlmaxBit) 387 def isKeepVl (func: UInt) = func(keepVlBit) 388 // RG: region 389 def writeIntRG(func: UInt) = !func(5) 390 def writeVecRG(func: UInt) = func(5) 391 def readIntRG (func: UInt) = !func(4) 392 def readVecRG (func: UInt) = func(4) 393 // modify fuOpType 394 def keepVl(func: UInt) = func | (1 << keepVlBit).U 395 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 396 } 397 398 object BRUOpType { 399 // branch 400 def beq = "b000_000".U 401 def bne = "b000_001".U 402 def blt = "b000_100".U 403 def bge = "b000_101".U 404 def bltu = "b001_000".U 405 def bgeu = "b001_001".U 406 407 def getBranchType(func: UInt) = func(3, 1) 408 def isBranchInvert(func: UInt) = func(0) 409 } 410 411 object MULOpType { 412 // mul 413 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 414 def mul = "b00000".U 415 def mulh = "b00001".U 416 def mulhsu = "b00010".U 417 def mulhu = "b00011".U 418 def mulw = "b00100".U 419 420 def mulw7 = "b01100".U 421 def isSign(op: UInt) = !op(1) 422 def isW(op: UInt) = op(2) 423 def isH(op: UInt) = op(1, 0) =/= 0.U 424 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 425 } 426 427 object DIVOpType { 428 // div 429 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 430 def div = "b10000".U 431 def divu = "b10010".U 432 def rem = "b10001".U 433 def remu = "b10011".U 434 435 def divw = "b10100".U 436 def divuw = "b10110".U 437 def remw = "b10101".U 438 def remuw = "b10111".U 439 440 def isSign(op: UInt) = !op(1) 441 def isW(op: UInt) = op(2) 442 def isH(op: UInt) = op(0) 443 } 444 445 object MDUOpType { 446 // mul 447 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 448 def mul = "b00000".U 449 def mulh = "b00001".U 450 def mulhsu = "b00010".U 451 def mulhu = "b00011".U 452 def mulw = "b00100".U 453 454 def mulw7 = "b01100".U 455 456 // div 457 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 458 def div = "b10000".U 459 def divu = "b10010".U 460 def rem = "b10001".U 461 def remu = "b10011".U 462 463 def divw = "b10100".U 464 def divuw = "b10110".U 465 def remw = "b10101".U 466 def remuw = "b10111".U 467 468 def isMul(op: UInt) = !op(4) 469 def isDiv(op: UInt) = op(4) 470 471 def isDivSign(op: UInt) = isDiv(op) && !op(1) 472 def isW(op: UInt) = op(2) 473 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 474 def getMulOp(op: UInt) = op(1, 0) 475 } 476 477 object LSUOpType { 478 // load pipeline 479 480 // normal load 481 // Note: bit(1, 0) are size, DO NOT CHANGE 482 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 483 def lb = "b0000".U 484 def lh = "b0001".U 485 def lw = "b0010".U 486 def ld = "b0011".U 487 def lbu = "b0100".U 488 def lhu = "b0101".U 489 def lwu = "b0110".U 490 491 // Zicbop software prefetch 492 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 493 def prefetch_i = "b1000".U // TODO 494 def prefetch_r = "b1001".U 495 def prefetch_w = "b1010".U 496 497 def isPrefetch(op: UInt): Bool = op(3) 498 499 // store pipeline 500 // normal store 501 // bit encoding: | store 00 | size(2bit) | 502 def sb = "b0000".U 503 def sh = "b0001".U 504 def sw = "b0010".U 505 def sd = "b0011".U 506 507 // l1 cache op 508 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 509 def cbo_zero = "b0111".U 510 511 // llc op 512 // bit encoding: | prefetch 11 | suboptype(2bit) | 513 def cbo_clean = "b1100".U 514 def cbo_flush = "b1101".U 515 def cbo_inval = "b1110".U 516 517 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 518 519 // atomics 520 // bit(1, 0) are size 521 // since atomics use a different fu type 522 // so we can safely reuse other load/store's encodings 523 // bit encoding: | optype(4bit) | size (2bit) | 524 def lr_w = "b000010".U 525 def sc_w = "b000110".U 526 def amoswap_w = "b001010".U 527 def amoadd_w = "b001110".U 528 def amoxor_w = "b010010".U 529 def amoand_w = "b010110".U 530 def amoor_w = "b011010".U 531 def amomin_w = "b011110".U 532 def amomax_w = "b100010".U 533 def amominu_w = "b100110".U 534 def amomaxu_w = "b101010".U 535 536 def lr_d = "b000011".U 537 def sc_d = "b000111".U 538 def amoswap_d = "b001011".U 539 def amoadd_d = "b001111".U 540 def amoxor_d = "b010011".U 541 def amoand_d = "b010111".U 542 def amoor_d = "b011011".U 543 def amomin_d = "b011111".U 544 def amomax_d = "b100011".U 545 def amominu_d = "b100111".U 546 def amomaxu_d = "b101011".U 547 548 def size(op: UInt) = op(1,0) 549 } 550 551 object BKUOpType { 552 553 def clmul = "b000000".U 554 def clmulh = "b000001".U 555 def clmulr = "b000010".U 556 def xpermn = "b000100".U 557 def xpermb = "b000101".U 558 559 def clz = "b001000".U 560 def clzw = "b001001".U 561 def ctz = "b001010".U 562 def ctzw = "b001011".U 563 def cpop = "b001100".U 564 def cpopw = "b001101".U 565 566 // 01xxxx is reserve 567 def aes64es = "b100000".U 568 def aes64esm = "b100001".U 569 def aes64ds = "b100010".U 570 def aes64dsm = "b100011".U 571 def aes64im = "b100100".U 572 def aes64ks1i = "b100101".U 573 def aes64ks2 = "b100110".U 574 575 // merge to two instruction sm4ks & sm4ed 576 def sm4ed0 = "b101000".U 577 def sm4ed1 = "b101001".U 578 def sm4ed2 = "b101010".U 579 def sm4ed3 = "b101011".U 580 def sm4ks0 = "b101100".U 581 def sm4ks1 = "b101101".U 582 def sm4ks2 = "b101110".U 583 def sm4ks3 = "b101111".U 584 585 def sha256sum0 = "b110000".U 586 def sha256sum1 = "b110001".U 587 def sha256sig0 = "b110010".U 588 def sha256sig1 = "b110011".U 589 def sha512sum0 = "b110100".U 590 def sha512sum1 = "b110101".U 591 def sha512sig0 = "b110110".U 592 def sha512sig1 = "b110111".U 593 594 def sm3p0 = "b111000".U 595 def sm3p1 = "b111001".U 596 } 597 598 object BTBtype { 599 def B = "b00".U // branch 600 def J = "b01".U // jump 601 def I = "b10".U // indirect 602 def R = "b11".U // return 603 604 def apply() = UInt(2.W) 605 } 606 607 object SelImm { 608 def IMM_X = "b0111".U 609 def IMM_S = "b1110".U 610 def IMM_SB = "b0001".U 611 def IMM_U = "b0010".U 612 def IMM_UJ = "b0011".U 613 def IMM_I = "b0100".U 614 def IMM_Z = "b0101".U 615 def INVALID_INSTR = "b0110".U 616 def IMM_B6 = "b1000".U 617 618 def IMM_OPIVIS = "b1001".U 619 def IMM_OPIVIU = "b1010".U 620 def IMM_VSETVLI = "b1100".U 621 def IMM_VSETIVLI = "b1101".U 622 def IMM_LUI32 = "b1011".U 623 624 def X = BitPat("b0000") 625 626 def apply() = UInt(4.W) 627 628 def mkString(immType: UInt) : String = { 629 val strMap = Map( 630 IMM_S.litValue -> "S", 631 IMM_SB.litValue -> "SB", 632 IMM_U.litValue -> "U", 633 IMM_UJ.litValue -> "UJ", 634 IMM_I.litValue -> "I", 635 IMM_Z.litValue -> "Z", 636 IMM_B6.litValue -> "B6", 637 IMM_OPIVIS.litValue -> "VIS", 638 IMM_OPIVIU.litValue -> "VIU", 639 IMM_VSETVLI.litValue -> "VSETVLI", 640 IMM_VSETIVLI.litValue -> "VSETIVLI", 641 IMM_LUI32.litValue -> "LUI32", 642 INVALID_INSTR.litValue -> "INVALID", 643 ) 644 strMap(immType.litValue) 645 } 646 647 def getImmUnion(immType: UInt) : Imm = { 648 val iuMap = Map( 649 IMM_S.litValue -> ImmUnion.S, 650 IMM_SB.litValue -> ImmUnion.B, 651 IMM_U.litValue -> ImmUnion.U, 652 IMM_UJ.litValue -> ImmUnion.J, 653 IMM_I.litValue -> ImmUnion.I, 654 IMM_Z.litValue -> ImmUnion.Z, 655 IMM_B6.litValue -> ImmUnion.B6, 656 IMM_OPIVIS.litValue -> ImmUnion.OPIVIS, 657 IMM_OPIVIU.litValue -> ImmUnion.OPIVIU, 658 IMM_VSETVLI.litValue -> ImmUnion.VSETVLI, 659 IMM_VSETIVLI.litValue -> ImmUnion.VSETIVLI, 660 IMM_LUI32.litValue -> ImmUnion.LUI32, 661 ) 662 iuMap(immType.litValue) 663 } 664 } 665 666 object UopSplitType { 667 def SCA_SIM = "b000000".U // 668 def VSET = "b010001".U // dirty: vset 669 def VEC_VVV = "b010010".U // VEC_VVV 670 def VEC_VXV = "b010011".U // VEC_VXV 671 def VEC_0XV = "b010100".U // VEC_0XV 672 def VEC_VVW = "b010101".U // VEC_VVW 673 def VEC_WVW = "b010110".U // VEC_WVW 674 def VEC_VXW = "b010111".U // VEC_VXW 675 def VEC_WXW = "b011000".U // VEC_WXW 676 def VEC_WVV = "b011001".U // VEC_WVV 677 def VEC_WXV = "b011010".U // VEC_WXV 678 def VEC_EXT2 = "b011011".U // VF2 0 -> V 679 def VEC_EXT4 = "b011100".U // VF4 0 -> V 680 def VEC_EXT8 = "b011101".U // VF8 0 -> V 681 def VEC_VVM = "b011110".U // VEC_VVM 682 def VEC_VXM = "b011111".U // VEC_VXM 683 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 684 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 685 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 686 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 687 def VEC_VRED = "b100100".U // VEC_VRED 688 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 689 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 690 def VEC_M0X = "b101001".U // VEC_M0X 0MV 691 def VEC_MVV = "b101010".U // VEC_MVV VMV 692 def VEC_M0X_VFIRST = "b101011".U // 693 def VEC_VWW = "b101100".U // 694 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 695 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 696 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 697 def VEC_COMPRESS = "b110000".U // vcompress.vm 698 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 699 def VEC_S_LDST = "b110010".U // vector strided load/store 700 def VEC_I_LDST = "b110011".U // vector indexed load/store 701 def VEC_VFV = "b111000".U // VEC_VFV 702 def VEC_VFW = "b111001".U // VEC_VFW 703 def VEC_WFW = "b111010".U // VEC_WVW 704 def VEC_VFM = "b111011".U // VEC_VFM 705 def VEC_VFRED = "b111100".U // VEC_VFRED 706 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 707 def VEC_M0M = "b000000".U // VEC_M0M 708 def VEC_MMM = "b000000".U // VEC_MMM 709 def VEC_MVNR = "b000100".U // vmvnr 710 def dummy = "b111111".U 711 712 def X = BitPat("b000000") 713 714 def apply() = UInt(6.W) 715 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 716 } 717 718 object ExceptionNO { 719 def instrAddrMisaligned = 0 720 def instrAccessFault = 1 721 def illegalInstr = 2 722 def breakPoint = 3 723 def loadAddrMisaligned = 4 724 def loadAccessFault = 5 725 def storeAddrMisaligned = 6 726 def storeAccessFault = 7 727 def ecallU = 8 728 def ecallS = 9 729 def ecallM = 11 730 def instrPageFault = 12 731 def loadPageFault = 13 732 // def singleStep = 14 733 def storePageFault = 15 734 def priorities = Seq( 735 breakPoint, // TODO: different BP has different priority 736 instrPageFault, 737 instrAccessFault, 738 illegalInstr, 739 instrAddrMisaligned, 740 ecallM, ecallS, ecallU, 741 storeAddrMisaligned, 742 loadAddrMisaligned, 743 storePageFault, 744 loadPageFault, 745 storeAccessFault, 746 loadAccessFault 747 ) 748 def all = priorities.distinct.sorted 749 def frontendSet = Seq( 750 instrAddrMisaligned, 751 instrAccessFault, 752 illegalInstr, 753 instrPageFault 754 ) 755 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 756 val new_vec = Wire(ExceptionVec()) 757 new_vec.foreach(_ := false.B) 758 select.foreach(i => new_vec(i) := vec(i)) 759 new_vec 760 } 761 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 762 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 763 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 764 partialSelect(vec, fuConfig.exceptionOut) 765 } 766 767 object TopDownCounters extends Enumeration { 768 val NoStall = Value("NoStall") // Base 769 // frontend 770 val OverrideBubble = Value("OverrideBubble") 771 val FtqUpdateBubble = Value("FtqUpdateBubble") 772 // val ControlRedirectBubble = Value("ControlRedirectBubble") 773 val TAGEMissBubble = Value("TAGEMissBubble") 774 val SCMissBubble = Value("SCMissBubble") 775 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 776 val RASMissBubble = Value("RASMissBubble") 777 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 778 val OtherRedirectBubble = Value("OtherRedirectBubble") 779 val FtqFullStall = Value("FtqFullStall") 780 781 val ICacheMissBubble = Value("ICacheMissBubble") 782 val ITLBMissBubble = Value("ITLBMissBubble") 783 val BTBMissBubble = Value("BTBMissBubble") 784 val FetchFragBubble = Value("FetchFragBubble") 785 786 // backend 787 // long inst stall at rob head 788 val DivStall = Value("DivStall") // int div, float div/sqrt 789 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 790 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 791 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 792 // freelist full 793 val IntFlStall = Value("IntFlStall") 794 val FpFlStall = Value("FpFlStall") 795 // dispatch queue full 796 val IntDqStall = Value("IntDqStall") 797 val FpDqStall = Value("FpDqStall") 798 val LsDqStall = Value("LsDqStall") 799 800 // memblock 801 val LoadTLBStall = Value("LoadTLBStall") 802 val LoadL1Stall = Value("LoadL1Stall") 803 val LoadL2Stall = Value("LoadL2Stall") 804 val LoadL3Stall = Value("LoadL3Stall") 805 val LoadMemStall = Value("LoadMemStall") 806 val StoreStall = Value("StoreStall") // include store tlb miss 807 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 808 809 // xs replay (different to gem5) 810 val LoadVioReplayStall = Value("LoadVioReplayStall") 811 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 812 813 // bad speculation 814 val ControlRecoveryStall = Value("ControlRecoveryStall") 815 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 816 val OtherRecoveryStall = Value("OtherRecoveryStall") 817 818 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 819 820 val OtherCoreStall = Value("OtherCoreStall") 821 822 val NumStallReasons = Value("NumStallReasons") 823 } 824} 825