1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27import xiangshan.backend.decode.{Imm, ImmUnion} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 def no = "b000".U // this src read no reg but cannot be Any value 37 38 // alias 39 def reg = this.xp 40 def DC = imm // Don't Care 41 def X = BitPat("b000") 42 43 def isPc(srcType: UInt) = srcType===pc 44 def isImm(srcType: UInt) = srcType===imm 45 def isReg(srcType: UInt) = srcType(0) 46 def isXp(srcType: UInt) = srcType(0) 47 def isFp(srcType: UInt) = srcType(1) 48 def isVp(srcType: UInt) = srcType(2) 49 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 50 def isNotReg(srcType: UInt): Bool = !srcType.orR 51 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 61 def isReady(state: UInt): Bool = state === this.rdy 62 def isBusy(state: UInt): Bool = state === this.busy 63 } 64 65 def FuOpTypeWidth = 9 66 object FuOpType { 67 def apply() = UInt(FuOpTypeWidth.W) 68 def X = BitPat("b0_0000_0000") 69 def FMVXF = BitPat("b1_1000_0000") //for fmv_x_d & fmv_x_w 70 } 71 72 object VlduType { 73 // bit encoding: | padding (2bit) || mop (2bit) | lumop(5bit) | 74 // only unit-stride use lumop 75 // mop [1:0] 76 // 0 0 : unit-stride 77 // 0 1 : indexed-unordered 78 // 1 0 : strided 79 // 1 1 : indexed-ordered 80 // lumop[4:0] 81 // 0 0 0 0 0 : unit-stride load 82 // 0 1 0 0 0 : unit-stride, whole register load 83 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 84 // 1 0 0 0 0 : unit-stride fault-only-first 85 def vle = "b00_00_00000".U 86 def vlr = "b00_00_01000".U 87 def vlm = "b00_00_01011".U 88 def vleff = "b00_00_10000".U 89 def vluxe = "b00_01_00000".U 90 def vlse = "b00_10_00000".U 91 def vloxe = "b00_11_00000".U 92 93 def isStrided(fuOpType: UInt): Bool = fuOpType === vlse 94 def isIndexed(fuOpType: UInt): Bool = fuOpType === vluxe || fuOpType === vloxe 95 def isMasked(fuOpType: UInt): Bool = fuOpType === vlm 96 } 97 98 object VstuType { 99 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 100 // only unit-stride use sumop 101 // mop [1:0] 102 // 0 0 : unit-stride 103 // 0 1 : indexed-unordered 104 // 1 0 : strided 105 // 1 1 : indexed-ordered 106 // sumop[4:0] 107 // 0 0 0 0 0 : unit-stride load 108 // 0 1 0 0 0 : unit-stride, whole register load 109 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 110 def vse = "b00_00_00000".U 111 def vsr = "b00_00_01000".U 112 def vsm = "b00_00_01011".U 113 def vsuxe = "b00_01_00000".U 114 def vsse = "b00_10_00000".U 115 def vsoxe = "b00_11_00000".U 116 117 def isStrided(fuOpType: UInt): Bool = fuOpType === vsse 118 def isIndexed(fuOpType: UInt): Bool = fuOpType === vsuxe || fuOpType === vsoxe 119 } 120 121 object IF2VectorType { 122 // use last 2 bits for vsew 123 def iDup2Vec = "b1_00".U 124 def fDup2Vec = "b1_00".U 125 def immDup2Vec = "b1_10".U 126 def i2Vec = "b0_00".U 127 def f2Vec = "b0_01".U 128 def imm2Vec = "b0_10".U 129 def needDup(bits: UInt): Bool = bits(2) 130 def isImm(bits: UInt): Bool = bits(1) 131 def isFmv(bits: UInt): Bool = bits(0) 132 def FMX_D_X = "b0_01_11".U 133 def FMX_W_X = "b0_01_10".U 134 } 135 136 object CommitType { 137 def NORMAL = "b000".U // int/fp 138 def BRANCH = "b001".U // branch 139 def LOAD = "b010".U // load 140 def STORE = "b011".U // store 141 142 def apply() = UInt(3.W) 143 def isFused(commitType: UInt): Bool = commitType(2) 144 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 145 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 146 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 147 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 148 } 149 150 object RedirectLevel { 151 def flushAfter = "b0".U 152 def flush = "b1".U 153 154 def apply() = UInt(1.W) 155 // def isUnconditional(level: UInt) = level(1) 156 def flushItself(level: UInt) = level(0) 157 // def isException(level: UInt) = level(1) && level(0) 158 } 159 160 object ExceptionVec { 161 val ExceptionVecSize = 16 162 def apply() = Vec(ExceptionVecSize, Bool()) 163 } 164 165 object PMAMode { 166 def R = "b1".U << 0 //readable 167 def W = "b1".U << 1 //writeable 168 def X = "b1".U << 2 //executable 169 def I = "b1".U << 3 //cacheable: icache 170 def D = "b1".U << 4 //cacheable: dcache 171 def S = "b1".U << 5 //enable speculative access 172 def A = "b1".U << 6 //enable atomic operation, A imply R & W 173 def C = "b1".U << 7 //if it is cacheable is configable 174 def Reserved = "b0".U 175 176 def apply() = UInt(7.W) 177 178 def read(mode: UInt) = mode(0) 179 def write(mode: UInt) = mode(1) 180 def execute(mode: UInt) = mode(2) 181 def icache(mode: UInt) = mode(3) 182 def dcache(mode: UInt) = mode(4) 183 def speculate(mode: UInt) = mode(5) 184 def atomic(mode: UInt) = mode(6) 185 def configable_cache(mode: UInt) = mode(7) 186 187 def strToMode(s: String) = { 188 var result = 0.U(8.W) 189 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 190 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 191 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 192 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 193 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 194 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 195 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 196 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 197 result 198 } 199 } 200 201 202 object CSROpType { 203 def jmp = "b000".U 204 def wrt = "b001".U 205 def set = "b010".U 206 def clr = "b011".U 207 def wfi = "b100".U 208 def wrti = "b101".U 209 def seti = "b110".U 210 def clri = "b111".U 211 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 212 } 213 214 // jump 215 object JumpOpType { 216 def jal = "b00".U 217 def jalr = "b01".U 218 def auipc = "b10".U 219// def call = "b11_011".U 220// def ret = "b11_100".U 221 def jumpOpisJalr(op: UInt) = op(0) 222 def jumpOpisAuipc(op: UInt) = op(1) 223 } 224 225 object FenceOpType { 226 def fence = "b10000".U 227 def sfence = "b10001".U 228 def fencei = "b10010".U 229 def nofence= "b00000".U 230 } 231 232 object ALUOpType { 233 // shift optype 234 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 235 def sll = "b000_0001".U // sll: src1 << src2 236 237 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 238 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 239 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 240 241 def srl = "b000_0101".U // srl: src1 >> src2 242 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 243 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 244 245 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 246 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 247 248 // RV64 32bit optype 249 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 250 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 251 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 252 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 253 254 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 255 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 256 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 257 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 258 259 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 260 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 261 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 262 def rolw = "b001_1100".U 263 def rorw = "b001_1101".U 264 265 // ADD-op 266 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 267 def add = "b010_0001".U // add: src1 + src2 268 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 269 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 270 271 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 272 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 273 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 274 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 275 276 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 277 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 278 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 279 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 280 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 281 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 282 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 283 284 // SUB-op: src1 - src2 285 def sub = "b011_0000".U 286 def sltu = "b011_0001".U 287 def slt = "b011_0010".U 288 def maxu = "b011_0100".U 289 def minu = "b011_0101".U 290 def max = "b011_0110".U 291 def min = "b011_0111".U 292 293 // branch 294 def beq = "b111_0000".U 295 def bne = "b111_0010".U 296 def blt = "b111_1000".U 297 def bge = "b111_1010".U 298 def bltu = "b111_1100".U 299 def bgeu = "b111_1110".U 300 301 // misc optype 302 def and = "b100_0000".U 303 def andn = "b100_0001".U 304 def or = "b100_0010".U 305 def orn = "b100_0011".U 306 def xor = "b100_0100".U 307 def xnor = "b100_0101".U 308 def orcb = "b100_0110".U 309 310 def sextb = "b100_1000".U 311 def packh = "b100_1001".U 312 def sexth = "b100_1010".U 313 def packw = "b100_1011".U 314 315 def revb = "b101_0000".U 316 def rev8 = "b101_0001".U 317 def pack = "b101_0010".U 318 def orh48 = "b101_0011".U 319 320 def szewl1 = "b101_1000".U 321 def szewl2 = "b101_1001".U 322 def szewl3 = "b101_1010".U 323 def byte2 = "b101_1011".U 324 325 def andlsb = "b110_0000".U 326 def andzexth = "b110_0001".U 327 def orlsb = "b110_0010".U 328 def orzexth = "b110_0011".U 329 def xorlsb = "b110_0100".U 330 def xorzexth = "b110_0101".U 331 def orcblsb = "b110_0110".U 332 def orcbzexth = "b110_0111".U 333 334 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 335 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 336 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 337 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 338 339 def apply() = UInt(FuOpTypeWidth.W) 340 } 341 342 object VSETOpType { 343 val setVlmaxBit = 0 344 val keepVlBit = 1 345 // destTypeBit == 0: write vl to rd 346 // destTypeBit == 1: write vconfig 347 val destTypeBit = 5 348 349 // vsetvli's uop 350 // rs1!=x0, normal 351 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 352 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 353 def uvsetvcfg_xi = "b1010_0000".U 354 def uvsetrd_xi = "b1000_0000".U 355 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 356 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 357 // uop1: w(rd) | vlmax, vtypei -> x[rd] 358 def uvsetvcfg_vlmax_i = "b1010_0001".U 359 def uvsetrd_vlmax_i = "b1000_0001".U 360 // rs1==x0, rd==x0, keep vl, set vtype 361 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 362 def uvsetvcfg_keep_v = "b1010_0010".U 363 364 // vsetvl's uop 365 // rs1!=x0, normal 366 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 367 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 368 def uvsetvcfg_xx = "b0110_0000".U 369 def uvsetrd_xx = "b0100_0000".U 370 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 371 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 372 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 373 def uvsetvcfg_vlmax_x = "b0110_0001".U 374 def uvsetrd_vlmax_x = "b0100_0001".U 375 // rs1==x0, rd==x0, keep vl, set vtype 376 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 377 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 378 def uvmv_v_x = "b0110_0010".U 379 def uvsetvcfg_vv = "b0111_0010".U 380 381 // vsetivli's uop 382 // uop0: w(vconfig) | vli, vtypei -> vconfig 383 // uop1: w(rd) | vli, vtypei -> x[rd] 384 def uvsetvcfg_ii = "b0010_0000".U 385 def uvsetrd_ii = "b0000_0000".U 386 387 def isVsetvl (func: UInt) = func(6) 388 def isVsetvli (func: UInt) = func(7) 389 def isVsetivli(func: UInt) = func(7, 6) === 0.U 390 def isNormal (func: UInt) = func(1, 0) === 0.U 391 def isSetVlmax(func: UInt) = func(setVlmaxBit) 392 def isKeepVl (func: UInt) = func(keepVlBit) 393 // RG: region 394 def writeIntRG(func: UInt) = !func(5) 395 def writeVecRG(func: UInt) = func(5) 396 def readIntRG (func: UInt) = !func(4) 397 def readVecRG (func: UInt) = func(4) 398 // modify fuOpType 399 def keepVl(func: UInt) = func | (1 << keepVlBit).U 400 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 401 } 402 403 object BRUOpType { 404 // branch 405 def beq = "b000_000".U 406 def bne = "b000_001".U 407 def blt = "b000_100".U 408 def bge = "b000_101".U 409 def bltu = "b001_000".U 410 def bgeu = "b001_001".U 411 412 def getBranchType(func: UInt) = func(3, 1) 413 def isBranchInvert(func: UInt) = func(0) 414 } 415 416 object MULOpType { 417 // mul 418 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 419 def mul = "b00000".U 420 def mulh = "b00001".U 421 def mulhsu = "b00010".U 422 def mulhu = "b00011".U 423 def mulw = "b00100".U 424 425 def mulw7 = "b01100".U 426 def isSign(op: UInt) = !op(1) 427 def isW(op: UInt) = op(2) 428 def isH(op: UInt) = op(1, 0) =/= 0.U 429 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 430 } 431 432 object DIVOpType { 433 // div 434 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 435 def div = "b10000".U 436 def divu = "b10010".U 437 def rem = "b10001".U 438 def remu = "b10011".U 439 440 def divw = "b10100".U 441 def divuw = "b10110".U 442 def remw = "b10101".U 443 def remuw = "b10111".U 444 445 def isSign(op: UInt) = !op(1) 446 def isW(op: UInt) = op(2) 447 def isH(op: UInt) = op(0) 448 } 449 450 object MDUOpType { 451 // mul 452 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 453 def mul = "b00000".U 454 def mulh = "b00001".U 455 def mulhsu = "b00010".U 456 def mulhu = "b00011".U 457 def mulw = "b00100".U 458 459 def mulw7 = "b01100".U 460 461 // div 462 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 463 def div = "b10000".U 464 def divu = "b10010".U 465 def rem = "b10001".U 466 def remu = "b10011".U 467 468 def divw = "b10100".U 469 def divuw = "b10110".U 470 def remw = "b10101".U 471 def remuw = "b10111".U 472 473 def isMul(op: UInt) = !op(4) 474 def isDiv(op: UInt) = op(4) 475 476 def isDivSign(op: UInt) = isDiv(op) && !op(1) 477 def isW(op: UInt) = op(2) 478 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 479 def getMulOp(op: UInt) = op(1, 0) 480 } 481 482 object LSUOpType { 483 // load pipeline 484 485 // normal load 486 // Note: bit(1, 0) are size, DO NOT CHANGE 487 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 488 def lb = "b0000".U 489 def lh = "b0001".U 490 def lw = "b0010".U 491 def ld = "b0011".U 492 def lbu = "b0100".U 493 def lhu = "b0101".U 494 def lwu = "b0110".U 495 496 // Zicbop software prefetch 497 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 498 def prefetch_i = "b1000".U // TODO 499 def prefetch_r = "b1001".U 500 def prefetch_w = "b1010".U 501 502 def isPrefetch(op: UInt): Bool = op(3) 503 504 // store pipeline 505 // normal store 506 // bit encoding: | store 00 | size(2bit) | 507 def sb = "b0000".U 508 def sh = "b0001".U 509 def sw = "b0010".U 510 def sd = "b0011".U 511 512 // l1 cache op 513 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 514 def cbo_zero = "b0111".U 515 516 // llc op 517 // bit encoding: | prefetch 11 | suboptype(2bit) | 518 def cbo_clean = "b1100".U 519 def cbo_flush = "b1101".U 520 def cbo_inval = "b1110".U 521 522 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 523 524 // atomics 525 // bit(1, 0) are size 526 // since atomics use a different fu type 527 // so we can safely reuse other load/store's encodings 528 // bit encoding: | optype(4bit) | size (2bit) | 529 def lr_w = "b000010".U 530 def sc_w = "b000110".U 531 def amoswap_w = "b001010".U 532 def amoadd_w = "b001110".U 533 def amoxor_w = "b010010".U 534 def amoand_w = "b010110".U 535 def amoor_w = "b011010".U 536 def amomin_w = "b011110".U 537 def amomax_w = "b100010".U 538 def amominu_w = "b100110".U 539 def amomaxu_w = "b101010".U 540 541 def lr_d = "b000011".U 542 def sc_d = "b000111".U 543 def amoswap_d = "b001011".U 544 def amoadd_d = "b001111".U 545 def amoxor_d = "b010011".U 546 def amoand_d = "b010111".U 547 def amoor_d = "b011011".U 548 def amomin_d = "b011111".U 549 def amomax_d = "b100011".U 550 def amominu_d = "b100111".U 551 def amomaxu_d = "b101011".U 552 553 def size(op: UInt) = op(1,0) 554 } 555 556 object BKUOpType { 557 558 def clmul = "b000000".U 559 def clmulh = "b000001".U 560 def clmulr = "b000010".U 561 def xpermn = "b000100".U 562 def xpermb = "b000101".U 563 564 def clz = "b001000".U 565 def clzw = "b001001".U 566 def ctz = "b001010".U 567 def ctzw = "b001011".U 568 def cpop = "b001100".U 569 def cpopw = "b001101".U 570 571 // 01xxxx is reserve 572 def aes64es = "b100000".U 573 def aes64esm = "b100001".U 574 def aes64ds = "b100010".U 575 def aes64dsm = "b100011".U 576 def aes64im = "b100100".U 577 def aes64ks1i = "b100101".U 578 def aes64ks2 = "b100110".U 579 580 // merge to two instruction sm4ks & sm4ed 581 def sm4ed0 = "b101000".U 582 def sm4ed1 = "b101001".U 583 def sm4ed2 = "b101010".U 584 def sm4ed3 = "b101011".U 585 def sm4ks0 = "b101100".U 586 def sm4ks1 = "b101101".U 587 def sm4ks2 = "b101110".U 588 def sm4ks3 = "b101111".U 589 590 def sha256sum0 = "b110000".U 591 def sha256sum1 = "b110001".U 592 def sha256sig0 = "b110010".U 593 def sha256sig1 = "b110011".U 594 def sha512sum0 = "b110100".U 595 def sha512sum1 = "b110101".U 596 def sha512sig0 = "b110110".U 597 def sha512sig1 = "b110111".U 598 599 def sm3p0 = "b111000".U 600 def sm3p1 = "b111001".U 601 } 602 603 object BTBtype { 604 def B = "b00".U // branch 605 def J = "b01".U // jump 606 def I = "b10".U // indirect 607 def R = "b11".U // return 608 609 def apply() = UInt(2.W) 610 } 611 612 object SelImm { 613 def IMM_X = "b0111".U 614 def IMM_S = "b1110".U 615 def IMM_SB = "b0001".U 616 def IMM_U = "b0010".U 617 def IMM_UJ = "b0011".U 618 def IMM_I = "b0100".U 619 def IMM_Z = "b0101".U 620 def INVALID_INSTR = "b0110".U 621 def IMM_B6 = "b1000".U 622 623 def IMM_OPIVIS = "b1001".U 624 def IMM_OPIVIU = "b1010".U 625 def IMM_VSETVLI = "b1100".U 626 def IMM_VSETIVLI = "b1101".U 627 def IMM_LUI32 = "b1011".U 628 def IMM_VRORVI = "b1111".U 629 630 def X = BitPat("b0000") 631 632 def apply() = UInt(4.W) 633 634 def mkString(immType: UInt) : String = { 635 val strMap = Map( 636 IMM_S.litValue -> "S", 637 IMM_SB.litValue -> "SB", 638 IMM_U.litValue -> "U", 639 IMM_UJ.litValue -> "UJ", 640 IMM_I.litValue -> "I", 641 IMM_Z.litValue -> "Z", 642 IMM_B6.litValue -> "B6", 643 IMM_OPIVIS.litValue -> "VIS", 644 IMM_OPIVIU.litValue -> "VIU", 645 IMM_VSETVLI.litValue -> "VSETVLI", 646 IMM_VSETIVLI.litValue -> "VSETIVLI", 647 IMM_LUI32.litValue -> "LUI32", 648 IMM_VRORVI.litValue -> "VRORVI", 649 INVALID_INSTR.litValue -> "INVALID", 650 ) 651 strMap(immType.litValue) 652 } 653 654 def getImmUnion(immType: UInt) : Imm = { 655 val iuMap = Map( 656 IMM_S.litValue -> ImmUnion.S, 657 IMM_SB.litValue -> ImmUnion.B, 658 IMM_U.litValue -> ImmUnion.U, 659 IMM_UJ.litValue -> ImmUnion.J, 660 IMM_I.litValue -> ImmUnion.I, 661 IMM_Z.litValue -> ImmUnion.Z, 662 IMM_B6.litValue -> ImmUnion.B6, 663 IMM_OPIVIS.litValue -> ImmUnion.OPIVIS, 664 IMM_OPIVIU.litValue -> ImmUnion.OPIVIU, 665 IMM_VSETVLI.litValue -> ImmUnion.VSETVLI, 666 IMM_VSETIVLI.litValue -> ImmUnion.VSETIVLI, 667 IMM_LUI32.litValue -> ImmUnion.LUI32, 668 IMM_VRORVI.litValue -> ImmUnion.VRORVI, 669 ) 670 iuMap(immType.litValue) 671 } 672 } 673 674 object UopSplitType { 675 def SCA_SIM = "b000000".U // 676 def VSET = "b010001".U // dirty: vset 677 def VEC_VVV = "b010010".U // VEC_VVV 678 def VEC_VXV = "b010011".U // VEC_VXV 679 def VEC_0XV = "b010100".U // VEC_0XV 680 def VEC_VVW = "b010101".U // VEC_VVW 681 def VEC_WVW = "b010110".U // VEC_WVW 682 def VEC_VXW = "b010111".U // VEC_VXW 683 def VEC_WXW = "b011000".U // VEC_WXW 684 def VEC_WVV = "b011001".U // VEC_WVV 685 def VEC_WXV = "b011010".U // VEC_WXV 686 def VEC_EXT2 = "b011011".U // VF2 0 -> V 687 def VEC_EXT4 = "b011100".U // VF4 0 -> V 688 def VEC_EXT8 = "b011101".U // VF8 0 -> V 689 def VEC_VVM = "b011110".U // VEC_VVM 690 def VEC_VXM = "b011111".U // VEC_VXM 691 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 692 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 693 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 694 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 695 def VEC_VRED = "b100100".U // VEC_VRED 696 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 697 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 698 def VEC_M0X = "b101001".U // VEC_M0X 0MV 699 def VEC_MVV = "b101010".U // VEC_MVV VMV 700 def VEC_M0X_VFIRST = "b101011".U // 701 def VEC_VWW = "b101100".U // 702 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 703 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 704 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 705 def VEC_COMPRESS = "b110000".U // vcompress.vm 706 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 707 def VEC_S_LDST = "b110010".U // vector strided load/store 708 def VEC_I_LDST = "b110011".U // vector indexed load/store 709 def VEC_VFV = "b111000".U // VEC_VFV 710 def VEC_VFW = "b111001".U // VEC_VFW 711 def VEC_WFW = "b111010".U // VEC_WVW 712 def VEC_VFM = "b111011".U // VEC_VFM 713 def VEC_VFRED = "b111100".U // VEC_VFRED 714 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 715 def VEC_M0M = "b000000".U // VEC_M0M 716 def VEC_MMM = "b000000".U // VEC_MMM 717 def VEC_MVNR = "b000100".U // vmvnr 718 def dummy = "b111111".U 719 720 def X = BitPat("b000000") 721 722 def apply() = UInt(6.W) 723 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 724 } 725 726 object ExceptionNO { 727 def instrAddrMisaligned = 0 728 def instrAccessFault = 1 729 def illegalInstr = 2 730 def breakPoint = 3 731 def loadAddrMisaligned = 4 732 def loadAccessFault = 5 733 def storeAddrMisaligned = 6 734 def storeAccessFault = 7 735 def ecallU = 8 736 def ecallS = 9 737 def ecallM = 11 738 def instrPageFault = 12 739 def loadPageFault = 13 740 // def singleStep = 14 741 def storePageFault = 15 742 def priorities = Seq( 743 breakPoint, // TODO: different BP has different priority 744 instrPageFault, 745 instrAccessFault, 746 illegalInstr, 747 instrAddrMisaligned, 748 ecallM, ecallS, ecallU, 749 storeAddrMisaligned, 750 loadAddrMisaligned, 751 storePageFault, 752 loadPageFault, 753 storeAccessFault, 754 loadAccessFault 755 ) 756 def all = priorities.distinct.sorted 757 def frontendSet = Seq( 758 instrAddrMisaligned, 759 instrAccessFault, 760 illegalInstr, 761 instrPageFault 762 ) 763 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 764 val new_vec = Wire(ExceptionVec()) 765 new_vec.foreach(_ := false.B) 766 select.foreach(i => new_vec(i) := vec(i)) 767 new_vec 768 } 769 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 770 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 771 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 772 partialSelect(vec, fuConfig.exceptionOut) 773 } 774 775 object TopDownCounters extends Enumeration { 776 val NoStall = Value("NoStall") // Base 777 // frontend 778 val OverrideBubble = Value("OverrideBubble") 779 val FtqUpdateBubble = Value("FtqUpdateBubble") 780 // val ControlRedirectBubble = Value("ControlRedirectBubble") 781 val TAGEMissBubble = Value("TAGEMissBubble") 782 val SCMissBubble = Value("SCMissBubble") 783 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 784 val RASMissBubble = Value("RASMissBubble") 785 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 786 val OtherRedirectBubble = Value("OtherRedirectBubble") 787 val FtqFullStall = Value("FtqFullStall") 788 789 val ICacheMissBubble = Value("ICacheMissBubble") 790 val ITLBMissBubble = Value("ITLBMissBubble") 791 val BTBMissBubble = Value("BTBMissBubble") 792 val FetchFragBubble = Value("FetchFragBubble") 793 794 // backend 795 // long inst stall at rob head 796 val DivStall = Value("DivStall") // int div, float div/sqrt 797 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 798 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 799 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 800 // freelist full 801 val IntFlStall = Value("IntFlStall") 802 val FpFlStall = Value("FpFlStall") 803 // dispatch queue full 804 val IntDqStall = Value("IntDqStall") 805 val FpDqStall = Value("FpDqStall") 806 val LsDqStall = Value("LsDqStall") 807 808 // memblock 809 val LoadTLBStall = Value("LoadTLBStall") 810 val LoadL1Stall = Value("LoadL1Stall") 811 val LoadL2Stall = Value("LoadL2Stall") 812 val LoadL3Stall = Value("LoadL3Stall") 813 val LoadMemStall = Value("LoadMemStall") 814 val StoreStall = Value("StoreStall") // include store tlb miss 815 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 816 817 // xs replay (different to gem5) 818 val LoadVioReplayStall = Value("LoadVioReplayStall") 819 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 820 821 // bad speculation 822 val ControlRecoveryStall = Value("ControlRecoveryStall") 823 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 824 val OtherRecoveryStall = Value("OtherRecoveryStall") 825 826 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 827 828 val OtherCoreStall = Value("OtherCoreStall") 829 830 val NumStallReasons = Value("NumStallReasons") 831 } 832} 833