1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 def no = "b000".U // this src read no reg but cannot be Any value 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 51 def apply() = UInt(3.W) 52 } 53 54 object SrcState { 55 def busy = "b0".U 56 def rdy = "b1".U 57 // def specRdy = "b10".U // speculative ready, for future use 58 def apply() = UInt(1.W) 59 60 def isReady(state: UInt): Bool = state === this.rdy 61 def isBusy(state: UInt): Bool = state === this.busy 62 } 63 64 def FuOpTypeWidth = 9 65 object FuOpType { 66 def apply() = UInt(FuOpTypeWidth.W) 67 def X = BitPat("b00000000") 68 } 69 70 object VlduType { 71 // bit encoding: | padding (2bit) || mop (2bit) | lumop(5bit) | 72 // only unit-stride use lumop 73 // mop [1:0] 74 // 0 0 : unit-stride 75 // 0 1 : indexed-unordered 76 // 1 0 : strided 77 // 1 1 : indexed-ordered 78 // lumop[4:0] 79 // 0 0 0 0 0 : unit-stride load 80 // 0 1 0 0 0 : unit-stride, whole register load 81 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 82 // 1 0 0 0 0 : unit-stride fault-only-first 83 def vle = "b00_00_00000".U 84 def vlr = "b00_00_01000".U 85 def vlm = "b00_00_01011".U 86 def vleff = "b00_00_10000".U 87 def vluxe = "b00_01_00000".U 88 def vlse = "b00_10_00000".U 89 def vloxe = "b00_11_00000".U 90 91 def isStrided(fuOpType: UInt): Bool = fuOpType === vlse 92 def isIndexed(fuOpType: UInt): Bool = fuOpType === vluxe || fuOpType === vloxe 93 } 94 95 object VstuType { 96 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 97 // only unit-stride use sumop 98 // mop [1:0] 99 // 0 0 : unit-stride 100 // 0 1 : indexed-unordered 101 // 1 0 : strided 102 // 1 1 : indexed-ordered 103 // sumop[4:0] 104 // 0 0 0 0 0 : unit-stride load 105 // 0 1 0 0 0 : unit-stride, whole register load 106 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 107 def vse = "b00_00_00000".U 108 def vsr = "b00_00_01000".U 109 def vsm = "b00_00_01011".U 110 def vsuxe = "b00_01_00000".U 111 def vsse = "b00_10_00000".U 112 def vsoxe = "b00_11_00000".U 113 114 def isStrided(fuOpType: UInt): Bool = fuOpType === vsse 115 def isIndexed(fuOpType: UInt): Bool = fuOpType === vsuxe || fuOpType === vsoxe 116 } 117 118 object IF2VectorType { 119 // use last 2 bits for vsew 120 def iDup2Vec = "b1_00".U 121 def fDup2Vec = "b1_01".U 122 def immDup2Vec = "b1_10".U 123 def i2Vec = "b0_00".U 124 def imm2Vec = "b0_10".U 125 def needDup(bits: UInt): Bool = bits(2) 126 def isImm(bits: UInt): Bool = bits(1) 127 } 128 129 object CommitType { 130 def NORMAL = "b000".U // int/fp 131 def BRANCH = "b001".U // branch 132 def LOAD = "b010".U // load 133 def STORE = "b011".U // store 134 135 def apply() = UInt(3.W) 136 def isFused(commitType: UInt): Bool = commitType(2) 137 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 138 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 139 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 140 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 141 } 142 143 object RedirectLevel { 144 def flushAfter = "b0".U 145 def flush = "b1".U 146 147 def apply() = UInt(1.W) 148 // def isUnconditional(level: UInt) = level(1) 149 def flushItself(level: UInt) = level(0) 150 // def isException(level: UInt) = level(1) && level(0) 151 } 152 153 object ExceptionVec { 154 val ExceptionVecSize = 16 155 def apply() = Vec(ExceptionVecSize, Bool()) 156 } 157 158 object PMAMode { 159 def R = "b1".U << 0 //readable 160 def W = "b1".U << 1 //writeable 161 def X = "b1".U << 2 //executable 162 def I = "b1".U << 3 //cacheable: icache 163 def D = "b1".U << 4 //cacheable: dcache 164 def S = "b1".U << 5 //enable speculative access 165 def A = "b1".U << 6 //enable atomic operation, A imply R & W 166 def C = "b1".U << 7 //if it is cacheable is configable 167 def Reserved = "b0".U 168 169 def apply() = UInt(7.W) 170 171 def read(mode: UInt) = mode(0) 172 def write(mode: UInt) = mode(1) 173 def execute(mode: UInt) = mode(2) 174 def icache(mode: UInt) = mode(3) 175 def dcache(mode: UInt) = mode(4) 176 def speculate(mode: UInt) = mode(5) 177 def atomic(mode: UInt) = mode(6) 178 def configable_cache(mode: UInt) = mode(7) 179 180 def strToMode(s: String) = { 181 var result = 0.U(8.W) 182 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 183 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 184 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 185 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 186 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 187 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 188 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 189 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 190 result 191 } 192 } 193 194 195 object CSROpType { 196 def jmp = "b000".U 197 def wrt = "b001".U 198 def set = "b010".U 199 def clr = "b011".U 200 def wfi = "b100".U 201 def wrti = "b101".U 202 def seti = "b110".U 203 def clri = "b111".U 204 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 205 } 206 207 // jump 208 object JumpOpType { 209 def jal = "b00".U 210 def jalr = "b01".U 211 def auipc = "b10".U 212// def call = "b11_011".U 213// def ret = "b11_100".U 214 def jumpOpisJalr(op: UInt) = op(0) 215 def jumpOpisAuipc(op: UInt) = op(1) 216 } 217 218 object FenceOpType { 219 def fence = "b10000".U 220 def sfence = "b10001".U 221 def fencei = "b10010".U 222 def nofence= "b00000".U 223 } 224 225 object ALUOpType { 226 // shift optype 227 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 228 def sll = "b000_0001".U // sll: src1 << src2 229 230 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 231 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 232 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 233 234 def srl = "b000_0101".U // srl: src1 >> src2 235 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 236 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 237 238 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 239 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 240 241 // RV64 32bit optype 242 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 243 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 244 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 245 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 246 247 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 248 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 249 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 250 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 251 252 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 253 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 254 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 255 def rolw = "b001_1100".U 256 def rorw = "b001_1101".U 257 258 // ADD-op 259 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 260 def add = "b010_0001".U // add: src1 + src2 261 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 262 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 263 264 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 265 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 266 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 267 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 268 269 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 270 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 271 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 272 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 273 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 274 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 275 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 276 277 // SUB-op: src1 - src2 278 def sub = "b011_0000".U 279 def sltu = "b011_0001".U 280 def slt = "b011_0010".U 281 def maxu = "b011_0100".U 282 def minu = "b011_0101".U 283 def max = "b011_0110".U 284 def min = "b011_0111".U 285 286 // branch 287 def beq = "b111_0000".U 288 def bne = "b111_0010".U 289 def blt = "b111_1000".U 290 def bge = "b111_1010".U 291 def bltu = "b111_1100".U 292 def bgeu = "b111_1110".U 293 294 // misc optype 295 def and = "b100_0000".U 296 def andn = "b100_0001".U 297 def or = "b100_0010".U 298 def orn = "b100_0011".U 299 def xor = "b100_0100".U 300 def xnor = "b100_0101".U 301 def orcb = "b100_0110".U 302 303 def sextb = "b100_1000".U 304 def packh = "b100_1001".U 305 def sexth = "b100_1010".U 306 def packw = "b100_1011".U 307 308 def revb = "b101_0000".U 309 def rev8 = "b101_0001".U 310 def pack = "b101_0010".U 311 def orh48 = "b101_0011".U 312 313 def szewl1 = "b101_1000".U 314 def szewl2 = "b101_1001".U 315 def szewl3 = "b101_1010".U 316 def byte2 = "b101_1011".U 317 318 def andlsb = "b110_0000".U 319 def andzexth = "b110_0001".U 320 def orlsb = "b110_0010".U 321 def orzexth = "b110_0011".U 322 def xorlsb = "b110_0100".U 323 def xorzexth = "b110_0101".U 324 def orcblsb = "b110_0110".U 325 def orcbzexth = "b110_0111".U 326 327 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 328 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 329 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 330 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 331 332 def apply() = UInt(FuOpTypeWidth.W) 333 } 334 335 object VSETOpType { 336 val setVlmaxBit = 0 337 val keepVlBit = 1 338 // destTypeBit == 0: write vl to rd 339 // destTypeBit == 1: write vconfig 340 val destTypeBit = 5 341 342 // vsetvli's uop 343 // rs1!=x0, normal 344 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 345 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 346 def uvsetvcfg_xi = "b1010_0000".U 347 def uvsetrd_xi = "b1000_0000".U 348 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 349 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 350 // uop1: w(rd) | vlmax, vtypei -> x[rd] 351 def uvsetvcfg_vlmax_i = "b1010_0001".U 352 def uvsetrd_vlmax_i = "b1000_0001".U 353 // rs1==x0, rd==x0, keep vl, set vtype 354 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 355 def uvsetvcfg_keep_v = "b1010_0010".U 356 357 // vsetvl's uop 358 // rs1!=x0, normal 359 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 360 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 361 def uvsetvcfg_xx = "b0110_0000".U 362 def uvsetrd_xx = "b0100_0000".U 363 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 364 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 365 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 366 def uvsetvcfg_vlmax_x = "b0110_0001".U 367 def uvsetrd_vlmax_x = "b0100_0001".U 368 // rs1==x0, rd==x0, keep vl, set vtype 369 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 370 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 371 def uvmv_v_x = "b0110_0010".U 372 def uvsetvcfg_vv = "b0111_0010".U 373 374 // vsetivli's uop 375 // uop0: w(vconfig) | vli, vtypei -> vconfig 376 // uop1: w(rd) | vli, vtypei -> x[rd] 377 def uvsetvcfg_ii = "b0010_0000".U 378 def uvsetrd_ii = "b0000_0000".U 379 380 def isVsetvl (func: UInt) = func(6) 381 def isVsetvli (func: UInt) = func(7) 382 def isVsetivli(func: UInt) = func(7, 6) === 0.U 383 def isNormal (func: UInt) = func(1, 0) === 0.U 384 def isSetVlmax(func: UInt) = func(setVlmaxBit) 385 def isKeepVl (func: UInt) = func(keepVlBit) 386 // RG: region 387 def writeIntRG(func: UInt) = !func(5) 388 def writeVecRG(func: UInt) = func(5) 389 def readIntRG (func: UInt) = !func(4) 390 def readVecRG (func: UInt) = func(4) 391 // modify fuOpType 392 def keepVl(func: UInt) = func | (1 << keepVlBit).U 393 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 394 } 395 396 object BRUOpType { 397 // branch 398 def beq = "b000_000".U 399 def bne = "b000_001".U 400 def blt = "b000_100".U 401 def bge = "b000_101".U 402 def bltu = "b001_000".U 403 def bgeu = "b001_001".U 404 405 def getBranchType(func: UInt) = func(3, 1) 406 def isBranchInvert(func: UInt) = func(0) 407 } 408 409 object MULOpType { 410 // mul 411 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 412 def mul = "b00000".U 413 def mulh = "b00001".U 414 def mulhsu = "b00010".U 415 def mulhu = "b00011".U 416 def mulw = "b00100".U 417 418 def mulw7 = "b01100".U 419 def isSign(op: UInt) = !op(1) 420 def isW(op: UInt) = op(2) 421 def isH(op: UInt) = op(1, 0) =/= 0.U 422 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 423 } 424 425 object DIVOpType { 426 // div 427 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 428 def div = "b10000".U 429 def divu = "b10010".U 430 def rem = "b10001".U 431 def remu = "b10011".U 432 433 def divw = "b10100".U 434 def divuw = "b10110".U 435 def remw = "b10101".U 436 def remuw = "b10111".U 437 438 def isSign(op: UInt) = !op(1) 439 def isW(op: UInt) = op(2) 440 def isH(op: UInt) = op(0) 441 } 442 443 object MDUOpType { 444 // mul 445 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 446 def mul = "b00000".U 447 def mulh = "b00001".U 448 def mulhsu = "b00010".U 449 def mulhu = "b00011".U 450 def mulw = "b00100".U 451 452 def mulw7 = "b01100".U 453 454 // div 455 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 456 def div = "b10000".U 457 def divu = "b10010".U 458 def rem = "b10001".U 459 def remu = "b10011".U 460 461 def divw = "b10100".U 462 def divuw = "b10110".U 463 def remw = "b10101".U 464 def remuw = "b10111".U 465 466 def isMul(op: UInt) = !op(4) 467 def isDiv(op: UInt) = op(4) 468 469 def isDivSign(op: UInt) = isDiv(op) && !op(1) 470 def isW(op: UInt) = op(2) 471 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 472 def getMulOp(op: UInt) = op(1, 0) 473 } 474 475 object LSUOpType { 476 // load pipeline 477 478 // normal load 479 // Note: bit(1, 0) are size, DO NOT CHANGE 480 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 481 def lb = "b0000".U 482 def lh = "b0001".U 483 def lw = "b0010".U 484 def ld = "b0011".U 485 def lbu = "b0100".U 486 def lhu = "b0101".U 487 def lwu = "b0110".U 488 489 // Zicbop software prefetch 490 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 491 def prefetch_i = "b1000".U // TODO 492 def prefetch_r = "b1001".U 493 def prefetch_w = "b1010".U 494 495 def isPrefetch(op: UInt): Bool = op(3) 496 497 // store pipeline 498 // normal store 499 // bit encoding: | store 00 | size(2bit) | 500 def sb = "b0000".U 501 def sh = "b0001".U 502 def sw = "b0010".U 503 def sd = "b0011".U 504 505 // l1 cache op 506 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 507 def cbo_zero = "b0111".U 508 509 // llc op 510 // bit encoding: | prefetch 11 | suboptype(2bit) | 511 def cbo_clean = "b1100".U 512 def cbo_flush = "b1101".U 513 def cbo_inval = "b1110".U 514 515 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 516 517 // atomics 518 // bit(1, 0) are size 519 // since atomics use a different fu type 520 // so we can safely reuse other load/store's encodings 521 // bit encoding: | optype(4bit) | size (2bit) | 522 def lr_w = "b000010".U 523 def sc_w = "b000110".U 524 def amoswap_w = "b001010".U 525 def amoadd_w = "b001110".U 526 def amoxor_w = "b010010".U 527 def amoand_w = "b010110".U 528 def amoor_w = "b011010".U 529 def amomin_w = "b011110".U 530 def amomax_w = "b100010".U 531 def amominu_w = "b100110".U 532 def amomaxu_w = "b101010".U 533 534 def lr_d = "b000011".U 535 def sc_d = "b000111".U 536 def amoswap_d = "b001011".U 537 def amoadd_d = "b001111".U 538 def amoxor_d = "b010011".U 539 def amoand_d = "b010111".U 540 def amoor_d = "b011011".U 541 def amomin_d = "b011111".U 542 def amomax_d = "b100011".U 543 def amominu_d = "b100111".U 544 def amomaxu_d = "b101011".U 545 546 def size(op: UInt) = op(1,0) 547 } 548 549 object BKUOpType { 550 551 def clmul = "b000000".U 552 def clmulh = "b000001".U 553 def clmulr = "b000010".U 554 def xpermn = "b000100".U 555 def xpermb = "b000101".U 556 557 def clz = "b001000".U 558 def clzw = "b001001".U 559 def ctz = "b001010".U 560 def ctzw = "b001011".U 561 def cpop = "b001100".U 562 def cpopw = "b001101".U 563 564 // 01xxxx is reserve 565 def aes64es = "b100000".U 566 def aes64esm = "b100001".U 567 def aes64ds = "b100010".U 568 def aes64dsm = "b100011".U 569 def aes64im = "b100100".U 570 def aes64ks1i = "b100101".U 571 def aes64ks2 = "b100110".U 572 573 // merge to two instruction sm4ks & sm4ed 574 def sm4ed0 = "b101000".U 575 def sm4ed1 = "b101001".U 576 def sm4ed2 = "b101010".U 577 def sm4ed3 = "b101011".U 578 def sm4ks0 = "b101100".U 579 def sm4ks1 = "b101101".U 580 def sm4ks2 = "b101110".U 581 def sm4ks3 = "b101111".U 582 583 def sha256sum0 = "b110000".U 584 def sha256sum1 = "b110001".U 585 def sha256sig0 = "b110010".U 586 def sha256sig1 = "b110011".U 587 def sha512sum0 = "b110100".U 588 def sha512sum1 = "b110101".U 589 def sha512sig0 = "b110110".U 590 def sha512sig1 = "b110111".U 591 592 def sm3p0 = "b111000".U 593 def sm3p1 = "b111001".U 594 } 595 596 object BTBtype { 597 def B = "b00".U // branch 598 def J = "b01".U // jump 599 def I = "b10".U // indirect 600 def R = "b11".U // return 601 602 def apply() = UInt(2.W) 603 } 604 605 object SelImm { 606 def IMM_X = "b0111".U 607 def IMM_S = "b1110".U 608 def IMM_SB = "b0001".U 609 def IMM_U = "b0010".U 610 def IMM_UJ = "b0011".U 611 def IMM_I = "b0100".U 612 def IMM_Z = "b0101".U 613 def INVALID_INSTR = "b0110".U 614 def IMM_B6 = "b1000".U 615 616 def IMM_OPIVIS = "b1001".U 617 def IMM_OPIVIU = "b1010".U 618 def IMM_VSETVLI = "b1100".U 619 def IMM_VSETIVLI = "b1101".U 620 def IMM_LUI32 = "b1011".U 621 622 def X = BitPat("b0000") 623 624 def apply() = UInt(4.W) 625 626 def mkString(immType: UInt) : String = { 627 val strMap = Map( 628 IMM_S.litValue -> "S", 629 IMM_SB.litValue -> "SB", 630 IMM_U.litValue -> "U", 631 IMM_UJ.litValue -> "UJ", 632 IMM_I.litValue -> "I", 633 IMM_Z.litValue -> "Z", 634 IMM_B6.litValue -> "B6", 635 IMM_OPIVIS.litValue -> "VIS", 636 IMM_OPIVIU.litValue -> "VIU", 637 IMM_VSETVLI.litValue -> "VSETVLI", 638 IMM_VSETIVLI.litValue -> "VSETIVLI", 639 IMM_LUI32.litValue -> "LUI32", 640 INVALID_INSTR.litValue -> "INVALID", 641 ) 642 strMap(immType.litValue) 643 } 644 } 645 646 object UopSplitType { 647 def SCA_SIM = "b000000".U // 648 def VSET = "b010001".U // dirty: vset 649 def VEC_VVV = "b010010".U // VEC_VVV 650 def VEC_VXV = "b010011".U // VEC_VXV 651 def VEC_0XV = "b010100".U // VEC_0XV 652 def VEC_VVW = "b010101".U // VEC_VVW 653 def VEC_WVW = "b010110".U // VEC_WVW 654 def VEC_VXW = "b010111".U // VEC_VXW 655 def VEC_WXW = "b011000".U // VEC_WXW 656 def VEC_WVV = "b011001".U // VEC_WVV 657 def VEC_WXV = "b011010".U // VEC_WXV 658 def VEC_EXT2 = "b011011".U // VF2 0 -> V 659 def VEC_EXT4 = "b011100".U // VF4 0 -> V 660 def VEC_EXT8 = "b011101".U // VF8 0 -> V 661 def VEC_VVM = "b011110".U // VEC_VVM 662 def VEC_VXM = "b011111".U // VEC_VXM 663 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 664 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 665 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 666 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 667 def VEC_VRED = "b100100".U // VEC_VRED 668 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 669 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 670 def VEC_M0X = "b101001".U // VEC_M0X 0MV 671 def VEC_MVV = "b101010".U // VEC_MVV VMV 672 def VEC_M0X_VFIRST = "b101011".U // 673 def VEC_VWW = "b101100".U // 674 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 675 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 676 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 677 def VEC_COMPRESS = "b110000".U // vcompress.vm 678 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 679 def VEC_S_LDST = "b110010".U // vector strided load/store 680 def VEC_I_LDST = "b110011".U // vector indexed load/store 681 def VEC_VFV = "b111000".U // VEC_VFV 682 def VEC_VFW = "b111001".U // VEC_VFW 683 def VEC_WFW = "b111010".U // VEC_WVW 684 def VEC_VFM = "b111011".U // VEC_VFM 685 def VEC_VFRED = "b111100".U // VEC_VFRED 686 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 687 def VEC_M0M = "b000000".U // VEC_M0M 688 def VEC_MMM = "b000000".U // VEC_MMM 689 def VEC_MVNR = "b000100".U // vmvnr 690 def dummy = "b111111".U 691 692 def X = BitPat("b000000") 693 694 def apply() = UInt(6.W) 695 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 696 } 697 698 object ExceptionNO { 699 def instrAddrMisaligned = 0 700 def instrAccessFault = 1 701 def illegalInstr = 2 702 def breakPoint = 3 703 def loadAddrMisaligned = 4 704 def loadAccessFault = 5 705 def storeAddrMisaligned = 6 706 def storeAccessFault = 7 707 def ecallU = 8 708 def ecallS = 9 709 def ecallM = 11 710 def instrPageFault = 12 711 def loadPageFault = 13 712 // def singleStep = 14 713 def storePageFault = 15 714 def priorities = Seq( 715 breakPoint, // TODO: different BP has different priority 716 instrPageFault, 717 instrAccessFault, 718 illegalInstr, 719 instrAddrMisaligned, 720 ecallM, ecallS, ecallU, 721 storeAddrMisaligned, 722 loadAddrMisaligned, 723 storePageFault, 724 loadPageFault, 725 storeAccessFault, 726 loadAccessFault 727 ) 728 def all = priorities.distinct.sorted 729 def frontendSet = Seq( 730 instrAddrMisaligned, 731 instrAccessFault, 732 illegalInstr, 733 instrPageFault 734 ) 735 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 736 val new_vec = Wire(ExceptionVec()) 737 new_vec.foreach(_ := false.B) 738 select.foreach(i => new_vec(i) := vec(i)) 739 new_vec 740 } 741 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 742 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 743 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 744 partialSelect(vec, fuConfig.exceptionOut) 745 } 746 747 object TopDownCounters extends Enumeration { 748 val NoStall = Value("NoStall") // Base 749 // frontend 750 val OverrideBubble = Value("OverrideBubble") 751 val FtqUpdateBubble = Value("FtqUpdateBubble") 752 // val ControlRedirectBubble = Value("ControlRedirectBubble") 753 val TAGEMissBubble = Value("TAGEMissBubble") 754 val SCMissBubble = Value("SCMissBubble") 755 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 756 val RASMissBubble = Value("RASMissBubble") 757 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 758 val OtherRedirectBubble = Value("OtherRedirectBubble") 759 val FtqFullStall = Value("FtqFullStall") 760 761 val ICacheMissBubble = Value("ICacheMissBubble") 762 val ITLBMissBubble = Value("ITLBMissBubble") 763 val BTBMissBubble = Value("BTBMissBubble") 764 val FetchFragBubble = Value("FetchFragBubble") 765 766 // backend 767 // long inst stall at rob head 768 val DivStall = Value("DivStall") // int div, float div/sqrt 769 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 770 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 771 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 772 // freelist full 773 val IntFlStall = Value("IntFlStall") 774 val FpFlStall = Value("FpFlStall") 775 // dispatch queue full 776 val IntDqStall = Value("IntDqStall") 777 val FpDqStall = Value("FpDqStall") 778 val LsDqStall = Value("LsDqStall") 779 780 // memblock 781 val LoadTLBStall = Value("LoadTLBStall") 782 val LoadL1Stall = Value("LoadL1Stall") 783 val LoadL2Stall = Value("LoadL2Stall") 784 val LoadL3Stall = Value("LoadL3Stall") 785 val LoadMemStall = Value("LoadMemStall") 786 val StoreStall = Value("StoreStall") // include store tlb miss 787 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 788 789 // xs replay (different to gem5) 790 val LoadVioReplayStall = Value("LoadVioReplayStall") 791 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 792 793 // bad speculation 794 val ControlRecoveryStall = Value("ControlRecoveryStall") 795 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 796 val OtherRecoveryStall = Value("OtherRecoveryStall") 797 798 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 799 800 val OtherCoreStall = Value("OtherCoreStall") 801 802 val NumStallReasons = Value("NumStallReasons") 803 } 804} 805