1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.tile.XLen 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType===fp 40 def isPcOrImm(srcType: UInt) = srcType(0) 41 def isRegOrFp(srcType: UInt) = !srcType(1) 42 def regIsFp(srcType: UInt) = srcType(1) 43 44 def apply() = UInt(2.W) 45 } 46 47 object SrcState { 48 def busy = "b0".U 49 def rdy = "b1".U 50 // def specRdy = "b10".U // speculative ready, for future use 51 def apply() = UInt(1.W) 52 } 53 54 object FuType { 55 def jmp = "b0000".U 56 def i2f = "b0001".U 57 def csr = "b0010".U 58 def alu = "b0110".U 59 def mul = "b0100".U 60 def div = "b0101".U 61 def fence = "b0011".U 62 def bmu = "b0111".U 63 64 def fmac = "b1000".U 65 def fmisc = "b1011".U 66 def fDivSqrt = "b1010".U 67 68 def ldu = "b1100".U 69 def stu = "b1101".U 70 def mou = "b1111".U // for amo, lr, sc, fence 71 72 def num = 14 73 74 def apply() = UInt(log2Up(num).W) 75 76 def isIntExu(fuType: UInt) = !fuType(3) 77 def isJumpExu(fuType: UInt) = fuType === jmp 78 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 79 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 80 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 81 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 82 def isAMO(fuType: UInt) = fuType(1) 83 84 def jmpCanAccept(fuType: UInt) = !fuType(2) 85 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 86 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 87 88 def fmacCanAccept(fuType: UInt) = !fuType(1) 89 def fmiscCanAccept(fuType: UInt) = fuType(1) 90 91 def loadCanAccept(fuType: UInt) = !fuType(0) 92 def storeCanAccept(fuType: UInt) = fuType(0) 93 94 def storeIsAMO(fuType: UInt) = fuType(1) 95 96 val functionNameMap = Map( 97 jmp.litValue() -> "jmp", 98 i2f.litValue() -> "int to float", 99 csr.litValue() -> "csr", 100 alu.litValue() -> "alu", 101 mul.litValue() -> "mul", 102 div.litValue() -> "div", 103 fence.litValue() -> "fence", 104 fmac.litValue() -> "fmac", 105 fmisc.litValue() -> "fmisc", 106 fDivSqrt.litValue() -> "fdiv/fsqrt", 107 ldu.litValue() -> "load", 108 stu.litValue() -> "store" 109 ) 110 111 } 112 113 object FuOpType { 114 def apply() = UInt(8.W) 115 } 116 117 object CommitType { 118 def NORMAL = "b00".U // int/fp 119 def BRANCH = "b01".U // branch 120 def LOAD = "b10".U // load 121 def STORE = "b11".U // store 122 123 def apply() = UInt(2.W) 124 def isLoadStore(commitType: UInt) = commitType(1) 125 def lsInstIsStore(commitType: UInt) = commitType(0) 126 def isStore(commitType: UInt) = isLoadStore(commitType) && lsInstIsStore(commitType) 127 def isBranch(commitType: UInt) = commitType(0) && !commitType(1) 128 } 129 130 object RedirectLevel { 131 def flushAfter = "b0".U 132 def flush = "b1".U 133 134 def apply() = UInt(1.W) 135 // def isUnconditional(level: UInt) = level(1) 136 def flushItself(level: UInt) = level(0) 137 // def isException(level: UInt) = level(1) && level(0) 138 } 139 140 object ExceptionVec { 141 def apply() = Vec(16, Bool()) 142 } 143 144 object PMAMode { 145 def R = "b1".U << 0 //readable 146 def W = "b1".U << 1 //writeable 147 def X = "b1".U << 2 //executable 148 def I = "b1".U << 3 //cacheable: icache 149 def D = "b1".U << 4 //cacheable: dcache 150 def S = "b1".U << 5 //enable speculative access 151 def A = "b1".U << 6 //enable atomic operation, A imply R & W 152 def C = "b1".U << 7 //if it is cacheable is configable 153 def Reserved = "b0".U 154 155 def apply() = UInt(7.W) 156 157 def read(mode: UInt) = mode(0) 158 def write(mode: UInt) = mode(1) 159 def execute(mode: UInt) = mode(2) 160 def icache(mode: UInt) = mode(3) 161 def dcache(mode: UInt) = mode(4) 162 def speculate(mode: UInt) = mode(5) 163 def atomic(mode: UInt) = mode(6) 164 def configable_cache(mode: UInt) = mode(7) 165 166 def strToMode(s: String) = { 167 var result = 0.U(8.W) 168 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 169 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 170 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 171 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 172 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 173 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 174 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 175 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 176 result 177 } 178 } 179 180 181 object CSROpType { 182 def jmp = "b000".U 183 def wrt = "b001".U 184 def set = "b010".U 185 def clr = "b011".U 186 def wrti = "b101".U 187 def seti = "b110".U 188 def clri = "b111".U 189 } 190 191 // jump 192 object JumpOpType { 193 def jal = "b00".U 194 def jalr = "b01".U 195 def auipc = "b10".U 196// def call = "b11_011".U 197// def ret = "b11_100".U 198 def jumpOpisJalr(op: UInt) = op(0) 199 def jumpOpisAuipc(op: UInt) = op(1) 200 } 201 202 object FenceOpType { 203 def fence = "b10000".U 204 def sfence = "b10001".U 205 def fencei = "b10010".U 206 } 207 208 object ALUOpType { 209 // misc & branch optype 210 def and = "b0_00_00_000".U 211 def andn = "b0_00_00_001".U 212 def or = "b0_00_00_010".U 213 def orn = "b0_00_00_011".U 214 def xor = "b0_00_00_100".U 215 def xnor = "b0_00_00_101".U 216 def orh48 = "b0_00_00_110".U 217 218 def andlsb = "b0_00_11_000".U 219 def andnlsb = "b0_00_11_001".U 220 def orlsb = "b0_00_11_010".U 221 def ornlsb = "b0_00_11_011".U 222 def xorlsb = "b0_00_11_100".U 223 def xnorlsb = "b0_00_11_101".U 224 225 def sext_b = "b0_00_01_000".U 226 def sext_h = "b0_00_01_001".U 227 def zext_h = "b0_00_01_010".U 228 // TOOD: optimize it 229 def szewl1 = "b0_00_01_011".U 230 def orc_b = "b0_00_01_100".U 231 def rev8 = "b0_00_01_101".U 232 // TOOD: optimize it 233 def szewl2 = "b0_00_01_110".U 234 // TOOD: optimize it 235 def byte2 = "b0_00_01_111".U 236 237 def beq = "b0_00_10_000".U 238 def bne = "b0_00_10_001".U 239 def blt = "b0_00_10_100".U 240 def bge = "b0_00_10_101".U 241 def bltu = "b0_00_10_110".U 242 def bgeu = "b0_00_10_111".U 243 244 // add & sub optype 245 def add_uw = "b0_01_00_000".U 246 def add = "b0_01_00_001".U 247 def oddadd = "b0_01_10_001".U 248 def sh1add_uw = "b0_01_00_010".U 249 def sh1add = "b0_01_00_011".U 250 def sh2add_uw = "b0_01_00_100".U 251 def sh2add = "b0_01_00_101".U 252 def sh3add_uw = "b0_01_00_110".U 253 def sh3add = "b0_01_00_111".U 254 def sh4add = "b0_01_01_001".U 255 def sr30add = "b0_01_01_011".U 256 def sr31add = "b0_01_01_101".U 257 def sr32add = "b0_01_01_111".U 258 259 // shift optype 260 def slli_uw = "b0_10_00_000".U 261 def sll = "b0_10_00_001".U 262 def bclr = "b0_10_00_100".U 263 def bset = "b0_10_00_101".U 264 def binv = "b0_10_00_110".U 265 266 def srl = "b0_10_01_001".U 267 def bext = "b0_10_01_010".U 268 def sra = "b0_10_01_100".U 269 270 def rol = "b0_10_10_000".U 271 272 def ror = "b0_10_11_000".U 273 274 def sub = "b0_11_00_000".U 275 def sltu = "b0_11_00_001".U 276 def slt = "b0_11_00_010".U 277 def maxu = "b0_11_00_100".U 278 def minu = "b0_11_00_101".U 279 def max = "b0_11_00_110".U 280 def min = "b0_11_00_111".U 281 282 // RV64 32bit optype 283 def addw = "b1_01_00_001".U 284 def addwbyte = "b1_01_00_011".U 285 def addwbit = "b1_01_00_101".U 286 def oddaddw = "b1_01_10_001".U 287 def subw = "b1_11_00_000".U 288 def sllw = "b1_10_00_000".U 289 def srlw = "b1_10_01_001".U 290 def sraw = "b1_10_01_100".U 291 def rolw = "b1_10_10_000".U 292 def rorw = "b1_10_11_000".U 293 294 def isWordOp(func: UInt) = func(7) 295 def isAddw(func: UInt) = func(7, 5) === "b101".U 296 def isLogic(func: UInt) = func(7, 3) === "b00000".U 297 def logicToLSB(func: UInt) = Cat(func(7, 5), "b11".U(2.W), func(2, 0)) 298 def isBranch(func: UInt) = func(6, 3) === "b0010".U 299 def getBranchType(func: UInt) = func(2, 1) 300 def isBranchInvert(func: UInt) = func(0) 301 302 def apply() = UInt(8.W) 303 } 304 305 object MDUOpType { 306 // mul 307 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 308 def mul = "b00000".U 309 def mulh = "b00001".U 310 def mulhsu = "b00010".U 311 def mulhu = "b00011".U 312 def mulw = "b00100".U 313 314 def mulw7 = "b01100".U 315 316 // div 317 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 318 def div = "b10000".U 319 def divu = "b10010".U 320 def rem = "b10001".U 321 def remu = "b10011".U 322 323 def divw = "b10100".U 324 def divuw = "b10110".U 325 def remw = "b10101".U 326 def remuw = "b10111".U 327 328 def isMul(op: UInt) = !op(4) 329 def isDiv(op: UInt) = op(4) 330 331 def isDivSign(op: UInt) = isDiv(op) && !op(1) 332 def isW(op: UInt) = op(2) 333 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 334 def getMulOp(op: UInt) = op(1, 0) 335 } 336 337 object LSUOpType { 338 // normal load/store 339 // bit(1, 0) are size 340 def lb = "b000000".U 341 def lh = "b000001".U 342 def lw = "b000010".U 343 def ld = "b000011".U 344 def lbu = "b000100".U 345 def lhu = "b000101".U 346 def lwu = "b000110".U 347 def sb = "b001000".U 348 def sh = "b001001".U 349 def sw = "b001010".U 350 def sd = "b001011".U 351 352 def isLoad(op: UInt): Bool = !op(3) 353 def isStore(op: UInt): Bool = op(3) 354 355 // atomics 356 // bit(1, 0) are size 357 // since atomics use a different fu type 358 // so we can safely reuse other load/store's encodings 359 def lr_w = "b000010".U 360 def sc_w = "b000110".U 361 def amoswap_w = "b001010".U 362 def amoadd_w = "b001110".U 363 def amoxor_w = "b010010".U 364 def amoand_w = "b010110".U 365 def amoor_w = "b011010".U 366 def amomin_w = "b011110".U 367 def amomax_w = "b100010".U 368 def amominu_w = "b100110".U 369 def amomaxu_w = "b101010".U 370 371 def lr_d = "b000011".U 372 def sc_d = "b000111".U 373 def amoswap_d = "b001011".U 374 def amoadd_d = "b001111".U 375 def amoxor_d = "b010011".U 376 def amoand_d = "b010111".U 377 def amoor_d = "b011011".U 378 def amomin_d = "b011111".U 379 def amomax_d = "b100011".U 380 def amominu_d = "b100111".U 381 def amomaxu_d = "b101011".U 382 } 383 384 object BMUOpType { 385 386 def clmul = "b0000".U 387 def clmulh = "b0010".U 388 def clmulr = "b0100".U 389 390 def clz = "b1000".U 391 def clzw = "b1001".U 392 def ctz = "b1010".U 393 def ctzw = "b1011".U 394 def cpop = "b1100".U 395 def cpopw = "b1101".U 396 } 397 398 object BTBtype { 399 def B = "b00".U // branch 400 def J = "b01".U // jump 401 def I = "b10".U // indirect 402 def R = "b11".U // return 403 404 def apply() = UInt(2.W) 405 } 406 407 object SelImm { 408 def IMM_X = "b0111".U 409 def IMM_S = "b0000".U 410 def IMM_SB = "b0001".U 411 def IMM_U = "b0010".U 412 def IMM_UJ = "b0011".U 413 def IMM_I = "b0100".U 414 def IMM_Z = "b0101".U 415 def INVALID_INSTR = "b0110".U 416 def IMM_B6 = "b1000".U 417 418 def apply() = UInt(4.W) 419 } 420 421 def dividerGen(p: Parameters) = new SRT4Divider(p(XLen))(p) 422 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 423 def aluGen(p: Parameters) = new Alu()(p) 424 def bmuGen(p: Parameters) = new Bmu()(p) 425 def jmpGen(p: Parameters) = new Jump()(p) 426 def fenceGen(p: Parameters) = new Fence()(p) 427 def csrGen(p: Parameters) = new CSR()(p) 428 def i2fGen(p: Parameters) = new IntToFP()(p) 429 def fmacGen(p: Parameters) = new FMA()(p) 430 def f2iGen(p: Parameters) = new FPToInt()(p) 431 def f2fGen(p: Parameters) = new FPToFP()(p) 432 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 433 def stdGen(p: Parameters) = new Std()(p) 434 435 def f2iSel(uop: MicroOp): Bool = { 436 uop.ctrl.rfWen 437 } 438 439 def i2fSel(uop: MicroOp): Bool = { 440 uop.ctrl.fpu.fromInt 441 } 442 443 def f2fSel(uop: MicroOp): Bool = { 444 val ctrl = uop.ctrl.fpu 445 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 446 } 447 448 def fdivSqrtSel(uop: MicroOp): Bool = { 449 val ctrl = uop.ctrl.fpu 450 ctrl.div || ctrl.sqrt 451 } 452 453 val aluCfg = FuConfig( 454 name = "alu", 455 fuGen = aluGen, 456 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 457 fuType = FuType.alu, 458 numIntSrc = 2, 459 numFpSrc = 0, 460 writeIntRf = true, 461 writeFpRf = false, 462 hasRedirect = true, 463 ) 464 465 val jmpCfg = FuConfig( 466 name = "jmp", 467 fuGen = jmpGen, 468 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 469 fuType = FuType.jmp, 470 numIntSrc = 1, 471 numFpSrc = 0, 472 writeIntRf = true, 473 writeFpRf = false, 474 hasRedirect = true, 475 ) 476 477 val fenceCfg = FuConfig( 478 name = "fence", 479 fuGen = fenceGen, 480 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 481 FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 482 UncertainLatency() // TODO: need rewrite latency structure, not just this value 483 ) 484 485 val csrCfg = FuConfig( 486 name = "csr", 487 fuGen = csrGen, 488 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 489 fuType = FuType.csr, 490 numIntSrc = 1, 491 numFpSrc = 0, 492 writeIntRf = true, 493 writeFpRf = false, 494 hasRedirect = false 495 ) 496 497 val i2fCfg = FuConfig( 498 name = "i2f", 499 fuGen = i2fGen, 500 fuSel = i2fSel, 501 FuType.i2f, 502 numIntSrc = 1, 503 numFpSrc = 0, 504 writeIntRf = false, 505 writeFpRf = true, 506 hasRedirect = false, 507 latency = CertainLatency(2), 508 fastUopOut = true, fastImplemented = true 509 ) 510 511 val divCfg = FuConfig( 512 name = "div", 513 fuGen = dividerGen, 514 fuSel = (uop: MicroOp) => MDUOpType.isDiv(uop.ctrl.fuOpType), 515 FuType.div, 516 2, 517 0, 518 writeIntRf = true, 519 writeFpRf = false, 520 hasRedirect = false, 521 latency = UncertainLatency(), 522 fastUopOut = true, 523 fastImplemented = false 524 ) 525 526 val mulCfg = FuConfig( 527 name = "mul", 528 fuGen = multiplierGen, 529 fuSel = (uop: MicroOp) => MDUOpType.isMul(uop.ctrl.fuOpType), 530 FuType.mul, 531 2, 532 0, 533 writeIntRf = true, 534 writeFpRf = false, 535 hasRedirect = false, 536 latency = CertainLatency(2), 537 fastUopOut = true, 538 fastImplemented = true 539 ) 540 541 val bmuCfg = FuConfig( 542 name = "bmu", 543 fuGen = bmuGen, 544 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bmu, 545 fuType = FuType.bmu, 546 numIntSrc = 2, 547 numFpSrc = 0, 548 writeIntRf = true, 549 writeFpRf = false, 550 hasRedirect = false, 551 latency = CertainLatency(1), 552 fastUopOut = true, 553 fastImplemented = false 554 ) 555 556 val fmacCfg = FuConfig( 557 name = "fmac", 558 fuGen = fmacGen, 559 fuSel = _ => true.B, 560 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, 561 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 562 ) 563 564 val f2iCfg = FuConfig( 565 name = "f2i", 566 fuGen = f2iGen, 567 fuSel = f2iSel, 568 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2), 569 fastUopOut = true, fastImplemented = true 570 ) 571 572 val f2fCfg = FuConfig( 573 name = "f2f", 574 fuGen = f2fGen, 575 fuSel = f2fSel, 576 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2), 577 fastUopOut = true, fastImplemented = true 578 ) 579 580 val fdivSqrtCfg = FuConfig( 581 name = "fdivSqrt", 582 fuGen = fdivSqrtGen, 583 fuSel = fdivSqrtSel, 584 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency(), 585 fastUopOut = true, fastImplemented = false, hasInputBuffer = true 586 ) 587 588 val lduCfg = FuConfig( 589 "ldu", 590 null, // DontCare 591 null, 592 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 593 UncertainLatency() 594 ) 595 596 val staCfg = FuConfig( 597 "sta", 598 null, 599 null, 600 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 601 UncertainLatency() 602 ) 603 604 val stdCfg = FuConfig( 605 "std", 606 fuGen = stdGen, fuSel = _ => true.B, FuType.stu, 1, 1, 607 writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = CertainLatency(1) 608 ) 609 610 val mouCfg = FuConfig( 611 "mou", 612 null, 613 null, 614 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 615 UncertainLatency() 616 ) 617 618 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 619 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 620 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 621 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bmuCfg), 1, Int.MaxValue) 622 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 623 val FmiscExeUnitCfg = ExuConfig( 624 "FmiscExeUnit", 625 "Fp", 626 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 627 Int.MaxValue, 1 628 ) 629 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0) 630 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 631 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 632} 633