1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.tile.XLen 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType===fp 40 def isPcOrImm(srcType: UInt) = srcType(0) 41 def isRegOrFp(srcType: UInt) = !srcType(1) 42 def regIsFp(srcType: UInt) = srcType(1) 43 44 def apply() = UInt(2.W) 45 } 46 47 object SrcState { 48 def busy = "b0".U 49 def rdy = "b1".U 50 // def specRdy = "b10".U // speculative ready, for future use 51 def apply() = UInt(1.W) 52 } 53 54 object FuType { 55 def jmp = "b0000".U 56 def i2f = "b0001".U 57 def csr = "b0010".U 58 def alu = "b0110".U 59 def mul = "b0100".U 60 def div = "b0101".U 61 def fence = "b0011".U 62 def bmu = "b0111".U 63 64 def fmac = "b1000".U 65 def fmisc = "b1011".U 66 def fDivSqrt = "b1010".U 67 68 def ldu = "b1100".U 69 def stu = "b1101".U 70 def mou = "b1111".U // for amo, lr, sc, fence 71 72 def num = 14 73 74 def apply() = UInt(log2Up(num).W) 75 76 def isIntExu(fuType: UInt) = !fuType(3) 77 def isJumpExu(fuType: UInt) = fuType === jmp 78 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 79 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 80 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 81 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 82 def isAMO(fuType: UInt) = fuType(1) 83 84 def jmpCanAccept(fuType: UInt) = !fuType(2) 85 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 86 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 87 88 def fmacCanAccept(fuType: UInt) = !fuType(1) 89 def fmiscCanAccept(fuType: UInt) = fuType(1) 90 91 def loadCanAccept(fuType: UInt) = !fuType(0) 92 def storeCanAccept(fuType: UInt) = fuType(0) 93 94 def storeIsAMO(fuType: UInt) = fuType(1) 95 96 val functionNameMap = Map( 97 jmp.litValue() -> "jmp", 98 i2f.litValue() -> "int to float", 99 csr.litValue() -> "csr", 100 alu.litValue() -> "alu", 101 mul.litValue() -> "mul", 102 div.litValue() -> "div", 103 fence.litValue() -> "fence", 104 fmac.litValue() -> "fmac", 105 fmisc.litValue() -> "fmisc", 106 fDivSqrt.litValue() -> "fdiv/fsqrt", 107 ldu.litValue() -> "load", 108 stu.litValue() -> "store" 109 ) 110 111 } 112 113 object FuOpType { 114 def apply() = UInt(8.W) 115 } 116 117 object CommitType { 118 def NORMAL = "b00".U // int/fp 119 def BRANCH = "b01".U // branch 120 def LOAD = "b10".U // load 121 def STORE = "b11".U // store 122 123 def apply() = UInt(2.W) 124 def isLoadStore(commitType: UInt) = commitType(1) 125 def lsInstIsStore(commitType: UInt) = commitType(0) 126 def isStore(commitType: UInt) = isLoadStore(commitType) && lsInstIsStore(commitType) 127 def isBranch(commitType: UInt) = commitType(0) && !commitType(1) 128 } 129 130 object RedirectLevel { 131 def flushAfter = "b0".U 132 def flush = "b1".U 133 134 def apply() = UInt(1.W) 135 // def isUnconditional(level: UInt) = level(1) 136 def flushItself(level: UInt) = level(0) 137 // def isException(level: UInt) = level(1) && level(0) 138 } 139 140 object ExceptionVec { 141 def apply() = Vec(16, Bool()) 142 } 143 144 object PMAMode { 145 def R = "b1".U << 0 //readable 146 def W = "b1".U << 1 //writeable 147 def X = "b1".U << 2 //executable 148 def I = "b1".U << 3 //cacheable: icache 149 def D = "b1".U << 4 //cacheable: dcache 150 def S = "b1".U << 5 //enable speculative access 151 def A = "b1".U << 6 //enable atomic operation, A imply R & W 152 def C = "b1".U << 7 //if it is cacheable is configable 153 def Reserved = "b0".U 154 155 def apply() = UInt(7.W) 156 157 def read(mode: UInt) = mode(0) 158 def write(mode: UInt) = mode(1) 159 def execute(mode: UInt) = mode(2) 160 def icache(mode: UInt) = mode(3) 161 def dcache(mode: UInt) = mode(4) 162 def speculate(mode: UInt) = mode(5) 163 def atomic(mode: UInt) = mode(6) 164 def configable_cache(mode: UInt) = mode(7) 165 166 def strToMode(s: String) = { 167 var result = 0.U(8.W) 168 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 169 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 170 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 171 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 172 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 173 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 174 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 175 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 176 result 177 } 178 } 179 180 181 object CSROpType { 182 def jmp = "b000".U 183 def wrt = "b001".U 184 def set = "b010".U 185 def clr = "b011".U 186 def wrti = "b101".U 187 def seti = "b110".U 188 def clri = "b111".U 189 } 190 191 // jump 192 object JumpOpType { 193 def jal = "b00".U 194 def jalr = "b01".U 195 def auipc = "b10".U 196// def call = "b11_011".U 197// def ret = "b11_100".U 198 def jumpOpisJalr(op: UInt) = op(0) 199 def jumpOpisAuipc(op: UInt) = op(1) 200 } 201 202 object FenceOpType { 203 def fence = "b10000".U 204 def sfence = "b10001".U 205 def fencei = "b10010".U 206 } 207 208 object ALUOpType { 209 // misc & branch optype 210 def and = "b0_00_00_000".U 211 def andn = "b0_00_00_001".U 212 def or = "b0_00_00_010".U 213 def orn = "b0_00_00_011".U 214 def xor = "b0_00_00_100".U 215 def xnor = "b0_00_00_101".U 216 def orh48 = "b0_00_00_110".U 217 def orc_b = "b0_00_00_111".U 218 219 def andlsb = "b0_00_11_000".U 220 def andnlsb = "b0_00_11_001".U 221 def orlsb = "b0_00_11_010".U 222 def ornlsb = "b0_00_11_011".U 223 def xorlsb = "b0_00_11_100".U 224 def xnorlsb = "b0_00_11_101".U 225 226 def sext_b = "b0_00_01_000".U 227 def sext_h = "b0_00_01_001".U 228 def zext_h = "b0_00_01_010".U 229 def rev8 = "b0_00_01_011".U 230 // TOOD: optimize it 231 def szewl1 = "b0_00_01_100".U 232 def szewl2 = "b0_00_01_101".U 233 def szewl3 = "b0_00_01_110".U 234 def byte2 = "b0_00_01_111".U 235 236 def beq = "b0_00_10_000".U 237 def bne = "b0_00_10_001".U 238 def blt = "b0_00_10_100".U 239 def bge = "b0_00_10_101".U 240 def bltu = "b0_00_10_110".U 241 def bgeu = "b0_00_10_111".U 242 243 // add & sub optype 244 def add_uw = "b0_01_00_000".U 245 def add = "b0_01_00_001".U 246 247 def oddadd = "b0_01_11_001".U 248 249 def sh1add_uw = "b0_01_10_000".U 250 def sh1add = "b0_01_10_001".U 251 def sh2add_uw = "b0_01_10_010".U 252 def sh2add = "b0_01_10_011".U 253 def sh3add_uw = "b0_01_10_100".U 254 def sh3add = "b0_01_10_101".U 255 def sh4add = "b0_01_10_111".U 256 257 def sr29add = "b0_01_01_001".U 258 def sr30add = "b0_01_01_011".U 259 def sr31add = "b0_01_01_101".U 260 def sr32add = "b0_01_01_111".U 261 262 // shift optype 263 def slli_uw = "b0_10_00_000".U 264 def sll = "b0_10_00_001".U 265 def bclr = "b0_10_00_100".U 266 def bset = "b0_10_00_101".U 267 def binv = "b0_10_00_110".U 268 269 def srl = "b0_10_01_001".U 270 def bext = "b0_10_01_010".U 271 def sra = "b0_10_01_100".U 272 273 def rol = "b0_10_10_000".U 274 275 def ror = "b0_10_11_000".U 276 277 def sub = "b0_11_00_000".U 278 def sltu = "b0_11_00_001".U 279 def slt = "b0_11_00_010".U 280 def maxu = "b0_11_00_100".U 281 def minu = "b0_11_00_101".U 282 def max = "b0_11_00_110".U 283 def min = "b0_11_00_111".U 284 285 // RV64 32bit optype 286 def addw = "b1_01_00_001".U 287 def addwbyte = "b1_01_00_011".U 288 def addwbit = "b1_01_00_101".U 289 def oddaddw = "b1_01_11_001".U 290 def subw = "b1_11_00_000".U 291 def sllw = "b1_10_00_000".U 292 def srlw = "b1_10_01_001".U 293 def sraw = "b1_10_01_100".U 294 def rolw = "b1_10_10_000".U 295 def rorw = "b1_10_11_000".U 296 297 def isWordOp(func: UInt) = func(7) 298 def isAddw(func: UInt) = func(7, 5) === "b101".U 299 def isLogic(func: UInt) = func(7, 3) === "b00000".U 300 def logicToLSB(func: UInt) = Cat(func(7, 5), "b11".U(2.W), func(2, 0)) 301 def isBranch(func: UInt) = func(6, 3) === "b0010".U 302 def getBranchType(func: UInt) = func(2, 1) 303 def isBranchInvert(func: UInt) = func(0) 304 def isAddOddBit(func: UInt) = func(4, 3) === "b11".U(2.W) 305 def isShAdd(func: UInt) = func(4, 3) === "b10".U(2.W) 306 def isSrAdd(func: UInt) = func(4, 3) === "b01".U(2.W) 307 308 def apply() = UInt(8.W) 309 } 310 311 object MDUOpType { 312 // mul 313 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 314 def mul = "b00000".U 315 def mulh = "b00001".U 316 def mulhsu = "b00010".U 317 def mulhu = "b00011".U 318 def mulw = "b00100".U 319 320 def mulw7 = "b01100".U 321 322 // div 323 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 324 def div = "b10000".U 325 def divu = "b10010".U 326 def rem = "b10001".U 327 def remu = "b10011".U 328 329 def divw = "b10100".U 330 def divuw = "b10110".U 331 def remw = "b10101".U 332 def remuw = "b10111".U 333 334 def isMul(op: UInt) = !op(4) 335 def isDiv(op: UInt) = op(4) 336 337 def isDivSign(op: UInt) = isDiv(op) && !op(1) 338 def isW(op: UInt) = op(2) 339 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 340 def getMulOp(op: UInt) = op(1, 0) 341 } 342 343 object LSUOpType { 344 // normal load/store 345 // bit(1, 0) are size 346 def lb = "b000000".U 347 def lh = "b000001".U 348 def lw = "b000010".U 349 def ld = "b000011".U 350 def lbu = "b000100".U 351 def lhu = "b000101".U 352 def lwu = "b000110".U 353 def sb = "b001000".U 354 def sh = "b001001".U 355 def sw = "b001010".U 356 def sd = "b001011".U 357 358 def isLoad(op: UInt): Bool = !op(3) 359 def isStore(op: UInt): Bool = op(3) 360 361 // atomics 362 // bit(1, 0) are size 363 // since atomics use a different fu type 364 // so we can safely reuse other load/store's encodings 365 def lr_w = "b000010".U 366 def sc_w = "b000110".U 367 def amoswap_w = "b001010".U 368 def amoadd_w = "b001110".U 369 def amoxor_w = "b010010".U 370 def amoand_w = "b010110".U 371 def amoor_w = "b011010".U 372 def amomin_w = "b011110".U 373 def amomax_w = "b100010".U 374 def amominu_w = "b100110".U 375 def amomaxu_w = "b101010".U 376 377 def lr_d = "b000011".U 378 def sc_d = "b000111".U 379 def amoswap_d = "b001011".U 380 def amoadd_d = "b001111".U 381 def amoxor_d = "b010011".U 382 def amoand_d = "b010111".U 383 def amoor_d = "b011011".U 384 def amomin_d = "b011111".U 385 def amomax_d = "b100011".U 386 def amominu_d = "b100111".U 387 def amomaxu_d = "b101011".U 388 } 389 390 object BMUOpType { 391 392 def clmul = "b0000".U 393 def clmulh = "b0010".U 394 def clmulr = "b0100".U 395 396 def clz = "b1000".U 397 def clzw = "b1001".U 398 def ctz = "b1010".U 399 def ctzw = "b1011".U 400 def cpop = "b1100".U 401 def cpopw = "b1101".U 402 } 403 404 object BTBtype { 405 def B = "b00".U // branch 406 def J = "b01".U // jump 407 def I = "b10".U // indirect 408 def R = "b11".U // return 409 410 def apply() = UInt(2.W) 411 } 412 413 object SelImm { 414 def IMM_X = "b0111".U 415 def IMM_S = "b0000".U 416 def IMM_SB = "b0001".U 417 def IMM_U = "b0010".U 418 def IMM_UJ = "b0011".U 419 def IMM_I = "b0100".U 420 def IMM_Z = "b0101".U 421 def INVALID_INSTR = "b0110".U 422 def IMM_B6 = "b1000".U 423 424 def apply() = UInt(4.W) 425 } 426 427 def dividerGen(p: Parameters) = new SRT4Divider(p(XLen))(p) 428 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 429 def aluGen(p: Parameters) = new Alu()(p) 430 def bmuGen(p: Parameters) = new Bmu()(p) 431 def jmpGen(p: Parameters) = new Jump()(p) 432 def fenceGen(p: Parameters) = new Fence()(p) 433 def csrGen(p: Parameters) = new CSR()(p) 434 def i2fGen(p: Parameters) = new IntToFP()(p) 435 def fmacGen(p: Parameters) = new FMA()(p) 436 def f2iGen(p: Parameters) = new FPToInt()(p) 437 def f2fGen(p: Parameters) = new FPToFP()(p) 438 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 439 def stdGen(p: Parameters) = new Std()(p) 440 441 def f2iSel(uop: MicroOp): Bool = { 442 uop.ctrl.rfWen 443 } 444 445 def i2fSel(uop: MicroOp): Bool = { 446 uop.ctrl.fpu.fromInt 447 } 448 449 def f2fSel(uop: MicroOp): Bool = { 450 val ctrl = uop.ctrl.fpu 451 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 452 } 453 454 def fdivSqrtSel(uop: MicroOp): Bool = { 455 val ctrl = uop.ctrl.fpu 456 ctrl.div || ctrl.sqrt 457 } 458 459 val aluCfg = FuConfig( 460 name = "alu", 461 fuGen = aluGen, 462 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 463 fuType = FuType.alu, 464 numIntSrc = 2, 465 numFpSrc = 0, 466 writeIntRf = true, 467 writeFpRf = false, 468 hasRedirect = true, 469 ) 470 471 val jmpCfg = FuConfig( 472 name = "jmp", 473 fuGen = jmpGen, 474 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 475 fuType = FuType.jmp, 476 numIntSrc = 1, 477 numFpSrc = 0, 478 writeIntRf = true, 479 writeFpRf = false, 480 hasRedirect = true, 481 ) 482 483 val fenceCfg = FuConfig( 484 name = "fence", 485 fuGen = fenceGen, 486 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 487 FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 488 latency = UncertainLatency(), // TODO: need rewrite latency structure, not just this value, 489 hasExceptionOut = true 490 ) 491 492 val csrCfg = FuConfig( 493 name = "csr", 494 fuGen = csrGen, 495 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 496 fuType = FuType.csr, 497 numIntSrc = 1, 498 numFpSrc = 0, 499 writeIntRf = true, 500 writeFpRf = false, 501 hasRedirect = false, 502 hasExceptionOut = true 503 ) 504 505 val i2fCfg = FuConfig( 506 name = "i2f", 507 fuGen = i2fGen, 508 fuSel = i2fSel, 509 FuType.i2f, 510 numIntSrc = 1, 511 numFpSrc = 0, 512 writeIntRf = false, 513 writeFpRf = true, 514 hasRedirect = false, 515 latency = CertainLatency(2), 516 fastUopOut = true, fastImplemented = true 517 ) 518 519 val divCfg = FuConfig( 520 name = "div", 521 fuGen = dividerGen, 522 fuSel = (uop: MicroOp) => MDUOpType.isDiv(uop.ctrl.fuOpType), 523 FuType.div, 524 2, 525 0, 526 writeIntRf = true, 527 writeFpRf = false, 528 hasRedirect = false, 529 latency = UncertainLatency(), 530 fastUopOut = true, 531 fastImplemented = false 532 ) 533 534 val mulCfg = FuConfig( 535 name = "mul", 536 fuGen = multiplierGen, 537 fuSel = (uop: MicroOp) => MDUOpType.isMul(uop.ctrl.fuOpType), 538 FuType.mul, 539 2, 540 0, 541 writeIntRf = true, 542 writeFpRf = false, 543 hasRedirect = false, 544 latency = CertainLatency(2), 545 fastUopOut = true, 546 fastImplemented = true 547 ) 548 549 val bmuCfg = FuConfig( 550 name = "bmu", 551 fuGen = bmuGen, 552 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bmu, 553 fuType = FuType.bmu, 554 numIntSrc = 2, 555 numFpSrc = 0, 556 writeIntRf = true, 557 writeFpRf = false, 558 hasRedirect = false, 559 latency = CertainLatency(1), 560 fastUopOut = true, 561 fastImplemented = false 562 ) 563 564 val fmacCfg = FuConfig( 565 name = "fmac", 566 fuGen = fmacGen, 567 fuSel = _ => true.B, 568 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, 569 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 570 ) 571 572 val f2iCfg = FuConfig( 573 name = "f2i", 574 fuGen = f2iGen, 575 fuSel = f2iSel, 576 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2), 577 fastUopOut = true, fastImplemented = true 578 ) 579 580 val f2fCfg = FuConfig( 581 name = "f2f", 582 fuGen = f2fGen, 583 fuSel = f2fSel, 584 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2), 585 fastUopOut = true, fastImplemented = true 586 ) 587 588 val fdivSqrtCfg = FuConfig( 589 name = "fdivSqrt", 590 fuGen = fdivSqrtGen, 591 fuSel = fdivSqrtSel, 592 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency(), 593 fastUopOut = true, fastImplemented = false, hasInputBuffer = true 594 ) 595 596 val lduCfg = FuConfig( 597 "ldu", 598 null, // DontCare 599 null, 600 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 601 latency = UncertainLatency(), hasExceptionOut = true 602 ) 603 604 val staCfg = FuConfig( 605 "sta", 606 null, 607 null, 608 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 609 latency = UncertainLatency(), hasExceptionOut = true 610 ) 611 612 val stdCfg = FuConfig( 613 "std", 614 fuGen = stdGen, fuSel = _ => true.B, FuType.stu, 1, 1, 615 writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = CertainLatency(1) 616 ) 617 618 val mouCfg = FuConfig( 619 "mou", 620 null, 621 null, 622 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 623 latency = UncertainLatency(), hasExceptionOut = true 624 ) 625 626 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 627 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 628 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 629 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bmuCfg), 1, Int.MaxValue) 630 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 631 val FmiscExeUnitCfg = ExuConfig( 632 "FmiscExeUnit", 633 "Fp", 634 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 635 Int.MaxValue, 1 636 ) 637 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0) 638 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 639 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 640} 641