1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isFp(srcType: UInt) = srcType(1) 46 def isVp(srcType: UInt) = srcType(2) 47 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 48 49 def isNull(srcType: UInt) = !(isPcOrImm(srcType) || isReg(srcType) || 50 isFp(srcType) || isVp(srcType)) 51 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 } 61 62 // Todo: Use OH instead 63 object FuType { 64 def jmp = "b00000".U 65 def i2f = "b00001".U 66 def csr = "b00010".U 67 def alu = "b00110".U 68 def mul = "b00100".U 69 def div = "b00101".U 70 def fence = "b00011".U 71 def bku = "b00111".U 72 73 def fmac = "b01000".U 74 def fmisc = "b01011".U 75 def fDivSqrt = "b01010".U 76 77 def ldu = "b01100".U 78 def stu = "b01101".U 79 def mou = "b01111".U // for amo, lr, sc, fence 80 81 def vipu = "b10000".U 82 def vialuF = "b10001".U // for VIALU Fixed-Point instructions 83 def vfpu = "b11000".U 84 def vldu = "b11100".U 85 def vstu = "b11101".U 86 def vppu = "b11001".U // for Permutation Unit 87 def X = BitPat("b00000") // TODO: It may be a potential bug 88 89 def num = 19 90 91 def apply() = UInt(log2Up(num).W) 92 93 // TODO: Optimize FuTpye and its method 94 // FIXME: Vector FuType coding is not ready 95 def isVecExu(fuType: UInt) = fuType(4) 96 def isIntExu(fuType: UInt) = !isVecExu(fuType) && !fuType(3) 97 def isJumpExu(fuType: UInt) = fuType === jmp 98 def isFpExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b10".U) 99 def isMemExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b11".U) 100 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 101 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 102 def isAMO(fuType: UInt) = fuType(1) 103 def isFence(fuType: UInt) = fuType === fence 104 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 105 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 106 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 107 108 def jmpCanAccept(fuType: UInt) = !fuType(2) 109 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 110 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 111 112 def fmacCanAccept(fuType: UInt) = !fuType(1) 113 def fmiscCanAccept(fuType: UInt) = fuType(1) 114 115 def loadCanAccept(fuType: UInt) = !fuType(0) 116 def storeCanAccept(fuType: UInt) = fuType(0) 117 118 def storeIsAMO(fuType: UInt) = fuType(1) 119 120 val functionNameMap = Map( 121 jmp.litValue() -> "jmp", 122 i2f.litValue() -> "int_to_float", 123 csr.litValue() -> "csr", 124 alu.litValue() -> "alu", 125 mul.litValue() -> "mul", 126 div.litValue() -> "div", 127 fence.litValue() -> "fence", 128 bku.litValue() -> "bku", 129 fmac.litValue() -> "fmac", 130 fmisc.litValue() -> "fmisc", 131 fDivSqrt.litValue() -> "fdiv_fsqrt", 132 ldu.litValue() -> "load", 133 stu.litValue() -> "store", 134 mou.litValue() -> "mou" 135 ) 136 } 137 138 def FuOpTypeWidth = 8 139 object FuOpType { 140 def apply() = UInt(FuOpTypeWidth.W) 141 def X = BitPat("b00000000") 142 } 143 144 // move VipuType and VfpuType into YunSuan/package.scala 145 // object VipuType { 146 // def dummy = 0.U(7.W) 147 // } 148 149 // object VfpuType { 150 // def dummy = 0.U(7.W) 151 // } 152 153 object VlduType { 154 def dummy = 0.U 155 } 156 157 object VstuType { 158 def dummy = 0.U 159 } 160 161 object CommitType { 162 def NORMAL = "b000".U // int/fp 163 def BRANCH = "b001".U // branch 164 def LOAD = "b010".U // load 165 def STORE = "b011".U // store 166 167 def apply() = UInt(3.W) 168 def isFused(commitType: UInt): Bool = commitType(2) 169 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 170 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 171 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 172 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 173 } 174 175 object RedirectLevel { 176 def flushAfter = "b0".U 177 def flush = "b1".U 178 179 def apply() = UInt(1.W) 180 // def isUnconditional(level: UInt) = level(1) 181 def flushItself(level: UInt) = level(0) 182 // def isException(level: UInt) = level(1) && level(0) 183 } 184 185 object ExceptionVec { 186 def apply() = Vec(16, Bool()) 187 } 188 189 object PMAMode { 190 def R = "b1".U << 0 //readable 191 def W = "b1".U << 1 //writeable 192 def X = "b1".U << 2 //executable 193 def I = "b1".U << 3 //cacheable: icache 194 def D = "b1".U << 4 //cacheable: dcache 195 def S = "b1".U << 5 //enable speculative access 196 def A = "b1".U << 6 //enable atomic operation, A imply R & W 197 def C = "b1".U << 7 //if it is cacheable is configable 198 def Reserved = "b0".U 199 200 def apply() = UInt(7.W) 201 202 def read(mode: UInt) = mode(0) 203 def write(mode: UInt) = mode(1) 204 def execute(mode: UInt) = mode(2) 205 def icache(mode: UInt) = mode(3) 206 def dcache(mode: UInt) = mode(4) 207 def speculate(mode: UInt) = mode(5) 208 def atomic(mode: UInt) = mode(6) 209 def configable_cache(mode: UInt) = mode(7) 210 211 def strToMode(s: String) = { 212 var result = 0.U(8.W) 213 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 214 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 215 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 216 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 217 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 218 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 219 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 220 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 221 result 222 } 223 } 224 225 226 object CSROpType { 227 def jmp = "b000".U 228 def wrt = "b001".U 229 def set = "b010".U 230 def clr = "b011".U 231 def wfi = "b100".U 232 def wrti = "b101".U 233 def seti = "b110".U 234 def clri = "b111".U 235 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 236 } 237 238 // jump 239 object JumpOpType { 240 def jal = "b00".U 241 def jalr = "b01".U 242 def auipc = "b10".U 243// def call = "b11_011".U 244// def ret = "b11_100".U 245 def jumpOpisJalr(op: UInt) = op(0) 246 def jumpOpisAuipc(op: UInt) = op(1) 247 } 248 249 object FenceOpType { 250 def fence = "b10000".U 251 def sfence = "b10001".U 252 def fencei = "b10010".U 253 def nofence= "b00000".U 254 } 255 256 object ALUOpType { 257 // shift optype 258 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 259 def sll = "b000_0001".U // sll: src1 << src2 260 261 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 262 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 263 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 264 265 def srl = "b000_0101".U // srl: src1 >> src2 266 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 267 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 268 269 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 270 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 271 272 // RV64 32bit optype 273 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 274 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 275 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 276 277 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 278 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 279 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 280 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 281 282 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 283 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 284 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 285 def rolw = "b001_1100".U 286 def rorw = "b001_1101".U 287 288 // ADD-op 289 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 290 def add = "b010_0001".U // add: src1 + src2 291 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 292 293 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 294 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 295 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 296 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 297 298 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 299 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 300 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 301 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 302 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 303 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 304 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 305 306 // SUB-op: src1 - src2 307 def sub = "b011_0000".U 308 def sltu = "b011_0001".U 309 def slt = "b011_0010".U 310 def maxu = "b011_0100".U 311 def minu = "b011_0101".U 312 def max = "b011_0110".U 313 def min = "b011_0111".U 314 315 // branch 316 def beq = "b111_0000".U 317 def bne = "b111_0010".U 318 def blt = "b111_1000".U 319 def bge = "b111_1010".U 320 def bltu = "b111_1100".U 321 def bgeu = "b111_1110".U 322 323 // misc optype 324 def and = "b100_0000".U 325 def andn = "b100_0001".U 326 def or = "b100_0010".U 327 def orn = "b100_0011".U 328 def xor = "b100_0100".U 329 def xnor = "b100_0101".U 330 def orcb = "b100_0110".U 331 332 def sextb = "b100_1000".U 333 def packh = "b100_1001".U 334 def sexth = "b100_1010".U 335 def packw = "b100_1011".U 336 337 def revb = "b101_0000".U 338 def rev8 = "b101_0001".U 339 def pack = "b101_0010".U 340 def orh48 = "b101_0011".U 341 342 def szewl1 = "b101_1000".U 343 def szewl2 = "b101_1001".U 344 def szewl3 = "b101_1010".U 345 def byte2 = "b101_1011".U 346 347 def andlsb = "b110_0000".U 348 def andzexth = "b110_0001".U 349 def orlsb = "b110_0010".U 350 def orzexth = "b110_0011".U 351 def xorlsb = "b110_0100".U 352 def xorzexth = "b110_0101".U 353 def orcblsb = "b110_0110".U 354 def orcbzexth = "b110_0111".U 355 def vsetvli1 = "b1000_0000".U 356 def vsetvli2 = "b1000_0100".U 357 def vsetvl1 = "b1000_0001".U 358 def vsetvl2 = "b1000_0101".U 359 def vsetivli1 = "b1000_0010".U 360 def vsetivli2 = "b1000_0110".U 361 362 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 363 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 364 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 365 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 366 def isBranch(func: UInt) = func(6, 4) === "b111".U 367 def getBranchType(func: UInt) = func(3, 2) 368 def isBranchInvert(func: UInt) = func(1) 369 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 370 def isVsetvl(func: UInt) = isVset(func) && func(0) 371 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 372 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 373 374 def apply() = UInt(FuOpTypeWidth.W) 375 } 376 377 object MDUOpType { 378 // mul 379 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 380 def mul = "b00000".U 381 def mulh = "b00001".U 382 def mulhsu = "b00010".U 383 def mulhu = "b00011".U 384 def mulw = "b00100".U 385 386 def mulw7 = "b01100".U 387 388 // div 389 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 390 def div = "b10000".U 391 def divu = "b10010".U 392 def rem = "b10001".U 393 def remu = "b10011".U 394 395 def divw = "b10100".U 396 def divuw = "b10110".U 397 def remw = "b10101".U 398 def remuw = "b10111".U 399 400 def isMul(op: UInt) = !op(4) 401 def isDiv(op: UInt) = op(4) 402 403 def isDivSign(op: UInt) = isDiv(op) && !op(1) 404 def isW(op: UInt) = op(2) 405 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 406 def getMulOp(op: UInt) = op(1, 0) 407 } 408 409 object LSUOpType { 410 // load pipeline 411 412 // normal load 413 // Note: bit(1, 0) are size, DO NOT CHANGE 414 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 415 def lb = "b0000".U 416 def lh = "b0001".U 417 def lw = "b0010".U 418 def ld = "b0011".U 419 def lbu = "b0100".U 420 def lhu = "b0101".U 421 def lwu = "b0110".U 422 423 // Zicbop software prefetch 424 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 425 def prefetch_i = "b1000".U // TODO 426 def prefetch_r = "b1001".U 427 def prefetch_w = "b1010".U 428 429 def isPrefetch(op: UInt): Bool = op(3) 430 431 // store pipeline 432 // normal store 433 // bit encoding: | store 00 | size(2bit) | 434 def sb = "b0000".U 435 def sh = "b0001".U 436 def sw = "b0010".U 437 def sd = "b0011".U 438 439 // l1 cache op 440 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 441 def cbo_zero = "b0111".U 442 443 // llc op 444 // bit encoding: | prefetch 11 | suboptype(2bit) | 445 def cbo_clean = "b1100".U 446 def cbo_flush = "b1101".U 447 def cbo_inval = "b1110".U 448 449 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 450 451 // atomics 452 // bit(1, 0) are size 453 // since atomics use a different fu type 454 // so we can safely reuse other load/store's encodings 455 // bit encoding: | optype(4bit) | size (2bit) | 456 def lr_w = "b000010".U 457 def sc_w = "b000110".U 458 def amoswap_w = "b001010".U 459 def amoadd_w = "b001110".U 460 def amoxor_w = "b010010".U 461 def amoand_w = "b010110".U 462 def amoor_w = "b011010".U 463 def amomin_w = "b011110".U 464 def amomax_w = "b100010".U 465 def amominu_w = "b100110".U 466 def amomaxu_w = "b101010".U 467 468 def lr_d = "b000011".U 469 def sc_d = "b000111".U 470 def amoswap_d = "b001011".U 471 def amoadd_d = "b001111".U 472 def amoxor_d = "b010011".U 473 def amoand_d = "b010111".U 474 def amoor_d = "b011011".U 475 def amomin_d = "b011111".U 476 def amomax_d = "b100011".U 477 def amominu_d = "b100111".U 478 def amomaxu_d = "b101011".U 479 480 def size(op: UInt) = op(1,0) 481 } 482 483 object BKUOpType { 484 485 def clmul = "b000000".U 486 def clmulh = "b000001".U 487 def clmulr = "b000010".U 488 def xpermn = "b000100".U 489 def xpermb = "b000101".U 490 491 def clz = "b001000".U 492 def clzw = "b001001".U 493 def ctz = "b001010".U 494 def ctzw = "b001011".U 495 def cpop = "b001100".U 496 def cpopw = "b001101".U 497 498 // 01xxxx is reserve 499 def aes64es = "b100000".U 500 def aes64esm = "b100001".U 501 def aes64ds = "b100010".U 502 def aes64dsm = "b100011".U 503 def aes64im = "b100100".U 504 def aes64ks1i = "b100101".U 505 def aes64ks2 = "b100110".U 506 507 // merge to two instruction sm4ks & sm4ed 508 def sm4ed0 = "b101000".U 509 def sm4ed1 = "b101001".U 510 def sm4ed2 = "b101010".U 511 def sm4ed3 = "b101011".U 512 def sm4ks0 = "b101100".U 513 def sm4ks1 = "b101101".U 514 def sm4ks2 = "b101110".U 515 def sm4ks3 = "b101111".U 516 517 def sha256sum0 = "b110000".U 518 def sha256sum1 = "b110001".U 519 def sha256sig0 = "b110010".U 520 def sha256sig1 = "b110011".U 521 def sha512sum0 = "b110100".U 522 def sha512sum1 = "b110101".U 523 def sha512sig0 = "b110110".U 524 def sha512sig1 = "b110111".U 525 526 def sm3p0 = "b111000".U 527 def sm3p1 = "b111001".U 528 } 529 530 object BTBtype { 531 def B = "b00".U // branch 532 def J = "b01".U // jump 533 def I = "b10".U // indirect 534 def R = "b11".U // return 535 536 def apply() = UInt(2.W) 537 } 538 539 object SelImm { 540 def IMM_X = "b0111".U 541 def IMM_S = "b1110".U 542 def IMM_SB = "b0001".U 543 def IMM_U = "b0010".U 544 def IMM_UJ = "b0011".U 545 def IMM_I = "b0100".U 546 def IMM_Z = "b0101".U 547 def INVALID_INSTR = "b0110".U 548 def IMM_B6 = "b1000".U 549 550 def IMM_OPIVIS = "b1001".U 551 def IMM_OPIVIU = "b1010".U 552 def IMM_VSETVLI = "b1100".U 553 def IMM_VSETIVLI = "b1101".U 554 555 def X = BitPat("b0000") 556 557 def apply() = UInt(4.W) 558 } 559 560 object UopDivType { 561 def SCA_SIM = "b000000".U // 562 def DIR = "b010001".U // dirty: vset 563 def VEC_VVV = "b010010".U // VEC_VVV 564 def VEC_VXV = "b010011".U // VEC_VXV 565 def VEC_0XV = "b010100".U // VEC_0XV 566 def VEC_VVW = "b010101".U // VEC_VVW 567 def VEC_WVW = "b010110".U // VEC_WVW 568 def VEC_VXW = "b010111".U // VEC_VXW 569 def VEC_WXW = "b011000".U // VEC_WXW 570 def VEC_WVV = "b011001".U // VEC_WVV 571 def VEC_WXV = "b011010".U // VEC_WXV 572 def VEC_EXT2 = "b011011".U // VF2 0 -> V 573 def VEC_EXT4 = "b011100".U // VF4 0 -> V 574 def VEC_EXT8 = "b011101".U // VF8 0 -> V 575 def VEC_VVM = "b011110".U // VEC_VVM 576 def VEC_VXM = "b011111".U // VEC_VXM 577 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 578 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 579 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 580 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 581 def VEC_VRED = "b100100".U // VEC_VRED 582 def VEC_MMM = "b000000".U // VEC_MMM 583 def dummy = "b111111".U 584 585 def X = BitPat("b000000") 586 587 def apply() = UInt(6.W) 588 def needSplit(UopDivType: UInt) = UopDivType(4) || UopDivType(5) 589 } 590 591 object ExceptionNO { 592 def instrAddrMisaligned = 0 593 def instrAccessFault = 1 594 def illegalInstr = 2 595 def breakPoint = 3 596 def loadAddrMisaligned = 4 597 def loadAccessFault = 5 598 def storeAddrMisaligned = 6 599 def storeAccessFault = 7 600 def ecallU = 8 601 def ecallS = 9 602 def ecallM = 11 603 def instrPageFault = 12 604 def loadPageFault = 13 605 // def singleStep = 14 606 def storePageFault = 15 607 def priorities = Seq( 608 breakPoint, // TODO: different BP has different priority 609 instrPageFault, 610 instrAccessFault, 611 illegalInstr, 612 instrAddrMisaligned, 613 ecallM, ecallS, ecallU, 614 storeAddrMisaligned, 615 loadAddrMisaligned, 616 storePageFault, 617 loadPageFault, 618 storeAccessFault, 619 loadAccessFault 620 ) 621 def all = priorities.distinct.sorted 622 def frontendSet = Seq( 623 instrAddrMisaligned, 624 instrAccessFault, 625 illegalInstr, 626 instrPageFault 627 ) 628 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 629 val new_vec = Wire(ExceptionVec()) 630 new_vec.foreach(_ := false.B) 631 select.foreach(i => new_vec(i) := vec(i)) 632 new_vec 633 } 634 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 635 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 636 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 637 partialSelect(vec, fuConfig.exceptionOut) 638 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 639 partialSelect(vec, exuConfig.exceptionOut) 640 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 641 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 642 } 643 644 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 645 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 646 def aluGen(p: Parameters) = new Alu()(p) 647 def bkuGen(p: Parameters) = new Bku()(p) 648 def jmpGen(p: Parameters) = new Jump()(p) 649 def fenceGen(p: Parameters) = new Fence()(p) 650 def csrGen(p: Parameters) = new CSR()(p) 651 def i2fGen(p: Parameters) = new IntToFP()(p) 652 def fmacGen(p: Parameters) = new FMA()(p) 653 def f2iGen(p: Parameters) = new FPToInt()(p) 654 def f2fGen(p: Parameters) = new FPToFP()(p) 655 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 656 def stdGen(p: Parameters) = new Std()(p) 657 def mouDataGen(p: Parameters) = new Std()(p) 658 def vipuGen(p: Parameters) = new VIPU()(p) 659 def vialuFGen(p: Parameters) = new VIAluFix()(p) 660 def vppuGen(p: Parameters) = new VPerm()(p) 661 def vfpuGen(p: Parameters) = new VFPU()(p) 662 663 def f2iSel(uop: MicroOp): Bool = { 664 uop.ctrl.rfWen 665 } 666 667 def i2fSel(uop: MicroOp): Bool = { 668 uop.ctrl.fpu.fromInt 669 } 670 671 def f2fSel(uop: MicroOp): Bool = { 672 val ctrl = uop.ctrl.fpu 673 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 674 } 675 676 def fdivSqrtSel(uop: MicroOp): Bool = { 677 val ctrl = uop.ctrl.fpu 678 ctrl.div || ctrl.sqrt 679 } 680 681 val aluCfg = FuConfig( 682 name = "alu", 683 fuGen = aluGen, 684 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 685 fuType = FuType.alu, 686 numIntSrc = 2, 687 numFpSrc = 0, 688 writeIntRf = true, 689 writeFpRf = false, 690 hasRedirect = true, 691 ) 692 693 val jmpCfg = FuConfig( 694 name = "jmp", 695 fuGen = jmpGen, 696 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 697 fuType = FuType.jmp, 698 numIntSrc = 1, 699 numFpSrc = 0, 700 writeIntRf = true, 701 writeFpRf = false, 702 hasRedirect = true, 703 ) 704 705 val fenceCfg = FuConfig( 706 name = "fence", 707 fuGen = fenceGen, 708 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 709 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 710 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 711 flushPipe = true 712 ) 713 714 val csrCfg = FuConfig( 715 name = "csr", 716 fuGen = csrGen, 717 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 718 fuType = FuType.csr, 719 numIntSrc = 1, 720 numFpSrc = 0, 721 writeIntRf = true, 722 writeFpRf = false, 723 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 724 flushPipe = true 725 ) 726 727 val i2fCfg = FuConfig( 728 name = "i2f", 729 fuGen = i2fGen, 730 fuSel = i2fSel, 731 FuType.i2f, 732 numIntSrc = 1, 733 numFpSrc = 0, 734 writeIntRf = false, 735 writeFpRf = true, 736 writeFflags = true, 737 latency = CertainLatency(2), 738 fastUopOut = true, fastImplemented = true 739 ) 740 741 val divCfg = FuConfig( 742 name = "div", 743 fuGen = dividerGen, 744 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 745 FuType.div, 746 2, 747 0, 748 writeIntRf = true, 749 writeFpRf = false, 750 latency = UncertainLatency(), 751 fastUopOut = true, 752 fastImplemented = true, 753 hasInputBuffer = (true, 4, true) 754 ) 755 756 val mulCfg = FuConfig( 757 name = "mul", 758 fuGen = multiplierGen, 759 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 760 FuType.mul, 761 2, 762 0, 763 writeIntRf = true, 764 writeFpRf = false, 765 latency = CertainLatency(2), 766 fastUopOut = true, 767 fastImplemented = true 768 ) 769 770 val bkuCfg = FuConfig( 771 name = "bku", 772 fuGen = bkuGen, 773 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 774 fuType = FuType.bku, 775 numIntSrc = 2, 776 numFpSrc = 0, 777 writeIntRf = true, 778 writeFpRf = false, 779 latency = CertainLatency(1), 780 fastUopOut = true, 781 fastImplemented = true 782 ) 783 784 val fmacCfg = FuConfig( 785 name = "fmac", 786 fuGen = fmacGen, 787 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fmac, 788 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 789 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 790 ) 791 792 val f2iCfg = FuConfig( 793 name = "f2i", 794 fuGen = f2iGen, 795 fuSel = f2iSel, 796 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 797 fastUopOut = true, fastImplemented = true 798 ) 799 800 val f2fCfg = FuConfig( 801 name = "f2f", 802 fuGen = f2fGen, 803 fuSel = f2fSel, 804 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 805 fastUopOut = true, fastImplemented = true 806 ) 807 808 val fdivSqrtCfg = FuConfig( 809 name = "fdivSqrt", 810 fuGen = fdivSqrtGen, 811 fuSel = fdivSqrtSel, 812 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 813 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 814 ) 815 816 val lduCfg = FuConfig( 817 "ldu", 818 null, // DontCare 819 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 820 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 821 latency = UncertainLatency(), 822 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 823 flushPipe = true, 824 replayInst = true, 825 hasLoadError = true 826 ) 827 828 val staCfg = FuConfig( 829 "sta", 830 null, 831 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 832 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 833 latency = UncertainLatency(), 834 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 835 ) 836 837 val stdCfg = FuConfig( 838 "std", 839 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 840 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 841 ) 842 843 val mouCfg = FuConfig( 844 "mou", 845 null, 846 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 847 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 848 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 849 ) 850 851 val mouDataCfg = FuConfig( 852 "mou", 853 mouDataGen, 854 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 855 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 856 latency = UncertainLatency() 857 ) 858 859 val vipuCfg = FuConfig( 860 name = "vipu", 861 fuGen = vipuGen, 862 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 863 fuType = FuType.vipu, 864 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, writeVxsat = true, 865 numVecSrc = 4, writeVecRf = true, 866 fastUopOut = false, // TODO: check 867 fastImplemented = true, //TODO: check 868 ) 869 870 val vialuFCfg = FuConfig( 871 name = "vialuF", 872 fuGen = vialuFGen, 873 fuSel = (uop: MicroOp) => FuType.vialuF === uop.ctrl.fuType, 874 fuType = FuType.vialuF, 875 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, writeVxsat = true, 876 numVecSrc = 4, writeVecRf = true, 877 fastUopOut = false, // TODO: check 878 fastImplemented = true, //TODO: check 879 ) 880 881 val vppuCfg = FuConfig( 882 name = "vppu", 883 fuGen = vppuGen, 884 fuSel = (uop: MicroOp) => FuType.vppu === uop.ctrl.fuType, 885 fuType = FuType.vppu, 886 numIntSrc = 0, numFpSrc = 1, writeIntRf = false, writeFpRf = false, writeFflags = false, 887 numVecSrc = 1, writeVecRf = true, 888 fastUopOut = false, // TODO: check 889 fastImplemented = true, //TODO: check 890 ) 891 892 val vfpuCfg = FuConfig( 893 name = "vfpu", 894 fuGen = vfpuGen, 895 fuSel = (uop: MicroOp) => FuType.vfpu === uop.ctrl.fuType, 896 fuType = FuType.vfpu, 897 numIntSrc = 0, numFpSrc = 1, writeIntRf = false, writeFpRf = false, writeFflags = true, 898 numVecSrc = 3, writeVecRf = true, 899 fastUopOut = false, // TODO: check 900 fastImplemented = true, //TODO: check 901 // latency = CertainLatency(2) 902 ) 903 904 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 905 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 906 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 907 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 908 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg, vppuCfg, vfpuCfg, vialuFCfg), Int.MaxValue, 0) 909 val FmiscExeUnitCfg = ExuConfig( 910 "FmiscExeUnit", 911 "Fp", 912 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 913 Int.MaxValue, 1 914 ) 915 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 916 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 917 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 918 919 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 920 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 921 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 922 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 923 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 924 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 925 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 926 927 val aluRSMod = new RSMod( 928 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 929 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 930 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 931 ) 932 val fmaRSMod = new RSMod( 933 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 934 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 935 ) 936 val fmiscRSMod = new RSMod( 937 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 938 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 939 ) 940 val jumpRSMod = new RSMod( 941 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 942 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 943 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 944 ) 945 val loadRSMod = new RSMod( 946 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 947 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 948 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 949 ) 950 val mulRSMod = new RSMod( 951 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 952 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 953 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 954 ) 955 val staRSMod = new RSMod( 956 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 957 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 958 ) 959 val stdRSMod = new RSMod( 960 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 961 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 962 ) 963} 964