1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isFp(srcType: UInt) = srcType(1) 46 def isVp(srcType: UInt) = srcType(2) 47 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 48 49 def isNull(srcType: UInt) = !(isPcOrImm(srcType) || isReg(srcType) || 50 isFp(srcType) || isVp(srcType)) 51 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 } 61 62 // Todo: Use OH instead 63 object FuType { 64 def jmp = "b00000".U 65 def i2f = "b00001".U 66 def csr = "b00010".U 67 def alu = "b00110".U 68 def mul = "b00100".U 69 def div = "b00101".U 70 def fence = "b00011".U 71 def bku = "b00111".U 72 73 def fmac = "b01000".U 74 def fmisc = "b01011".U 75 def fDivSqrt = "b01010".U 76 77 def ldu = "b01100".U 78 def stu = "b01101".U 79 def mou = "b01111".U // for amo, lr, sc, fence 80 81 def vipu = "b10000".U 82 def vimac = "b10010".U // for VIMacU 83 def vialuF = "b10001".U // for VIALU Fixed-Point instructions 84 def vfpu = "b11000".U 85 def vldu = "b11100".U 86 def vstu = "b11101".U 87 def vppu = "b11001".U // for Permutation Unit 88 def X = BitPat("b00000") // TODO: It may be a potential bug 89 90 def num = 19 91 92 def apply() = UInt(log2Up(num).W) 93 94 // TODO: Optimize FuTpye and its method 95 // FIXME: Vector FuType coding is not ready 96 def isVecExu(fuType: UInt) = fuType(4) 97 def isIntExu(fuType: UInt) = !isVecExu(fuType) && !fuType(3) 98 def isJumpExu(fuType: UInt) = fuType === jmp 99 def isFpExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b10".U) 100 def isMemExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b11".U) 101 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 102 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 103 def isAMO(fuType: UInt) = fuType(1) 104 def isFence(fuType: UInt) = fuType === fence 105 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 106 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 107 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 108 109 def jmpCanAccept(fuType: UInt) = !fuType(2) 110 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 111 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 112 113 def fmacCanAccept(fuType: UInt) = !fuType(1) 114 def fmiscCanAccept(fuType: UInt) = fuType(1) 115 116 def loadCanAccept(fuType: UInt) = !fuType(0) 117 def storeCanAccept(fuType: UInt) = fuType(0) 118 119 def storeIsAMO(fuType: UInt) = fuType(1) 120 121 val functionNameMap = Map( 122 jmp.litValue() -> "jmp", 123 i2f.litValue() -> "int_to_float", 124 csr.litValue() -> "csr", 125 alu.litValue() -> "alu", 126 mul.litValue() -> "mul", 127 div.litValue() -> "div", 128 fence.litValue() -> "fence", 129 bku.litValue() -> "bku", 130 fmac.litValue() -> "fmac", 131 fmisc.litValue() -> "fmisc", 132 fDivSqrt.litValue() -> "fdiv_fsqrt", 133 ldu.litValue() -> "load", 134 stu.litValue() -> "store", 135 mou.litValue() -> "mou" 136 ) 137 } 138 139 def FuOpTypeWidth = 8 140 object FuOpType { 141 def apply() = UInt(FuOpTypeWidth.W) 142 def X = BitPat("b00000000") 143 } 144 145 // move VipuType and VfpuType into YunSuan/package.scala 146 // object VipuType { 147 // def dummy = 0.U(7.W) 148 // } 149 150 // object VfpuType { 151 // def dummy = 0.U(7.W) 152 // } 153 154 object VlduType { 155 def dummy = 0.U 156 } 157 158 object VstuType { 159 def dummy = 0.U 160 } 161 162 object CommitType { 163 def NORMAL = "b000".U // int/fp 164 def BRANCH = "b001".U // branch 165 def LOAD = "b010".U // load 166 def STORE = "b011".U // store 167 168 def apply() = UInt(3.W) 169 def isFused(commitType: UInt): Bool = commitType(2) 170 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 171 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 172 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 173 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 174 } 175 176 object RedirectLevel { 177 def flushAfter = "b0".U 178 def flush = "b1".U 179 180 def apply() = UInt(1.W) 181 // def isUnconditional(level: UInt) = level(1) 182 def flushItself(level: UInt) = level(0) 183 // def isException(level: UInt) = level(1) && level(0) 184 } 185 186 object ExceptionVec { 187 def apply() = Vec(16, Bool()) 188 } 189 190 object PMAMode { 191 def R = "b1".U << 0 //readable 192 def W = "b1".U << 1 //writeable 193 def X = "b1".U << 2 //executable 194 def I = "b1".U << 3 //cacheable: icache 195 def D = "b1".U << 4 //cacheable: dcache 196 def S = "b1".U << 5 //enable speculative access 197 def A = "b1".U << 6 //enable atomic operation, A imply R & W 198 def C = "b1".U << 7 //if it is cacheable is configable 199 def Reserved = "b0".U 200 201 def apply() = UInt(7.W) 202 203 def read(mode: UInt) = mode(0) 204 def write(mode: UInt) = mode(1) 205 def execute(mode: UInt) = mode(2) 206 def icache(mode: UInt) = mode(3) 207 def dcache(mode: UInt) = mode(4) 208 def speculate(mode: UInt) = mode(5) 209 def atomic(mode: UInt) = mode(6) 210 def configable_cache(mode: UInt) = mode(7) 211 212 def strToMode(s: String) = { 213 var result = 0.U(8.W) 214 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 215 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 216 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 217 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 218 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 219 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 220 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 221 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 222 result 223 } 224 } 225 226 227 object CSROpType { 228 def jmp = "b000".U 229 def wrt = "b001".U 230 def set = "b010".U 231 def clr = "b011".U 232 def wfi = "b100".U 233 def wrti = "b101".U 234 def seti = "b110".U 235 def clri = "b111".U 236 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 237 } 238 239 // jump 240 object JumpOpType { 241 def jal = "b00".U 242 def jalr = "b01".U 243 def auipc = "b10".U 244// def call = "b11_011".U 245// def ret = "b11_100".U 246 def jumpOpisJalr(op: UInt) = op(0) 247 def jumpOpisAuipc(op: UInt) = op(1) 248 } 249 250 object FenceOpType { 251 def fence = "b10000".U 252 def sfence = "b10001".U 253 def fencei = "b10010".U 254 def nofence= "b00000".U 255 } 256 257 object ALUOpType { 258 // shift optype 259 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 260 def sll = "b000_0001".U // sll: src1 << src2 261 262 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 263 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 264 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 265 266 def srl = "b000_0101".U // srl: src1 >> src2 267 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 268 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 269 270 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 271 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 272 273 // RV64 32bit optype 274 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 275 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 276 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 277 278 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 279 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 280 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 281 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 282 283 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 284 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 285 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 286 def rolw = "b001_1100".U 287 def rorw = "b001_1101".U 288 289 // ADD-op 290 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 291 def add = "b010_0001".U // add: src1 + src2 292 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 293 294 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 295 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 296 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 297 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 298 299 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 300 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 301 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 302 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 303 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 304 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 305 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 306 307 // SUB-op: src1 - src2 308 def sub = "b011_0000".U 309 def sltu = "b011_0001".U 310 def slt = "b011_0010".U 311 def maxu = "b011_0100".U 312 def minu = "b011_0101".U 313 def max = "b011_0110".U 314 def min = "b011_0111".U 315 316 // branch 317 def beq = "b111_0000".U 318 def bne = "b111_0010".U 319 def blt = "b111_1000".U 320 def bge = "b111_1010".U 321 def bltu = "b111_1100".U 322 def bgeu = "b111_1110".U 323 324 // misc optype 325 def and = "b100_0000".U 326 def andn = "b100_0001".U 327 def or = "b100_0010".U 328 def orn = "b100_0011".U 329 def xor = "b100_0100".U 330 def xnor = "b100_0101".U 331 def orcb = "b100_0110".U 332 333 def sextb = "b100_1000".U 334 def packh = "b100_1001".U 335 def sexth = "b100_1010".U 336 def packw = "b100_1011".U 337 338 def revb = "b101_0000".U 339 def rev8 = "b101_0001".U 340 def pack = "b101_0010".U 341 def orh48 = "b101_0011".U 342 343 def szewl1 = "b101_1000".U 344 def szewl2 = "b101_1001".U 345 def szewl3 = "b101_1010".U 346 def byte2 = "b101_1011".U 347 348 def andlsb = "b110_0000".U 349 def andzexth = "b110_0001".U 350 def orlsb = "b110_0010".U 351 def orzexth = "b110_0011".U 352 def xorlsb = "b110_0100".U 353 def xorzexth = "b110_0101".U 354 def orcblsb = "b110_0110".U 355 def orcbzexth = "b110_0111".U 356 def vsetvli1 = "b1000_0000".U 357 def vsetvli2 = "b1000_0100".U 358 def vsetvl1 = "b1000_0001".U 359 def vsetvl2 = "b1000_0101".U 360 def vsetivli1 = "b1000_0010".U 361 def vsetivli2 = "b1000_0110".U 362 363 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 364 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 365 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 366 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 367 def isBranch(func: UInt) = func(6, 4) === "b111".U 368 def getBranchType(func: UInt) = func(3, 2) 369 def isBranchInvert(func: UInt) = func(1) 370 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 371 def isVsetvl(func: UInt) = isVset(func) && func(0) 372 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 373 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 374 375 def apply() = UInt(FuOpTypeWidth.W) 376 } 377 378 object MDUOpType { 379 // mul 380 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 381 def mul = "b00000".U 382 def mulh = "b00001".U 383 def mulhsu = "b00010".U 384 def mulhu = "b00011".U 385 def mulw = "b00100".U 386 387 def mulw7 = "b01100".U 388 389 // div 390 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 391 def div = "b10000".U 392 def divu = "b10010".U 393 def rem = "b10001".U 394 def remu = "b10011".U 395 396 def divw = "b10100".U 397 def divuw = "b10110".U 398 def remw = "b10101".U 399 def remuw = "b10111".U 400 401 def isMul(op: UInt) = !op(4) 402 def isDiv(op: UInt) = op(4) 403 404 def isDivSign(op: UInt) = isDiv(op) && !op(1) 405 def isW(op: UInt) = op(2) 406 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 407 def getMulOp(op: UInt) = op(1, 0) 408 } 409 410 object LSUOpType { 411 // load pipeline 412 413 // normal load 414 // Note: bit(1, 0) are size, DO NOT CHANGE 415 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 416 def lb = "b0000".U 417 def lh = "b0001".U 418 def lw = "b0010".U 419 def ld = "b0011".U 420 def lbu = "b0100".U 421 def lhu = "b0101".U 422 def lwu = "b0110".U 423 424 // Zicbop software prefetch 425 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 426 def prefetch_i = "b1000".U // TODO 427 def prefetch_r = "b1001".U 428 def prefetch_w = "b1010".U 429 430 def isPrefetch(op: UInt): Bool = op(3) 431 432 // store pipeline 433 // normal store 434 // bit encoding: | store 00 | size(2bit) | 435 def sb = "b0000".U 436 def sh = "b0001".U 437 def sw = "b0010".U 438 def sd = "b0011".U 439 440 // l1 cache op 441 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 442 def cbo_zero = "b0111".U 443 444 // llc op 445 // bit encoding: | prefetch 11 | suboptype(2bit) | 446 def cbo_clean = "b1100".U 447 def cbo_flush = "b1101".U 448 def cbo_inval = "b1110".U 449 450 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 451 452 // atomics 453 // bit(1, 0) are size 454 // since atomics use a different fu type 455 // so we can safely reuse other load/store's encodings 456 // bit encoding: | optype(4bit) | size (2bit) | 457 def lr_w = "b000010".U 458 def sc_w = "b000110".U 459 def amoswap_w = "b001010".U 460 def amoadd_w = "b001110".U 461 def amoxor_w = "b010010".U 462 def amoand_w = "b010110".U 463 def amoor_w = "b011010".U 464 def amomin_w = "b011110".U 465 def amomax_w = "b100010".U 466 def amominu_w = "b100110".U 467 def amomaxu_w = "b101010".U 468 469 def lr_d = "b000011".U 470 def sc_d = "b000111".U 471 def amoswap_d = "b001011".U 472 def amoadd_d = "b001111".U 473 def amoxor_d = "b010011".U 474 def amoand_d = "b010111".U 475 def amoor_d = "b011011".U 476 def amomin_d = "b011111".U 477 def amomax_d = "b100011".U 478 def amominu_d = "b100111".U 479 def amomaxu_d = "b101011".U 480 481 def size(op: UInt) = op(1,0) 482 } 483 484 object BKUOpType { 485 486 def clmul = "b000000".U 487 def clmulh = "b000001".U 488 def clmulr = "b000010".U 489 def xpermn = "b000100".U 490 def xpermb = "b000101".U 491 492 def clz = "b001000".U 493 def clzw = "b001001".U 494 def ctz = "b001010".U 495 def ctzw = "b001011".U 496 def cpop = "b001100".U 497 def cpopw = "b001101".U 498 499 // 01xxxx is reserve 500 def aes64es = "b100000".U 501 def aes64esm = "b100001".U 502 def aes64ds = "b100010".U 503 def aes64dsm = "b100011".U 504 def aes64im = "b100100".U 505 def aes64ks1i = "b100101".U 506 def aes64ks2 = "b100110".U 507 508 // merge to two instruction sm4ks & sm4ed 509 def sm4ed0 = "b101000".U 510 def sm4ed1 = "b101001".U 511 def sm4ed2 = "b101010".U 512 def sm4ed3 = "b101011".U 513 def sm4ks0 = "b101100".U 514 def sm4ks1 = "b101101".U 515 def sm4ks2 = "b101110".U 516 def sm4ks3 = "b101111".U 517 518 def sha256sum0 = "b110000".U 519 def sha256sum1 = "b110001".U 520 def sha256sig0 = "b110010".U 521 def sha256sig1 = "b110011".U 522 def sha512sum0 = "b110100".U 523 def sha512sum1 = "b110101".U 524 def sha512sig0 = "b110110".U 525 def sha512sig1 = "b110111".U 526 527 def sm3p0 = "b111000".U 528 def sm3p1 = "b111001".U 529 } 530 531 object BTBtype { 532 def B = "b00".U // branch 533 def J = "b01".U // jump 534 def I = "b10".U // indirect 535 def R = "b11".U // return 536 537 def apply() = UInt(2.W) 538 } 539 540 object SelImm { 541 def IMM_X = "b0111".U 542 def IMM_S = "b1110".U 543 def IMM_SB = "b0001".U 544 def IMM_U = "b0010".U 545 def IMM_UJ = "b0011".U 546 def IMM_I = "b0100".U 547 def IMM_Z = "b0101".U 548 def INVALID_INSTR = "b0110".U 549 def IMM_B6 = "b1000".U 550 551 def IMM_OPIVIS = "b1001".U 552 def IMM_OPIVIU = "b1010".U 553 def IMM_VSETVLI = "b1100".U 554 def IMM_VSETIVLI = "b1101".U 555 556 def X = BitPat("b0000") 557 558 def apply() = UInt(4.W) 559 } 560 561 object UopSplitType { 562 def SCA_SIM = "b000000".U // 563 def DIR = "b010001".U // dirty: vset 564 def VEC_VVV = "b010010".U // VEC_VVV 565 def VEC_VXV = "b010011".U // VEC_VXV 566 def VEC_0XV = "b010100".U // VEC_0XV 567 def VEC_VVW = "b010101".U // VEC_VVW 568 def VEC_WVW = "b010110".U // VEC_WVW 569 def VEC_VXW = "b010111".U // VEC_VXW 570 def VEC_WXW = "b011000".U // VEC_WXW 571 def VEC_WVV = "b011001".U // VEC_WVV 572 def VEC_WXV = "b011010".U // VEC_WXV 573 def VEC_EXT2 = "b011011".U // VF2 0 -> V 574 def VEC_EXT4 = "b011100".U // VF4 0 -> V 575 def VEC_EXT8 = "b011101".U // VF8 0 -> V 576 def VEC_VVM = "b011110".U // VEC_VVM 577 def VEC_VXM = "b011111".U // VEC_VXM 578 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 579 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 580 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 581 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 582 def VEC_VRED = "b100100".U // VEC_VRED 583 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 584 def VEC_ISLIDEUP = "b100110".U // VEC_ISLIDEUP 585 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 586 def VEC_ISLIDEDOWN = "b101000".U // VEC_ISLIDEDOWN 587 def VEC_M0X = "b101001".U // VEC_M0X 0MV 588 def VEC_MVV = "b101010".U // VEC_MVV VMV 589 def VEC_M0X_VFIRST = "b101011".U // 590 def VEC_VWW = "b101100".U // 591 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 592 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 593 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 594 def VEC_COMPRESS = "b110000".U // vcompress.vm 595 def VEC_M0M = "b000000".U // VEC_M0M 596 def VEC_MMM = "b000000".U // VEC_MMM 597 def dummy = "b111111".U 598 599 def X = BitPat("b000000") 600 601 def apply() = UInt(6.W) 602 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 603 } 604 605 object ExceptionNO { 606 def instrAddrMisaligned = 0 607 def instrAccessFault = 1 608 def illegalInstr = 2 609 def breakPoint = 3 610 def loadAddrMisaligned = 4 611 def loadAccessFault = 5 612 def storeAddrMisaligned = 6 613 def storeAccessFault = 7 614 def ecallU = 8 615 def ecallS = 9 616 def ecallM = 11 617 def instrPageFault = 12 618 def loadPageFault = 13 619 // def singleStep = 14 620 def storePageFault = 15 621 def priorities = Seq( 622 breakPoint, // TODO: different BP has different priority 623 instrPageFault, 624 instrAccessFault, 625 illegalInstr, 626 instrAddrMisaligned, 627 ecallM, ecallS, ecallU, 628 storeAddrMisaligned, 629 loadAddrMisaligned, 630 storePageFault, 631 loadPageFault, 632 storeAccessFault, 633 loadAccessFault 634 ) 635 def all = priorities.distinct.sorted 636 def frontendSet = Seq( 637 instrAddrMisaligned, 638 instrAccessFault, 639 illegalInstr, 640 instrPageFault 641 ) 642 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 643 val new_vec = Wire(ExceptionVec()) 644 new_vec.foreach(_ := false.B) 645 select.foreach(i => new_vec(i) := vec(i)) 646 new_vec 647 } 648 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 649 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 650 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 651 partialSelect(vec, fuConfig.exceptionOut) 652 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 653 partialSelect(vec, exuConfig.exceptionOut) 654 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 655 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 656 } 657 658 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 659 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 660 def aluGen(p: Parameters) = new Alu()(p) 661 def bkuGen(p: Parameters) = new Bku()(p) 662 def jmpGen(p: Parameters) = new Jump()(p) 663 def fenceGen(p: Parameters) = new Fence()(p) 664 def csrGen(p: Parameters) = new CSR()(p) 665 def i2fGen(p: Parameters) = new IntToFP()(p) 666 def fmacGen(p: Parameters) = new FMA()(p) 667 def f2iGen(p: Parameters) = new FPToInt()(p) 668 def f2fGen(p: Parameters) = new FPToFP()(p) 669 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 670 def stdGen(p: Parameters) = new Std()(p) 671 def mouDataGen(p: Parameters) = new Std()(p) 672 def vipuGen(p: Parameters) = new VIPU()(p) 673 def vimacGen(p: Parameters) = new VIMacU()(p) 674 def vialuFGen(p: Parameters) = new VIAluFix()(p) 675 def vppuGen(p: Parameters) = new VPerm()(p) 676 def vfpuGen(p: Parameters) = new VFPU()(p) 677 678 def f2iSel(uop: MicroOp): Bool = { 679 uop.ctrl.rfWen 680 } 681 682 def i2fSel(uop: MicroOp): Bool = { 683 uop.ctrl.fpu.fromInt 684 } 685 686 def f2fSel(uop: MicroOp): Bool = { 687 val ctrl = uop.ctrl.fpu 688 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 689 } 690 691 def fdivSqrtSel(uop: MicroOp): Bool = { 692 val ctrl = uop.ctrl.fpu 693 ctrl.div || ctrl.sqrt 694 } 695 696 val aluCfg = FuConfig( 697 name = "alu", 698 fuGen = aluGen, 699 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 700 fuType = FuType.alu, 701 numIntSrc = 2, 702 numFpSrc = 0, 703 writeIntRf = true, 704 writeFpRf = false, 705 hasRedirect = true, 706 ) 707 708 val jmpCfg = FuConfig( 709 name = "jmp", 710 fuGen = jmpGen, 711 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 712 fuType = FuType.jmp, 713 numIntSrc = 1, 714 numFpSrc = 0, 715 writeIntRf = true, 716 writeFpRf = false, 717 hasRedirect = true, 718 ) 719 720 val fenceCfg = FuConfig( 721 name = "fence", 722 fuGen = fenceGen, 723 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 724 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 725 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 726 flushPipe = true 727 ) 728 729 val csrCfg = FuConfig( 730 name = "csr", 731 fuGen = csrGen, 732 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 733 fuType = FuType.csr, 734 numIntSrc = 1, 735 numFpSrc = 0, 736 writeIntRf = true, 737 writeFpRf = false, 738 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 739 flushPipe = true 740 ) 741 742 val i2fCfg = FuConfig( 743 name = "i2f", 744 fuGen = i2fGen, 745 fuSel = i2fSel, 746 FuType.i2f, 747 numIntSrc = 1, 748 numFpSrc = 0, 749 writeIntRf = false, 750 writeFpRf = true, 751 writeFflags = true, 752 latency = CertainLatency(2), 753 fastUopOut = true, fastImplemented = true 754 ) 755 756 val divCfg = FuConfig( 757 name = "div", 758 fuGen = dividerGen, 759 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 760 FuType.div, 761 2, 762 0, 763 writeIntRf = true, 764 writeFpRf = false, 765 latency = UncertainLatency(), 766 fastUopOut = true, 767 fastImplemented = true, 768 hasInputBuffer = (true, 4, true) 769 ) 770 771 val mulCfg = FuConfig( 772 name = "mul", 773 fuGen = multiplierGen, 774 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 775 FuType.mul, 776 2, 777 0, 778 writeIntRf = true, 779 writeFpRf = false, 780 latency = CertainLatency(2), 781 fastUopOut = true, 782 fastImplemented = true 783 ) 784 785 val bkuCfg = FuConfig( 786 name = "bku", 787 fuGen = bkuGen, 788 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 789 fuType = FuType.bku, 790 numIntSrc = 2, 791 numFpSrc = 0, 792 writeIntRf = true, 793 writeFpRf = false, 794 latency = CertainLatency(1), 795 fastUopOut = true, 796 fastImplemented = true 797 ) 798 799 val fmacCfg = FuConfig( 800 name = "fmac", 801 fuGen = fmacGen, 802 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fmac, 803 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 804 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 805 ) 806 807 val f2iCfg = FuConfig( 808 name = "f2i", 809 fuGen = f2iGen, 810 fuSel = f2iSel, 811 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 812 fastUopOut = true, fastImplemented = true 813 ) 814 815 val f2fCfg = FuConfig( 816 name = "f2f", 817 fuGen = f2fGen, 818 fuSel = f2fSel, 819 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 820 fastUopOut = true, fastImplemented = true 821 ) 822 823 val fdivSqrtCfg = FuConfig( 824 name = "fdivSqrt", 825 fuGen = fdivSqrtGen, 826 fuSel = fdivSqrtSel, 827 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 828 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 829 ) 830 831 val lduCfg = FuConfig( 832 "ldu", 833 null, // DontCare 834 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 835 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 836 latency = UncertainLatency(), 837 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 838 flushPipe = true, 839 replayInst = true, 840 hasLoadError = true 841 ) 842 843 val staCfg = FuConfig( 844 "sta", 845 null, 846 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 847 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 848 latency = UncertainLatency(), 849 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 850 ) 851 852 val stdCfg = FuConfig( 853 "std", 854 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 855 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 856 ) 857 858 val mouCfg = FuConfig( 859 "mou", 860 null, 861 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 862 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 863 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 864 ) 865 866 val mouDataCfg = FuConfig( 867 "mou", 868 mouDataGen, 869 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 870 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 871 latency = UncertainLatency() 872 ) 873 874 val vipuCfg = FuConfig( 875 name = "vipu", 876 fuGen = vipuGen, 877 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 878 fuType = FuType.vipu, 879 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, writeVxsat = true, 880 numVecSrc = 4, writeVecRf = true, 881 fastUopOut = false, // TODO: check 882 fastImplemented = true, //TODO: check 883 ) 884 885 val vimacCfg = FuConfig( 886 name = "vimac", 887 fuGen = vimacGen, 888 fuSel = (uop: MicroOp) => FuType.vimac === uop.ctrl.fuType, 889 fuType = FuType.vimac, 890 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, writeVxsat = true, 891 numVecSrc = 4, writeVecRf = true, 892 fastUopOut = false, // TODO: check 893 fastImplemented = true, //TODO: check 894 ) 895 896 val vialuFCfg = FuConfig( 897 name = "vialuF", 898 fuGen = vialuFGen, 899 fuSel = (uop: MicroOp) => FuType.vialuF === uop.ctrl.fuType, 900 fuType = FuType.vialuF, 901 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, writeVxsat = true, 902 numVecSrc = 4, writeVecRf = true, 903 fastUopOut = false, // TODO: check 904 fastImplemented = true, //TODO: check 905 ) 906 907 val vppuCfg = FuConfig( 908 name = "vppu", 909 fuGen = vppuGen, 910 fuSel = (uop: MicroOp) => FuType.vppu === uop.ctrl.fuType, 911 fuType = FuType.vppu, 912 numIntSrc = 0, numFpSrc = 1, writeIntRf = false, writeFpRf = false, writeFflags = false, 913 numVecSrc = 1, writeVecRf = true, 914 fastUopOut = false, // TODO: check 915 fastImplemented = true, //TODO: check 916 ) 917 918 val vfpuCfg = FuConfig( 919 name = "vfpu", 920 fuGen = vfpuGen, 921 fuSel = (uop: MicroOp) => FuType.vfpu === uop.ctrl.fuType, 922 fuType = FuType.vfpu, 923 numIntSrc = 0, numFpSrc = 1, writeIntRf = false, writeFpRf = false, writeFflags = true, 924 numVecSrc = 3, writeVecRf = true, 925 fastUopOut = false, // TODO: check 926 fastImplemented = true, //TODO: check 927 // latency = CertainLatency(2) 928 ) 929 930 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 931 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 932 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 933 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 934 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg, vimacCfg, vppuCfg, vfpuCfg, vialuFCfg), Int.MaxValue, 0) 935 val FmiscExeUnitCfg = ExuConfig( 936 "FmiscExeUnit", 937 "Fp", 938 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 939 Int.MaxValue, 1 940 ) 941 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 942 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 943 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 944 945 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 946 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 947 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 948 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 949 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 950 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 951 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 952 953 val aluRSMod = new RSMod( 954 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 955 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 956 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 957 ) 958 val fmaRSMod = new RSMod( 959 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 960 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 961 ) 962 val fmiscRSMod = new RSMod( 963 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 964 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 965 ) 966 val jumpRSMod = new RSMod( 967 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 968 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 969 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 970 ) 971 val loadRSMod = new RSMod( 972 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 973 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 974 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 975 ) 976 val mulRSMod = new RSMod( 977 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 978 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 979 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 980 ) 981 val staRSMod = new RSMod( 982 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 983 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 984 ) 985 val stdRSMod = new RSMod( 986 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 987 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 988 ) 989} 990