1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isFp(srcType: UInt) = srcType(1) 46 def isVp(srcType: UInt) = srcType(2) 47 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 48 49 def isNull(srcType: UInt) = !(isPcOrImm(srcType) || isReg(srcType) || 50 isFp(srcType) || isVp(srcType)) 51 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 } 61 62 // Todo: Use OH instead 63 object FuType { 64 def jmp = "b00000".U 65 def i2f = "b00001".U 66 def csr = "b00010".U 67 def alu = "b00110".U 68 def mul = "b00100".U 69 def div = "b00101".U 70 def fence = "b00011".U 71 def bku = "b00111".U 72 73 def fmac = "b01000".U 74 def fmisc = "b01011".U 75 def fDivSqrt = "b01010".U 76 77 def ldu = "b01100".U 78 def stu = "b01101".U 79 def mou = "b01111".U // for amo, lr, sc, fence 80 81 def vipu = "b10000".U 82 def vfpu = "b11000".U 83 def vldu = "b11100".U 84 def vstu = "b11101".U 85 def vppu = "b11001".U // for Permutation Unit 86 def X = BitPat("b00000") // TODO: It may be a potential bug 87 88 def num = 19 89 90 def apply() = UInt(log2Up(num).W) 91 92 // TODO: Optimize FuTpye and its method 93 // FIXME: Vector FuType coding is not ready 94 def isVecExu(fuType: UInt) = fuType(4) 95 def isIntExu(fuType: UInt) = !isVecExu(fuType) && !fuType(3) 96 def isJumpExu(fuType: UInt) = fuType === jmp 97 def isFpExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b10".U) 98 def isMemExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b11".U) 99 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 100 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 101 def isAMO(fuType: UInt) = fuType(1) 102 def isFence(fuType: UInt) = fuType === fence 103 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 104 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 105 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 106 107 def jmpCanAccept(fuType: UInt) = !fuType(2) 108 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 109 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 110 111 def fmacCanAccept(fuType: UInt) = !fuType(1) 112 def fmiscCanAccept(fuType: UInt) = fuType(1) 113 114 def loadCanAccept(fuType: UInt) = !fuType(0) 115 def storeCanAccept(fuType: UInt) = fuType(0) 116 117 def storeIsAMO(fuType: UInt) = fuType(1) 118 119 val functionNameMap = Map( 120 jmp.litValue() -> "jmp", 121 i2f.litValue() -> "int_to_float", 122 csr.litValue() -> "csr", 123 alu.litValue() -> "alu", 124 mul.litValue() -> "mul", 125 div.litValue() -> "div", 126 fence.litValue() -> "fence", 127 bku.litValue() -> "bku", 128 fmac.litValue() -> "fmac", 129 fmisc.litValue() -> "fmisc", 130 fDivSqrt.litValue() -> "fdiv_fsqrt", 131 ldu.litValue() -> "load", 132 stu.litValue() -> "store", 133 mou.litValue() -> "mou" 134 ) 135 } 136 137 def FuOpTypeWidth = 8 138 object FuOpType { 139 def apply() = UInt(FuOpTypeWidth.W) 140 def X = BitPat("b00000000") 141 } 142 143 // move VipuType and VfpuType into YunSuan/package.scala 144 // object VipuType { 145 // def dummy = 0.U(7.W) 146 // } 147 148 // object VfpuType { 149 // def dummy = 0.U(7.W) 150 // } 151 152 object VlduType { 153 def dummy = 0.U 154 } 155 156 object VstuType { 157 def dummy = 0.U 158 } 159 160 object CommitType { 161 def NORMAL = "b000".U // int/fp 162 def BRANCH = "b001".U // branch 163 def LOAD = "b010".U // load 164 def STORE = "b011".U // store 165 166 def apply() = UInt(3.W) 167 def isFused(commitType: UInt): Bool = commitType(2) 168 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 169 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 170 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 171 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 172 } 173 174 object RedirectLevel { 175 def flushAfter = "b0".U 176 def flush = "b1".U 177 178 def apply() = UInt(1.W) 179 // def isUnconditional(level: UInt) = level(1) 180 def flushItself(level: UInt) = level(0) 181 // def isException(level: UInt) = level(1) && level(0) 182 } 183 184 object ExceptionVec { 185 def apply() = Vec(16, Bool()) 186 } 187 188 object PMAMode { 189 def R = "b1".U << 0 //readable 190 def W = "b1".U << 1 //writeable 191 def X = "b1".U << 2 //executable 192 def I = "b1".U << 3 //cacheable: icache 193 def D = "b1".U << 4 //cacheable: dcache 194 def S = "b1".U << 5 //enable speculative access 195 def A = "b1".U << 6 //enable atomic operation, A imply R & W 196 def C = "b1".U << 7 //if it is cacheable is configable 197 def Reserved = "b0".U 198 199 def apply() = UInt(7.W) 200 201 def read(mode: UInt) = mode(0) 202 def write(mode: UInt) = mode(1) 203 def execute(mode: UInt) = mode(2) 204 def icache(mode: UInt) = mode(3) 205 def dcache(mode: UInt) = mode(4) 206 def speculate(mode: UInt) = mode(5) 207 def atomic(mode: UInt) = mode(6) 208 def configable_cache(mode: UInt) = mode(7) 209 210 def strToMode(s: String) = { 211 var result = 0.U(8.W) 212 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 213 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 214 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 215 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 216 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 217 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 218 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 219 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 220 result 221 } 222 } 223 224 225 object CSROpType { 226 def jmp = "b000".U 227 def wrt = "b001".U 228 def set = "b010".U 229 def clr = "b011".U 230 def wfi = "b100".U 231 def wrti = "b101".U 232 def seti = "b110".U 233 def clri = "b111".U 234 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 235 } 236 237 // jump 238 object JumpOpType { 239 def jal = "b00".U 240 def jalr = "b01".U 241 def auipc = "b10".U 242// def call = "b11_011".U 243// def ret = "b11_100".U 244 def jumpOpisJalr(op: UInt) = op(0) 245 def jumpOpisAuipc(op: UInt) = op(1) 246 } 247 248 object FenceOpType { 249 def fence = "b10000".U 250 def sfence = "b10001".U 251 def fencei = "b10010".U 252 def nofence= "b00000".U 253 } 254 255 object ALUOpType { 256 // shift optype 257 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 258 def sll = "b000_0001".U // sll: src1 << src2 259 260 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 261 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 262 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 263 264 def srl = "b000_0101".U // srl: src1 >> src2 265 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 266 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 267 268 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 269 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 270 271 // RV64 32bit optype 272 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 273 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 274 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 275 276 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 277 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 278 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 279 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 280 281 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 282 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 283 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 284 def rolw = "b001_1100".U 285 def rorw = "b001_1101".U 286 287 // ADD-op 288 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 289 def add = "b010_0001".U // add: src1 + src2 290 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 291 292 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 293 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 294 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 295 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 296 297 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 298 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 299 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 300 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 301 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 302 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 303 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 304 305 // SUB-op: src1 - src2 306 def sub = "b011_0000".U 307 def sltu = "b011_0001".U 308 def slt = "b011_0010".U 309 def maxu = "b011_0100".U 310 def minu = "b011_0101".U 311 def max = "b011_0110".U 312 def min = "b011_0111".U 313 314 // branch 315 def beq = "b111_0000".U 316 def bne = "b111_0010".U 317 def blt = "b111_1000".U 318 def bge = "b111_1010".U 319 def bltu = "b111_1100".U 320 def bgeu = "b111_1110".U 321 322 // misc optype 323 def and = "b100_0000".U 324 def andn = "b100_0001".U 325 def or = "b100_0010".U 326 def orn = "b100_0011".U 327 def xor = "b100_0100".U 328 def xnor = "b100_0101".U 329 def orcb = "b100_0110".U 330 331 def sextb = "b100_1000".U 332 def packh = "b100_1001".U 333 def sexth = "b100_1010".U 334 def packw = "b100_1011".U 335 336 def revb = "b101_0000".U 337 def rev8 = "b101_0001".U 338 def pack = "b101_0010".U 339 def orh48 = "b101_0011".U 340 341 def szewl1 = "b101_1000".U 342 def szewl2 = "b101_1001".U 343 def szewl3 = "b101_1010".U 344 def byte2 = "b101_1011".U 345 346 def andlsb = "b110_0000".U 347 def andzexth = "b110_0001".U 348 def orlsb = "b110_0010".U 349 def orzexth = "b110_0011".U 350 def xorlsb = "b110_0100".U 351 def xorzexth = "b110_0101".U 352 def orcblsb = "b110_0110".U 353 def orcbzexth = "b110_0111".U 354 def vsetvli1 = "b1000_0000".U 355 def vsetvli2 = "b1000_0100".U 356 def vsetvl1 = "b1000_0001".U 357 def vsetvl2 = "b1000_0101".U 358 def vsetivli1 = "b1000_0010".U 359 def vsetivli2 = "b1000_0110".U 360 361 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 362 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 363 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 364 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 365 def isBranch(func: UInt) = func(6, 4) === "b111".U 366 def getBranchType(func: UInt) = func(3, 2) 367 def isBranchInvert(func: UInt) = func(1) 368 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 369 def isVsetvl(func: UInt) = isVset(func) && func(0) 370 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 371 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 372 373 def apply() = UInt(FuOpTypeWidth.W) 374 } 375 376 object MDUOpType { 377 // mul 378 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 379 def mul = "b00000".U 380 def mulh = "b00001".U 381 def mulhsu = "b00010".U 382 def mulhu = "b00011".U 383 def mulw = "b00100".U 384 385 def mulw7 = "b01100".U 386 387 // div 388 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 389 def div = "b10000".U 390 def divu = "b10010".U 391 def rem = "b10001".U 392 def remu = "b10011".U 393 394 def divw = "b10100".U 395 def divuw = "b10110".U 396 def remw = "b10101".U 397 def remuw = "b10111".U 398 399 def isMul(op: UInt) = !op(4) 400 def isDiv(op: UInt) = op(4) 401 402 def isDivSign(op: UInt) = isDiv(op) && !op(1) 403 def isW(op: UInt) = op(2) 404 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 405 def getMulOp(op: UInt) = op(1, 0) 406 } 407 408 object LSUOpType { 409 // load pipeline 410 411 // normal load 412 // Note: bit(1, 0) are size, DO NOT CHANGE 413 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 414 def lb = "b0000".U 415 def lh = "b0001".U 416 def lw = "b0010".U 417 def ld = "b0011".U 418 def lbu = "b0100".U 419 def lhu = "b0101".U 420 def lwu = "b0110".U 421 422 // Zicbop software prefetch 423 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 424 def prefetch_i = "b1000".U // TODO 425 def prefetch_r = "b1001".U 426 def prefetch_w = "b1010".U 427 428 def isPrefetch(op: UInt): Bool = op(3) 429 430 // store pipeline 431 // normal store 432 // bit encoding: | store 00 | size(2bit) | 433 def sb = "b0000".U 434 def sh = "b0001".U 435 def sw = "b0010".U 436 def sd = "b0011".U 437 438 // l1 cache op 439 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 440 def cbo_zero = "b0111".U 441 442 // llc op 443 // bit encoding: | prefetch 11 | suboptype(2bit) | 444 def cbo_clean = "b1100".U 445 def cbo_flush = "b1101".U 446 def cbo_inval = "b1110".U 447 448 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 449 450 // atomics 451 // bit(1, 0) are size 452 // since atomics use a different fu type 453 // so we can safely reuse other load/store's encodings 454 // bit encoding: | optype(4bit) | size (2bit) | 455 def lr_w = "b000010".U 456 def sc_w = "b000110".U 457 def amoswap_w = "b001010".U 458 def amoadd_w = "b001110".U 459 def amoxor_w = "b010010".U 460 def amoand_w = "b010110".U 461 def amoor_w = "b011010".U 462 def amomin_w = "b011110".U 463 def amomax_w = "b100010".U 464 def amominu_w = "b100110".U 465 def amomaxu_w = "b101010".U 466 467 def lr_d = "b000011".U 468 def sc_d = "b000111".U 469 def amoswap_d = "b001011".U 470 def amoadd_d = "b001111".U 471 def amoxor_d = "b010011".U 472 def amoand_d = "b010111".U 473 def amoor_d = "b011011".U 474 def amomin_d = "b011111".U 475 def amomax_d = "b100011".U 476 def amominu_d = "b100111".U 477 def amomaxu_d = "b101011".U 478 479 def size(op: UInt) = op(1,0) 480 } 481 482 object BKUOpType { 483 484 def clmul = "b000000".U 485 def clmulh = "b000001".U 486 def clmulr = "b000010".U 487 def xpermn = "b000100".U 488 def xpermb = "b000101".U 489 490 def clz = "b001000".U 491 def clzw = "b001001".U 492 def ctz = "b001010".U 493 def ctzw = "b001011".U 494 def cpop = "b001100".U 495 def cpopw = "b001101".U 496 497 // 01xxxx is reserve 498 def aes64es = "b100000".U 499 def aes64esm = "b100001".U 500 def aes64ds = "b100010".U 501 def aes64dsm = "b100011".U 502 def aes64im = "b100100".U 503 def aes64ks1i = "b100101".U 504 def aes64ks2 = "b100110".U 505 506 // merge to two instruction sm4ks & sm4ed 507 def sm4ed0 = "b101000".U 508 def sm4ed1 = "b101001".U 509 def sm4ed2 = "b101010".U 510 def sm4ed3 = "b101011".U 511 def sm4ks0 = "b101100".U 512 def sm4ks1 = "b101101".U 513 def sm4ks2 = "b101110".U 514 def sm4ks3 = "b101111".U 515 516 def sha256sum0 = "b110000".U 517 def sha256sum1 = "b110001".U 518 def sha256sig0 = "b110010".U 519 def sha256sig1 = "b110011".U 520 def sha512sum0 = "b110100".U 521 def sha512sum1 = "b110101".U 522 def sha512sig0 = "b110110".U 523 def sha512sig1 = "b110111".U 524 525 def sm3p0 = "b111000".U 526 def sm3p1 = "b111001".U 527 } 528 529 object BTBtype { 530 def B = "b00".U // branch 531 def J = "b01".U // jump 532 def I = "b10".U // indirect 533 def R = "b11".U // return 534 535 def apply() = UInt(2.W) 536 } 537 538 object SelImm { 539 def IMM_X = "b0111".U 540 def IMM_S = "b1110".U 541 def IMM_SB = "b0001".U 542 def IMM_U = "b0010".U 543 def IMM_UJ = "b0011".U 544 def IMM_I = "b0100".U 545 def IMM_Z = "b0101".U 546 def INVALID_INSTR = "b0110".U 547 def IMM_B6 = "b1000".U 548 549 def IMM_OPIVIS = "b1001".U 550 def IMM_OPIVIU = "b1010".U 551 def IMM_VSETVLI = "b1100".U 552 def IMM_VSETIVLI = "b1101".U 553 554 def X = BitPat("b0000") 555 556 def apply() = UInt(4.W) 557 } 558 559 object UopDivType { 560 def SCA_SIM = "b00000".U 561 def DIR = "b00001".U 562 def VEC_LMUL = "b00010".U 563 def VEC_MV_LMUL = "b00011".U 564 def VEC_MV = "b00100".U 565 def VEC_WIDE = "b00101".U 566 def VEC_WIDE0 = "b00110".U 567 def VEC_MV_WIDE = "b00111".U 568 def VEC_MV_WIDE0 = "b01000".U 569 def VEC_NARROW = "b01001".U 570 def VEC_MV_NARROW = "b01010".U 571 def VEC_EXT2 = "b01011".U 572 def VEC_EXT4 = "b01100".U 573 def VEC_EXT8 = "b01101".U 574 def dummy = "b11111".U 575 576 def X = BitPat("b00000") 577 578 def apply() = UInt(5.W) 579 } 580 581 object ExceptionNO { 582 def instrAddrMisaligned = 0 583 def instrAccessFault = 1 584 def illegalInstr = 2 585 def breakPoint = 3 586 def loadAddrMisaligned = 4 587 def loadAccessFault = 5 588 def storeAddrMisaligned = 6 589 def storeAccessFault = 7 590 def ecallU = 8 591 def ecallS = 9 592 def ecallM = 11 593 def instrPageFault = 12 594 def loadPageFault = 13 595 // def singleStep = 14 596 def storePageFault = 15 597 def priorities = Seq( 598 breakPoint, // TODO: different BP has different priority 599 instrPageFault, 600 instrAccessFault, 601 illegalInstr, 602 instrAddrMisaligned, 603 ecallM, ecallS, ecallU, 604 storeAddrMisaligned, 605 loadAddrMisaligned, 606 storePageFault, 607 loadPageFault, 608 storeAccessFault, 609 loadAccessFault 610 ) 611 def all = priorities.distinct.sorted 612 def frontendSet = Seq( 613 instrAddrMisaligned, 614 instrAccessFault, 615 illegalInstr, 616 instrPageFault 617 ) 618 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 619 val new_vec = Wire(ExceptionVec()) 620 new_vec.foreach(_ := false.B) 621 select.foreach(i => new_vec(i) := vec(i)) 622 new_vec 623 } 624 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 625 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 626 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 627 partialSelect(vec, fuConfig.exceptionOut) 628 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 629 partialSelect(vec, exuConfig.exceptionOut) 630 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 631 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 632 } 633 634 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 635 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 636 def aluGen(p: Parameters) = new Alu()(p) 637 def bkuGen(p: Parameters) = new Bku()(p) 638 def jmpGen(p: Parameters) = new Jump()(p) 639 def fenceGen(p: Parameters) = new Fence()(p) 640 def csrGen(p: Parameters) = new CSR()(p) 641 def i2fGen(p: Parameters) = new IntToFP()(p) 642 def fmacGen(p: Parameters) = new FMA()(p) 643 def f2iGen(p: Parameters) = new FPToInt()(p) 644 def f2fGen(p: Parameters) = new FPToFP()(p) 645 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 646 def stdGen(p: Parameters) = new Std()(p) 647 def mouDataGen(p: Parameters) = new Std()(p) 648 def vipuGen(p: Parameters) = new VIPU()(p) 649 def vppuGen(p: Parameters) = new VPPU()(p) 650 def vfpuGen(p: Parameters) = new VFPU()(p) 651 652 def f2iSel(uop: MicroOp): Bool = { 653 uop.ctrl.rfWen 654 } 655 656 def i2fSel(uop: MicroOp): Bool = { 657 uop.ctrl.fpu.fromInt 658 } 659 660 def f2fSel(uop: MicroOp): Bool = { 661 val ctrl = uop.ctrl.fpu 662 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 663 } 664 665 def fdivSqrtSel(uop: MicroOp): Bool = { 666 val ctrl = uop.ctrl.fpu 667 ctrl.div || ctrl.sqrt 668 } 669 670 val aluCfg = FuConfig( 671 name = "alu", 672 fuGen = aluGen, 673 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 674 fuType = FuType.alu, 675 numIntSrc = 2, 676 numFpSrc = 0, 677 writeIntRf = true, 678 writeFpRf = false, 679 hasRedirect = true, 680 ) 681 682 val jmpCfg = FuConfig( 683 name = "jmp", 684 fuGen = jmpGen, 685 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 686 fuType = FuType.jmp, 687 numIntSrc = 1, 688 numFpSrc = 0, 689 writeIntRf = true, 690 writeFpRf = false, 691 hasRedirect = true, 692 ) 693 694 val fenceCfg = FuConfig( 695 name = "fence", 696 fuGen = fenceGen, 697 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 698 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 699 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 700 flushPipe = true 701 ) 702 703 val csrCfg = FuConfig( 704 name = "csr", 705 fuGen = csrGen, 706 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 707 fuType = FuType.csr, 708 numIntSrc = 1, 709 numFpSrc = 0, 710 writeIntRf = true, 711 writeFpRf = false, 712 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 713 flushPipe = true 714 ) 715 716 val i2fCfg = FuConfig( 717 name = "i2f", 718 fuGen = i2fGen, 719 fuSel = i2fSel, 720 FuType.i2f, 721 numIntSrc = 1, 722 numFpSrc = 0, 723 writeIntRf = false, 724 writeFpRf = true, 725 writeFflags = true, 726 latency = CertainLatency(2), 727 fastUopOut = true, fastImplemented = true 728 ) 729 730 val divCfg = FuConfig( 731 name = "div", 732 fuGen = dividerGen, 733 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 734 FuType.div, 735 2, 736 0, 737 writeIntRf = true, 738 writeFpRf = false, 739 latency = UncertainLatency(), 740 fastUopOut = true, 741 fastImplemented = true, 742 hasInputBuffer = (true, 4, true) 743 ) 744 745 val mulCfg = FuConfig( 746 name = "mul", 747 fuGen = multiplierGen, 748 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 749 FuType.mul, 750 2, 751 0, 752 writeIntRf = true, 753 writeFpRf = false, 754 latency = CertainLatency(2), 755 fastUopOut = true, 756 fastImplemented = true 757 ) 758 759 val bkuCfg = FuConfig( 760 name = "bku", 761 fuGen = bkuGen, 762 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 763 fuType = FuType.bku, 764 numIntSrc = 2, 765 numFpSrc = 0, 766 writeIntRf = true, 767 writeFpRf = false, 768 latency = CertainLatency(1), 769 fastUopOut = true, 770 fastImplemented = true 771 ) 772 773 val fmacCfg = FuConfig( 774 name = "fmac", 775 fuGen = fmacGen, 776 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fmac, 777 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 778 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 779 ) 780 781 val f2iCfg = FuConfig( 782 name = "f2i", 783 fuGen = f2iGen, 784 fuSel = f2iSel, 785 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 786 fastUopOut = true, fastImplemented = true 787 ) 788 789 val f2fCfg = FuConfig( 790 name = "f2f", 791 fuGen = f2fGen, 792 fuSel = f2fSel, 793 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 794 fastUopOut = true, fastImplemented = true 795 ) 796 797 val fdivSqrtCfg = FuConfig( 798 name = "fdivSqrt", 799 fuGen = fdivSqrtGen, 800 fuSel = fdivSqrtSel, 801 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 802 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 803 ) 804 805 val lduCfg = FuConfig( 806 "ldu", 807 null, // DontCare 808 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 809 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 810 latency = UncertainLatency(), 811 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 812 flushPipe = true, 813 replayInst = true, 814 hasLoadError = true 815 ) 816 817 val staCfg = FuConfig( 818 "sta", 819 null, 820 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 821 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 822 latency = UncertainLatency(), 823 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 824 ) 825 826 val stdCfg = FuConfig( 827 "std", 828 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 829 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 830 ) 831 832 val mouCfg = FuConfig( 833 "mou", 834 null, 835 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 836 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 837 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 838 ) 839 840 val mouDataCfg = FuConfig( 841 "mou", 842 mouDataGen, 843 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 844 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 845 latency = UncertainLatency() 846 ) 847 848 val vipuCfg = FuConfig( 849 name = "vipu", 850 fuGen = vipuGen, 851 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 852 fuType = FuType.vipu, 853 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, writeVxsat = true, 854 numVecSrc = 4, writeVecRf = true, 855 fastUopOut = false, // TODO: check 856 fastImplemented = true, //TODO: check 857 ) 858 859 val vppuCfg = FuConfig( 860 name = "vppu", 861 fuGen = vppuGen, 862 fuSel = (uop: MicroOp) => FuType.vppu === uop.ctrl.fuType, 863 fuType = FuType.vppu, 864 numIntSrc = 0, numFpSrc = 1, writeIntRf = false, writeFpRf = false, writeFflags = false, 865 numVecSrc = 1, writeVecRf = true, 866 fastUopOut = false, // TODO: check 867 fastImplemented = true, //TODO: check 868 ) 869 870 val vfpuCfg = FuConfig( 871 name = "vfpu", 872 fuGen = vfpuGen, 873 fuSel = (uop: MicroOp) => FuType.vfpu === uop.ctrl.fuType, 874 fuType = FuType.vfpu, 875 numIntSrc = 0, numFpSrc = 1, writeIntRf = false, writeFpRf = false, writeFflags = true, 876 numVecSrc = 3, writeVecRf = true, 877 fastUopOut = false, // TODO: check 878 fastImplemented = true, //TODO: check 879 // latency = CertainLatency(2) 880 ) 881 882 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 883 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 884 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 885 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 886 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg, vppuCfg, vfpuCfg), Int.MaxValue, 0) 887 val FmiscExeUnitCfg = ExuConfig( 888 "FmiscExeUnit", 889 "Fp", 890 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 891 Int.MaxValue, 1 892 ) 893 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 894 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 895 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 896 897 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 898 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 899 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 900 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 901 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 902 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 903 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 904 905 val aluRSMod = new RSMod( 906 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 907 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 908 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 909 ) 910 val fmaRSMod = new RSMod( 911 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 912 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 913 ) 914 val fmiscRSMod = new RSMod( 915 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 916 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 917 ) 918 val jumpRSMod = new RSMod( 919 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 920 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 921 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 922 ) 923 val loadRSMod = new RSMod( 924 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 925 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 926 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 927 ) 928 val mulRSMod = new RSMod( 929 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 930 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 931 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 932 ) 933 val staRSMod = new RSMod( 934 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 935 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 936 ) 937 val stdRSMod = new RSMod( 938 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 939 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 940 ) 941} 942