1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def apply() = UInt(3.W) 51 } 52 53 object SrcState { 54 def busy = "b0".U 55 def rdy = "b1".U 56 // def specRdy = "b10".U // speculative ready, for future use 57 def apply() = UInt(1.W) 58 59 def isReady(state: UInt): Bool = state === this.rdy 60 def isBusy(state: UInt): Bool = state === this.busy 61 } 62 63 // Todo: Use OH instead 64 object FuType { 65 def jmp = UIntToOH(0.U, num) 66 def brh = UIntToOH(1.U, num) 67 def i2f = UIntToOH(2.U, num) 68 def csr = UIntToOH(3.U, num) 69 def alu = UIntToOH(4.U, num) 70 def mul = UIntToOH(5.U, num) 71 def div = UIntToOH(6.U, num) 72 def fence = UIntToOH(7.U, num) 73 def bku = UIntToOH(8.U, num) 74 def vset = UIntToOH(9.U, num) 75 76 def fmac = UIntToOH(10.U, num) 77 def fmisc = UIntToOH(11.U, num) 78 def fDivSqrt = UIntToOH(12.U, num) 79 80 def ldu = UIntToOH(13.U, num) 81 def stu = UIntToOH(14.U, num) 82 def mou = UIntToOH(15.U, num) // for amo, lr, sc, fence 83 def vipu = UIntToOH(16.U, num) 84 def vfpu = UIntToOH(17.U, num) 85 def vldu = UIntToOH(18.U, num) 86 def vstu = UIntToOH(19.U, num) 87 def X = BitPat.dontCare(num) 88 89 def num = 20 90 91 def apply() = UInt(log2Up(num).W) 92 93 def isIntExu(fuType: UInt) = !fuType(3) 94 def isJumpExu(fuType: UInt) = fuType === jmp 95 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 96 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 97 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 98 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 99 def isAMO(fuType: UInt) = fuType(1) 100 def isFence(fuType: UInt) = fuType === fence 101 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 102 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 103 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 104 def isVpu(fuType: UInt) = fuType(4) 105 106 def jmpCanAccept(fuType: UInt) = !fuType(2) 107 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 108 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 109 110 def fmacCanAccept(fuType: UInt) = !fuType(1) 111 def fmiscCanAccept(fuType: UInt) = fuType(1) 112 113 def loadCanAccept(fuType: UInt) = !fuType(0) 114 def storeCanAccept(fuType: UInt) = fuType(0) 115 116 def storeIsAMO(fuType: UInt) = fuType(1) 117 118 val functionNameMap = Map( 119 jmp.litValue() -> "jmp", 120 i2f.litValue() -> "int_to_float", 121 csr.litValue() -> "csr", 122 alu.litValue() -> "alu", 123 mul.litValue() -> "mul", 124 div.litValue() -> "div", 125 fence.litValue() -> "fence", 126 bku.litValue() -> "bku", 127 fmac.litValue() -> "fmac", 128 fmisc.litValue() -> "fmisc", 129 fDivSqrt.litValue() -> "fdiv_fsqrt", 130 ldu.litValue() -> "load", 131 stu.litValue() -> "store", 132 mou.litValue() -> "mou" 133 ) 134 } 135 136 def FuOpTypeWidth = 8 137 object FuOpType { 138 def apply() = UInt(FuOpTypeWidth.W) 139 def X = BitPat("b00000000") 140 } 141 142 // move VipuType and VfpuType into YunSuan/package.scala 143 // object VipuType { 144 // def dummy = 0.U(7.W) 145 // } 146 147 // object VfpuType { 148 // def dummy = 0.U(7.W) 149 // } 150 151 object VlduType { 152 def dummy = 0.U 153 } 154 155 object VstuType { 156 def dummy = 0.U 157 } 158 159 object CommitType { 160 def NORMAL = "b000".U // int/fp 161 def BRANCH = "b001".U // branch 162 def LOAD = "b010".U // load 163 def STORE = "b011".U // store 164 165 def apply() = UInt(3.W) 166 def isFused(commitType: UInt): Bool = commitType(2) 167 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 168 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 169 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 170 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 171 } 172 173 object RedirectLevel { 174 def flushAfter = "b0".U 175 def flush = "b1".U 176 177 def apply() = UInt(1.W) 178 // def isUnconditional(level: UInt) = level(1) 179 def flushItself(level: UInt) = level(0) 180 // def isException(level: UInt) = level(1) && level(0) 181 } 182 183 object ExceptionVec { 184 def apply() = Vec(16, Bool()) 185 } 186 187 object PMAMode { 188 def R = "b1".U << 0 //readable 189 def W = "b1".U << 1 //writeable 190 def X = "b1".U << 2 //executable 191 def I = "b1".U << 3 //cacheable: icache 192 def D = "b1".U << 4 //cacheable: dcache 193 def S = "b1".U << 5 //enable speculative access 194 def A = "b1".U << 6 //enable atomic operation, A imply R & W 195 def C = "b1".U << 7 //if it is cacheable is configable 196 def Reserved = "b0".U 197 198 def apply() = UInt(7.W) 199 200 def read(mode: UInt) = mode(0) 201 def write(mode: UInt) = mode(1) 202 def execute(mode: UInt) = mode(2) 203 def icache(mode: UInt) = mode(3) 204 def dcache(mode: UInt) = mode(4) 205 def speculate(mode: UInt) = mode(5) 206 def atomic(mode: UInt) = mode(6) 207 def configable_cache(mode: UInt) = mode(7) 208 209 def strToMode(s: String) = { 210 var result = 0.U(8.W) 211 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 212 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 213 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 214 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 215 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 216 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 217 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 218 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 219 result 220 } 221 } 222 223 224 object CSROpType { 225 def jmp = "b000".U 226 def wrt = "b001".U 227 def set = "b010".U 228 def clr = "b011".U 229 def wfi = "b100".U 230 def wrti = "b101".U 231 def seti = "b110".U 232 def clri = "b111".U 233 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 234 } 235 236 // jump 237 object JumpOpType { 238 def jal = "b00".U 239 def jalr = "b01".U 240 def auipc = "b10".U 241// def call = "b11_011".U 242// def ret = "b11_100".U 243 def jumpOpisJalr(op: UInt) = op(0) 244 def jumpOpisAuipc(op: UInt) = op(1) 245 } 246 247 object FenceOpType { 248 def fence = "b10000".U 249 def sfence = "b10001".U 250 def fencei = "b10010".U 251 def nofence= "b00000".U 252 } 253 254 object ALUOpType { 255 // shift optype 256 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 257 def sll = "b000_0001".U // sll: src1 << src2 258 259 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 260 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 261 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 262 263 def srl = "b000_0101".U // srl: src1 >> src2 264 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 265 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 266 267 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 268 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 269 270 // RV64 32bit optype 271 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 272 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 273 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 274 275 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 276 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 277 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 278 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 279 280 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 281 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 282 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 283 def rolw = "b001_1100".U 284 def rorw = "b001_1101".U 285 286 // ADD-op 287 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 288 def add = "b010_0001".U // add: src1 + src2 289 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 290 291 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 292 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 293 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 294 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 295 296 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 297 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 298 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 299 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 300 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 301 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 302 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 303 304 // SUB-op: src1 - src2 305 def sub = "b011_0000".U 306 def sltu = "b011_0001".U 307 def slt = "b011_0010".U 308 def maxu = "b011_0100".U 309 def minu = "b011_0101".U 310 def max = "b011_0110".U 311 def min = "b011_0111".U 312 313 // branch 314 def beq = "b111_0000".U 315 def bne = "b111_0010".U 316 def blt = "b111_1000".U 317 def bge = "b111_1010".U 318 def bltu = "b111_1100".U 319 def bgeu = "b111_1110".U 320 321 // misc optype 322 def and = "b100_0000".U 323 def andn = "b100_0001".U 324 def or = "b100_0010".U 325 def orn = "b100_0011".U 326 def xor = "b100_0100".U 327 def xnor = "b100_0101".U 328 def orcb = "b100_0110".U 329 330 def sextb = "b100_1000".U 331 def packh = "b100_1001".U 332 def sexth = "b100_1010".U 333 def packw = "b100_1011".U 334 335 def revb = "b101_0000".U 336 def rev8 = "b101_0001".U 337 def pack = "b101_0010".U 338 def orh48 = "b101_0011".U 339 340 def szewl1 = "b101_1000".U 341 def szewl2 = "b101_1001".U 342 def szewl3 = "b101_1010".U 343 def byte2 = "b101_1011".U 344 345 def andlsb = "b110_0000".U 346 def andzexth = "b110_0001".U 347 def orlsb = "b110_0010".U 348 def orzexth = "b110_0011".U 349 def xorlsb = "b110_0100".U 350 def xorzexth = "b110_0101".U 351 def orcblsb = "b110_0110".U 352 def orcbzexth = "b110_0111".U 353 def vsetvli1 = "b1000_0000".U 354 def vsetvli2 = "b1000_0100".U 355 def vsetvl1 = "b1000_0001".U 356 def vsetvl2 = "b1000_0101".U 357 def vsetivli1 = "b1000_0010".U 358 def vsetivli2 = "b1000_0110".U 359 360 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 361 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 362 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 363 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 364 def isBranch(func: UInt) = func(6, 4) === "b111".U 365 def getBranchType(func: UInt) = func(3, 2) 366 def isBranchInvert(func: UInt) = func(1) 367 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 368 def isVsetvl(func: UInt) = isVset(func) && func(0) 369 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 370 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 371 372 def apply() = UInt(FuOpTypeWidth.W) 373 } 374 375 object MDUOpType { 376 // mul 377 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 378 def mul = "b00000".U 379 def mulh = "b00001".U 380 def mulhsu = "b00010".U 381 def mulhu = "b00011".U 382 def mulw = "b00100".U 383 384 def mulw7 = "b01100".U 385 386 // div 387 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 388 def div = "b10000".U 389 def divu = "b10010".U 390 def rem = "b10001".U 391 def remu = "b10011".U 392 393 def divw = "b10100".U 394 def divuw = "b10110".U 395 def remw = "b10101".U 396 def remuw = "b10111".U 397 398 def isMul(op: UInt) = !op(4) 399 def isDiv(op: UInt) = op(4) 400 401 def isDivSign(op: UInt) = isDiv(op) && !op(1) 402 def isW(op: UInt) = op(2) 403 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 404 def getMulOp(op: UInt) = op(1, 0) 405 } 406 407 object LSUOpType { 408 // load pipeline 409 410 // normal load 411 // Note: bit(1, 0) are size, DO NOT CHANGE 412 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 413 def lb = "b0000".U 414 def lh = "b0001".U 415 def lw = "b0010".U 416 def ld = "b0011".U 417 def lbu = "b0100".U 418 def lhu = "b0101".U 419 def lwu = "b0110".U 420 421 // Zicbop software prefetch 422 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 423 def prefetch_i = "b1000".U // TODO 424 def prefetch_r = "b1001".U 425 def prefetch_w = "b1010".U 426 427 def isPrefetch(op: UInt): Bool = op(3) 428 429 // store pipeline 430 // normal store 431 // bit encoding: | store 00 | size(2bit) | 432 def sb = "b0000".U 433 def sh = "b0001".U 434 def sw = "b0010".U 435 def sd = "b0011".U 436 437 // l1 cache op 438 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 439 def cbo_zero = "b0111".U 440 441 // llc op 442 // bit encoding: | prefetch 11 | suboptype(2bit) | 443 def cbo_clean = "b1100".U 444 def cbo_flush = "b1101".U 445 def cbo_inval = "b1110".U 446 447 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 448 449 // atomics 450 // bit(1, 0) are size 451 // since atomics use a different fu type 452 // so we can safely reuse other load/store's encodings 453 // bit encoding: | optype(4bit) | size (2bit) | 454 def lr_w = "b000010".U 455 def sc_w = "b000110".U 456 def amoswap_w = "b001010".U 457 def amoadd_w = "b001110".U 458 def amoxor_w = "b010010".U 459 def amoand_w = "b010110".U 460 def amoor_w = "b011010".U 461 def amomin_w = "b011110".U 462 def amomax_w = "b100010".U 463 def amominu_w = "b100110".U 464 def amomaxu_w = "b101010".U 465 466 def lr_d = "b000011".U 467 def sc_d = "b000111".U 468 def amoswap_d = "b001011".U 469 def amoadd_d = "b001111".U 470 def amoxor_d = "b010011".U 471 def amoand_d = "b010111".U 472 def amoor_d = "b011011".U 473 def amomin_d = "b011111".U 474 def amomax_d = "b100011".U 475 def amominu_d = "b100111".U 476 def amomaxu_d = "b101011".U 477 478 def size(op: UInt) = op(1,0) 479 } 480 481 object BKUOpType { 482 483 def clmul = "b000000".U 484 def clmulh = "b000001".U 485 def clmulr = "b000010".U 486 def xpermn = "b000100".U 487 def xpermb = "b000101".U 488 489 def clz = "b001000".U 490 def clzw = "b001001".U 491 def ctz = "b001010".U 492 def ctzw = "b001011".U 493 def cpop = "b001100".U 494 def cpopw = "b001101".U 495 496 // 01xxxx is reserve 497 def aes64es = "b100000".U 498 def aes64esm = "b100001".U 499 def aes64ds = "b100010".U 500 def aes64dsm = "b100011".U 501 def aes64im = "b100100".U 502 def aes64ks1i = "b100101".U 503 def aes64ks2 = "b100110".U 504 505 // merge to two instruction sm4ks & sm4ed 506 def sm4ed0 = "b101000".U 507 def sm4ed1 = "b101001".U 508 def sm4ed2 = "b101010".U 509 def sm4ed3 = "b101011".U 510 def sm4ks0 = "b101100".U 511 def sm4ks1 = "b101101".U 512 def sm4ks2 = "b101110".U 513 def sm4ks3 = "b101111".U 514 515 def sha256sum0 = "b110000".U 516 def sha256sum1 = "b110001".U 517 def sha256sig0 = "b110010".U 518 def sha256sig1 = "b110011".U 519 def sha512sum0 = "b110100".U 520 def sha512sum1 = "b110101".U 521 def sha512sig0 = "b110110".U 522 def sha512sig1 = "b110111".U 523 524 def sm3p0 = "b111000".U 525 def sm3p1 = "b111001".U 526 } 527 528 object BTBtype { 529 def B = "b00".U // branch 530 def J = "b01".U // jump 531 def I = "b10".U // indirect 532 def R = "b11".U // return 533 534 def apply() = UInt(2.W) 535 } 536 537 object SelImm { 538 def IMM_X = "b0111".U 539 def IMM_S = "b0000".U 540 def IMM_SB = "b0001".U 541 def IMM_U = "b0010".U 542 def IMM_UJ = "b0011".U 543 def IMM_I = "b0100".U 544 def IMM_Z = "b0101".U 545 def INVALID_INSTR = "b0110".U 546 def IMM_B6 = "b1000".U 547 548 def IMM_OPIVIS = "b1001".U 549 def IMM_OPIVIU = "b1010".U 550 def IMM_VSETVLI = "b1100".U 551 def IMM_VSETIVLI = "b1101".U 552 553 def X = BitPat("b0000") 554 555 def apply() = UInt(4.W) 556 } 557 558 object ExceptionNO { 559 def instrAddrMisaligned = 0 560 def instrAccessFault = 1 561 def illegalInstr = 2 562 def breakPoint = 3 563 def loadAddrMisaligned = 4 564 def loadAccessFault = 5 565 def storeAddrMisaligned = 6 566 def storeAccessFault = 7 567 def ecallU = 8 568 def ecallS = 9 569 def ecallM = 11 570 def instrPageFault = 12 571 def loadPageFault = 13 572 // def singleStep = 14 573 def storePageFault = 15 574 def priorities = Seq( 575 breakPoint, // TODO: different BP has different priority 576 instrPageFault, 577 instrAccessFault, 578 illegalInstr, 579 instrAddrMisaligned, 580 ecallM, ecallS, ecallU, 581 storeAddrMisaligned, 582 loadAddrMisaligned, 583 storePageFault, 584 loadPageFault, 585 storeAccessFault, 586 loadAccessFault 587 ) 588 def all = priorities.distinct.sorted 589 def frontendSet = Seq( 590 instrAddrMisaligned, 591 instrAccessFault, 592 illegalInstr, 593 instrPageFault 594 ) 595 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 596 val new_vec = Wire(ExceptionVec()) 597 new_vec.foreach(_ := false.B) 598 select.foreach(i => new_vec(i) := vec(i)) 599 new_vec 600 } 601 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 602 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 603 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 604 partialSelect(vec, fuConfig.exceptionOut) 605 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 606 partialSelect(vec, exuConfig.exceptionOut) 607 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 608 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 609 } 610 611 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 612 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 613 def aluGen(p: Parameters) = new Alu()(p) 614 def bkuGen(p: Parameters) = new Bku()(p) 615 def jmpGen(p: Parameters) = new Jump()(p) 616 def fenceGen(p: Parameters) = new Fence()(p) 617 def csrGen(p: Parameters) = new CSR()(p) 618 def i2fGen(p: Parameters) = new IntToFP()(p) 619 def fmacGen(p: Parameters) = new FMA()(p) 620 def f2iGen(p: Parameters) = new FPToInt()(p) 621 def f2fGen(p: Parameters) = new FPToFP()(p) 622 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 623 def stdGen(p: Parameters) = new Std()(p) 624 def mouDataGen(p: Parameters) = new Std()(p) 625 def vipuGen(p: Parameters) = new VIPU()(p) 626 627 def f2iSel(uop: MicroOp): Bool = { 628 uop.ctrl.rfWen 629 } 630 631 def i2fSel(uop: MicroOp): Bool = { 632 uop.ctrl.fpu.fromInt 633 } 634 635 def f2fSel(uop: MicroOp): Bool = { 636 val ctrl = uop.ctrl.fpu 637 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 638 } 639 640 def fdivSqrtSel(uop: MicroOp): Bool = { 641 val ctrl = uop.ctrl.fpu 642 ctrl.div || ctrl.sqrt 643 } 644 645 val aluCfg = FuConfig( 646 name = "alu", 647 fuGen = aluGen, 648 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 649 fuType = FuType.alu, 650 numIntSrc = 2, 651 numFpSrc = 0, 652 writeIntRf = true, 653 writeFpRf = false, 654 hasRedirect = true, 655 ) 656 657 val jmpCfg = FuConfig( 658 name = "jmp", 659 fuGen = jmpGen, 660 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 661 fuType = FuType.jmp, 662 numIntSrc = 1, 663 numFpSrc = 0, 664 writeIntRf = true, 665 writeFpRf = false, 666 hasRedirect = true, 667 ) 668 669 val fenceCfg = FuConfig( 670 name = "fence", 671 fuGen = fenceGen, 672 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 673 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 674 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 675 flushPipe = true 676 ) 677 678 val csrCfg = FuConfig( 679 name = "csr", 680 fuGen = csrGen, 681 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 682 fuType = FuType.csr, 683 numIntSrc = 1, 684 numFpSrc = 0, 685 writeIntRf = true, 686 writeFpRf = false, 687 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 688 flushPipe = true 689 ) 690 691 val i2fCfg = FuConfig( 692 name = "i2f", 693 fuGen = i2fGen, 694 fuSel = i2fSel, 695 FuType.i2f, 696 numIntSrc = 1, 697 numFpSrc = 0, 698 writeIntRf = false, 699 writeFpRf = true, 700 writeFflags = true, 701 latency = CertainLatency(2), 702 fastUopOut = true, fastImplemented = true 703 ) 704 705 val divCfg = FuConfig( 706 name = "div", 707 fuGen = dividerGen, 708 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 709 FuType.div, 710 2, 711 0, 712 writeIntRf = true, 713 writeFpRf = false, 714 latency = UncertainLatency(), 715 fastUopOut = true, 716 fastImplemented = true, 717 hasInputBuffer = (true, 4, true) 718 ) 719 720 val mulCfg = FuConfig( 721 name = "mul", 722 fuGen = multiplierGen, 723 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 724 FuType.mul, 725 2, 726 0, 727 writeIntRf = true, 728 writeFpRf = false, 729 latency = CertainLatency(2), 730 fastUopOut = true, 731 fastImplemented = true 732 ) 733 734 val bkuCfg = FuConfig( 735 name = "bku", 736 fuGen = bkuGen, 737 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 738 fuType = FuType.bku, 739 numIntSrc = 2, 740 numFpSrc = 0, 741 writeIntRf = true, 742 writeFpRf = false, 743 latency = CertainLatency(1), 744 fastUopOut = true, 745 fastImplemented = true 746 ) 747 748 val fmacCfg = FuConfig( 749 name = "fmac", 750 fuGen = fmacGen, 751 fuSel = _ => true.B, 752 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 753 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 754 ) 755 756 val f2iCfg = FuConfig( 757 name = "f2i", 758 fuGen = f2iGen, 759 fuSel = f2iSel, 760 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 761 fastUopOut = true, fastImplemented = true 762 ) 763 764 val f2fCfg = FuConfig( 765 name = "f2f", 766 fuGen = f2fGen, 767 fuSel = f2fSel, 768 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 769 fastUopOut = true, fastImplemented = true 770 ) 771 772 val fdivSqrtCfg = FuConfig( 773 name = "fdivSqrt", 774 fuGen = fdivSqrtGen, 775 fuSel = fdivSqrtSel, 776 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 777 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 778 ) 779 780 val lduCfg = FuConfig( 781 "ldu", 782 null, // DontCare 783 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 784 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 785 latency = UncertainLatency(), 786 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 787 flushPipe = true, 788 replayInst = true, 789 hasLoadError = true 790 ) 791 792 val staCfg = FuConfig( 793 "sta", 794 null, 795 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 796 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 797 latency = UncertainLatency(), 798 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 799 ) 800 801 val stdCfg = FuConfig( 802 "std", 803 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 804 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 805 ) 806 807 val mouCfg = FuConfig( 808 "mou", 809 null, 810 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 811 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 812 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 813 ) 814 815 val mouDataCfg = FuConfig( 816 "mou", 817 mouDataGen, 818 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 819 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 820 latency = UncertainLatency() 821 ) 822 823 val vipuCfg = FuConfig( 824 name = "vipu", 825 fuGen = vipuGen, 826 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 827 fuType = FuType.vipu, 828 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 829 numVecSrc = 2, writeVecRf = true, 830 fastUopOut = true, // TODO: check 831 fastImplemented = true, //TODO: check 832 ) 833 834 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 835 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 836 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 837 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 838 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 839 val FmiscExeUnitCfg = ExuConfig( 840 "FmiscExeUnit", 841 "Fp", 842 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 843 Int.MaxValue, 1 844 ) 845 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 846 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 847 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 848 849 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 850 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 851 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 852 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 853 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 854 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 855 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 856 857 val aluRSMod = new RSMod( 858 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 859 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 860 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 861 ) 862 val fmaRSMod = new RSMod( 863 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 864 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 865 ) 866 val fmiscRSMod = new RSMod( 867 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 868 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 869 ) 870 val jumpRSMod = new RSMod( 871 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 872 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 873 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 874 ) 875 val loadRSMod = new RSMod( 876 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 877 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 878 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 879 ) 880 val mulRSMod = new RSMod( 881 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 882 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 883 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 884 ) 885 val staRSMod = new RSMod( 886 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 887 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 888 ) 889 val stdRSMod = new RSMod( 890 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 891 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 892 ) 893} 894