1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def apply() = UInt(3.W) 51 } 52 53 object SrcState { 54 def busy = "b0".U 55 def rdy = "b1".U 56 // def specRdy = "b10".U // speculative ready, for future use 57 def apply() = UInt(1.W) 58 59 def isReady(state: UInt): Bool = state === this.rdy 60 def isBusy(state: UInt): Bool = state === this.busy 61 } 62 63 // Todo: Use OH instead 64 object FuType { 65 def jmp = "b00000".U 66 def i2f = "b00001".U 67 def csr = "b00010".U 68 def alu = "b00110".U 69 def mul = "b00100".U 70 def div = "b00101".U 71 def fence = "b00011".U 72 def bku = "b00111".U 73 74 def fmac = "b01000".U 75 def fmisc = "b01011".U 76 def fDivSqrt = "b01010".U 77 78 def ldu = "b01100".U 79 def stu = "b01101".U 80 def mou = "b01111".U // for amo, lr, sc, fence 81 def vipu = "b10000".U 82 def vfpu = "b11000".U 83 def vldu = "b11100".U 84 def vstu = "b11101".U 85 def X = BitPat("b00000") 86 87 def num = 18 88 89 def apply() = UInt(log2Up(num).W) 90 91 def isIntExu(fuType: UInt) = !fuType(3) 92 def isJumpExu(fuType: UInt) = fuType === jmp 93 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 94 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 95 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 96 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 97 def isAMO(fuType: UInt) = fuType(1) 98 def isFence(fuType: UInt) = fuType === fence 99 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 100 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 101 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 102 def isVpu(fuType: UInt) = fuType(4) 103 104 def jmpCanAccept(fuType: UInt) = !fuType(2) 105 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 106 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 107 108 def fmacCanAccept(fuType: UInt) = !fuType(1) 109 def fmiscCanAccept(fuType: UInt) = fuType(1) 110 111 def loadCanAccept(fuType: UInt) = !fuType(0) 112 def storeCanAccept(fuType: UInt) = fuType(0) 113 114 def storeIsAMO(fuType: UInt) = fuType(1) 115 116 val functionNameMap = Map( 117 jmp.litValue() -> "jmp", 118 i2f.litValue() -> "int_to_float", 119 csr.litValue() -> "csr", 120 alu.litValue() -> "alu", 121 mul.litValue() -> "mul", 122 div.litValue() -> "div", 123 fence.litValue() -> "fence", 124 bku.litValue() -> "bku", 125 fmac.litValue() -> "fmac", 126 fmisc.litValue() -> "fmisc", 127 fDivSqrt.litValue() -> "fdiv_fsqrt", 128 ldu.litValue() -> "load", 129 stu.litValue() -> "store", 130 mou.litValue() -> "mou" 131 ) 132 } 133 134 def FuOpTypeWidth = 8 135 object FuOpType { 136 def apply() = UInt(FuOpTypeWidth.W) 137 def X = BitPat("b00000000") 138 } 139 140 // move VipuType and VfpuType into YunSuan/package.scala 141 // object VipuType { 142 // def dummy = 0.U(7.W) 143 // } 144 145 // object VfpuType { 146 // def dummy = 0.U(7.W) 147 // } 148 149 object VlduType { 150 def dummy = 0.U 151 } 152 153 object VstuType { 154 def dummy = 0.U 155 } 156 157 object CommitType { 158 def NORMAL = "b000".U // int/fp 159 def BRANCH = "b001".U // branch 160 def LOAD = "b010".U // load 161 def STORE = "b011".U // store 162 163 def apply() = UInt(3.W) 164 def isFused(commitType: UInt): Bool = commitType(2) 165 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 166 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 167 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 168 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 169 } 170 171 object RedirectLevel { 172 def flushAfter = "b0".U 173 def flush = "b1".U 174 175 def apply() = UInt(1.W) 176 // def isUnconditional(level: UInt) = level(1) 177 def flushItself(level: UInt) = level(0) 178 // def isException(level: UInt) = level(1) && level(0) 179 } 180 181 object ExceptionVec { 182 def apply() = Vec(16, Bool()) 183 } 184 185 object PMAMode { 186 def R = "b1".U << 0 //readable 187 def W = "b1".U << 1 //writeable 188 def X = "b1".U << 2 //executable 189 def I = "b1".U << 3 //cacheable: icache 190 def D = "b1".U << 4 //cacheable: dcache 191 def S = "b1".U << 5 //enable speculative access 192 def A = "b1".U << 6 //enable atomic operation, A imply R & W 193 def C = "b1".U << 7 //if it is cacheable is configable 194 def Reserved = "b0".U 195 196 def apply() = UInt(7.W) 197 198 def read(mode: UInt) = mode(0) 199 def write(mode: UInt) = mode(1) 200 def execute(mode: UInt) = mode(2) 201 def icache(mode: UInt) = mode(3) 202 def dcache(mode: UInt) = mode(4) 203 def speculate(mode: UInt) = mode(5) 204 def atomic(mode: UInt) = mode(6) 205 def configable_cache(mode: UInt) = mode(7) 206 207 def strToMode(s: String) = { 208 var result = 0.U(8.W) 209 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 210 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 211 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 212 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 213 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 214 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 215 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 216 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 217 result 218 } 219 } 220 221 222 object CSROpType { 223 def jmp = "b000".U 224 def wrt = "b001".U 225 def set = "b010".U 226 def clr = "b011".U 227 def wfi = "b100".U 228 def wrti = "b101".U 229 def seti = "b110".U 230 def clri = "b111".U 231 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 232 } 233 234 // jump 235 object JumpOpType { 236 def jal = "b00".U 237 def jalr = "b01".U 238 def auipc = "b10".U 239// def call = "b11_011".U 240// def ret = "b11_100".U 241 def jumpOpisJalr(op: UInt) = op(0) 242 def jumpOpisAuipc(op: UInt) = op(1) 243 } 244 245 object FenceOpType { 246 def fence = "b10000".U 247 def sfence = "b10001".U 248 def fencei = "b10010".U 249 def nofence= "b00000".U 250 } 251 252 object ALUOpType { 253 // shift optype 254 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 255 def sll = "b000_0001".U // sll: src1 << src2 256 257 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 258 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 259 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 260 261 def srl = "b000_0101".U // srl: src1 >> src2 262 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 263 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 264 265 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 266 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 267 268 // RV64 32bit optype 269 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 270 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 271 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 272 273 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 274 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 275 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 276 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 277 278 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 279 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 280 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 281 def rolw = "b001_1100".U 282 def rorw = "b001_1101".U 283 284 // ADD-op 285 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 286 def add = "b010_0001".U // add: src1 + src2 287 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 288 289 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 290 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 291 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 292 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 293 294 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 295 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 296 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 297 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 298 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 299 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 300 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 301 302 // SUB-op: src1 - src2 303 def sub = "b011_0000".U 304 def sltu = "b011_0001".U 305 def slt = "b011_0010".U 306 def maxu = "b011_0100".U 307 def minu = "b011_0101".U 308 def max = "b011_0110".U 309 def min = "b011_0111".U 310 311 // branch 312 def beq = "b111_0000".U 313 def bne = "b111_0010".U 314 def blt = "b111_1000".U 315 def bge = "b111_1010".U 316 def bltu = "b111_1100".U 317 def bgeu = "b111_1110".U 318 319 // misc optype 320 def and = "b100_0000".U 321 def andn = "b100_0001".U 322 def or = "b100_0010".U 323 def orn = "b100_0011".U 324 def xor = "b100_0100".U 325 def xnor = "b100_0101".U 326 def orcb = "b100_0110".U 327 328 def sextb = "b100_1000".U 329 def packh = "b100_1001".U 330 def sexth = "b100_1010".U 331 def packw = "b100_1011".U 332 333 def revb = "b101_0000".U 334 def rev8 = "b101_0001".U 335 def pack = "b101_0010".U 336 def orh48 = "b101_0011".U 337 338 def szewl1 = "b101_1000".U 339 def szewl2 = "b101_1001".U 340 def szewl3 = "b101_1010".U 341 def byte2 = "b101_1011".U 342 343 def andlsb = "b110_0000".U 344 def andzexth = "b110_0001".U 345 def orlsb = "b110_0010".U 346 def orzexth = "b110_0011".U 347 def xorlsb = "b110_0100".U 348 def xorzexth = "b110_0101".U 349 def orcblsb = "b110_0110".U 350 def orcbzexth = "b110_0111".U 351 def vsetvli1 = "b1000_0000".U 352 def vsetvli2 = "b1000_0100".U 353 def vsetvl1 = "b1000_0001".U 354 def vsetvl2 = "b1000_0101".U 355 def vsetivli1 = "b1000_0010".U 356 def vsetivli2 = "b1000_0110".U 357 358 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 359 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 360 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 361 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 362 def isBranch(func: UInt) = func(6, 4) === "b111".U 363 def getBranchType(func: UInt) = func(3, 2) 364 def isBranchInvert(func: UInt) = func(1) 365 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 366 def isVsetvl(func: UInt) = isVset(func) && func(0) 367 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 368 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 369 370 def apply() = UInt(FuOpTypeWidth.W) 371 } 372 373 object MDUOpType { 374 // mul 375 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 376 def mul = "b00000".U 377 def mulh = "b00001".U 378 def mulhsu = "b00010".U 379 def mulhu = "b00011".U 380 def mulw = "b00100".U 381 382 def mulw7 = "b01100".U 383 384 // div 385 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 386 def div = "b10000".U 387 def divu = "b10010".U 388 def rem = "b10001".U 389 def remu = "b10011".U 390 391 def divw = "b10100".U 392 def divuw = "b10110".U 393 def remw = "b10101".U 394 def remuw = "b10111".U 395 396 def isMul(op: UInt) = !op(4) 397 def isDiv(op: UInt) = op(4) 398 399 def isDivSign(op: UInt) = isDiv(op) && !op(1) 400 def isW(op: UInt) = op(2) 401 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 402 def getMulOp(op: UInt) = op(1, 0) 403 } 404 405 object LSUOpType { 406 // load pipeline 407 408 // normal load 409 // Note: bit(1, 0) are size, DO NOT CHANGE 410 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 411 def lb = "b0000".U 412 def lh = "b0001".U 413 def lw = "b0010".U 414 def ld = "b0011".U 415 def lbu = "b0100".U 416 def lhu = "b0101".U 417 def lwu = "b0110".U 418 419 // Zicbop software prefetch 420 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 421 def prefetch_i = "b1000".U // TODO 422 def prefetch_r = "b1001".U 423 def prefetch_w = "b1010".U 424 425 def isPrefetch(op: UInt): Bool = op(3) 426 427 // store pipeline 428 // normal store 429 // bit encoding: | store 00 | size(2bit) | 430 def sb = "b0000".U 431 def sh = "b0001".U 432 def sw = "b0010".U 433 def sd = "b0011".U 434 435 // l1 cache op 436 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 437 def cbo_zero = "b0111".U 438 439 // llc op 440 // bit encoding: | prefetch 11 | suboptype(2bit) | 441 def cbo_clean = "b1100".U 442 def cbo_flush = "b1101".U 443 def cbo_inval = "b1110".U 444 445 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 446 447 // atomics 448 // bit(1, 0) are size 449 // since atomics use a different fu type 450 // so we can safely reuse other load/store's encodings 451 // bit encoding: | optype(4bit) | size (2bit) | 452 def lr_w = "b000010".U 453 def sc_w = "b000110".U 454 def amoswap_w = "b001010".U 455 def amoadd_w = "b001110".U 456 def amoxor_w = "b010010".U 457 def amoand_w = "b010110".U 458 def amoor_w = "b011010".U 459 def amomin_w = "b011110".U 460 def amomax_w = "b100010".U 461 def amominu_w = "b100110".U 462 def amomaxu_w = "b101010".U 463 464 def lr_d = "b000011".U 465 def sc_d = "b000111".U 466 def amoswap_d = "b001011".U 467 def amoadd_d = "b001111".U 468 def amoxor_d = "b010011".U 469 def amoand_d = "b010111".U 470 def amoor_d = "b011011".U 471 def amomin_d = "b011111".U 472 def amomax_d = "b100011".U 473 def amominu_d = "b100111".U 474 def amomaxu_d = "b101011".U 475 476 def size(op: UInt) = op(1,0) 477 } 478 479 object BKUOpType { 480 481 def clmul = "b000000".U 482 def clmulh = "b000001".U 483 def clmulr = "b000010".U 484 def xpermn = "b000100".U 485 def xpermb = "b000101".U 486 487 def clz = "b001000".U 488 def clzw = "b001001".U 489 def ctz = "b001010".U 490 def ctzw = "b001011".U 491 def cpop = "b001100".U 492 def cpopw = "b001101".U 493 494 // 01xxxx is reserve 495 def aes64es = "b100000".U 496 def aes64esm = "b100001".U 497 def aes64ds = "b100010".U 498 def aes64dsm = "b100011".U 499 def aes64im = "b100100".U 500 def aes64ks1i = "b100101".U 501 def aes64ks2 = "b100110".U 502 503 // merge to two instruction sm4ks & sm4ed 504 def sm4ed0 = "b101000".U 505 def sm4ed1 = "b101001".U 506 def sm4ed2 = "b101010".U 507 def sm4ed3 = "b101011".U 508 def sm4ks0 = "b101100".U 509 def sm4ks1 = "b101101".U 510 def sm4ks2 = "b101110".U 511 def sm4ks3 = "b101111".U 512 513 def sha256sum0 = "b110000".U 514 def sha256sum1 = "b110001".U 515 def sha256sig0 = "b110010".U 516 def sha256sig1 = "b110011".U 517 def sha512sum0 = "b110100".U 518 def sha512sum1 = "b110101".U 519 def sha512sig0 = "b110110".U 520 def sha512sig1 = "b110111".U 521 522 def sm3p0 = "b111000".U 523 def sm3p1 = "b111001".U 524 } 525 526 object BTBtype { 527 def B = "b00".U // branch 528 def J = "b01".U // jump 529 def I = "b10".U // indirect 530 def R = "b11".U // return 531 532 def apply() = UInt(2.W) 533 } 534 535 object SelImm { 536 def IMM_X = "b0111".U 537 def IMM_S = "b0000".U 538 def IMM_SB = "b0001".U 539 def IMM_U = "b0010".U 540 def IMM_UJ = "b0011".U 541 def IMM_I = "b0100".U 542 def IMM_Z = "b0101".U 543 def INVALID_INSTR = "b0110".U 544 def IMM_B6 = "b1000".U 545 546 def IMM_OPIVIS = "b1001".U 547 def IMM_OPIVIU = "b1010".U 548 def IMM_VSETVLI = "b1100".U 549 def IMM_VSETIVLI = "b1101".U 550 551 def X = BitPat("b0000") 552 553 def apply() = UInt(4.W) 554 } 555 556 object ExceptionNO { 557 def instrAddrMisaligned = 0 558 def instrAccessFault = 1 559 def illegalInstr = 2 560 def breakPoint = 3 561 def loadAddrMisaligned = 4 562 def loadAccessFault = 5 563 def storeAddrMisaligned = 6 564 def storeAccessFault = 7 565 def ecallU = 8 566 def ecallS = 9 567 def ecallM = 11 568 def instrPageFault = 12 569 def loadPageFault = 13 570 // def singleStep = 14 571 def storePageFault = 15 572 def priorities = Seq( 573 breakPoint, // TODO: different BP has different priority 574 instrPageFault, 575 instrAccessFault, 576 illegalInstr, 577 instrAddrMisaligned, 578 ecallM, ecallS, ecallU, 579 storeAddrMisaligned, 580 loadAddrMisaligned, 581 storePageFault, 582 loadPageFault, 583 storeAccessFault, 584 loadAccessFault 585 ) 586 def all = priorities.distinct.sorted 587 def frontendSet = Seq( 588 instrAddrMisaligned, 589 instrAccessFault, 590 illegalInstr, 591 instrPageFault 592 ) 593 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 594 val new_vec = Wire(ExceptionVec()) 595 new_vec.foreach(_ := false.B) 596 select.foreach(i => new_vec(i) := vec(i)) 597 new_vec 598 } 599 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 600 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 601 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 602 partialSelect(vec, fuConfig.exceptionOut) 603 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 604 partialSelect(vec, exuConfig.exceptionOut) 605 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 606 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 607 } 608 609 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 610 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 611 def aluGen(p: Parameters) = new Alu()(p) 612 def bkuGen(p: Parameters) = new Bku()(p) 613 def jmpGen(p: Parameters) = new Jump()(p) 614 def fenceGen(p: Parameters) = new Fence()(p) 615 def csrGen(p: Parameters) = new CSR()(p) 616 def i2fGen(p: Parameters) = new IntToFP()(p) 617 def fmacGen(p: Parameters) = new FMA()(p) 618 def f2iGen(p: Parameters) = new FPToInt()(p) 619 def f2fGen(p: Parameters) = new FPToFP()(p) 620 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 621 def stdGen(p: Parameters) = new Std()(p) 622 def mouDataGen(p: Parameters) = new Std()(p) 623 def vipuGen(p: Parameters) = new VIPU()(p) 624 625 def f2iSel(uop: MicroOp): Bool = { 626 uop.ctrl.rfWen 627 } 628 629 def i2fSel(uop: MicroOp): Bool = { 630 uop.ctrl.fpu.fromInt 631 } 632 633 def f2fSel(uop: MicroOp): Bool = { 634 val ctrl = uop.ctrl.fpu 635 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 636 } 637 638 def fdivSqrtSel(uop: MicroOp): Bool = { 639 val ctrl = uop.ctrl.fpu 640 ctrl.div || ctrl.sqrt 641 } 642 643 val aluCfg = FuConfig( 644 name = "alu", 645 fuGen = aluGen, 646 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 647 fuType = FuType.alu, 648 numIntSrc = 2, 649 numFpSrc = 0, 650 writeIntRf = true, 651 writeFpRf = false, 652 hasRedirect = true, 653 ) 654 655 val jmpCfg = FuConfig( 656 name = "jmp", 657 fuGen = jmpGen, 658 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 659 fuType = FuType.jmp, 660 numIntSrc = 1, 661 numFpSrc = 0, 662 writeIntRf = true, 663 writeFpRf = false, 664 hasRedirect = true, 665 ) 666 667 val fenceCfg = FuConfig( 668 name = "fence", 669 fuGen = fenceGen, 670 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 671 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 672 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 673 flushPipe = true 674 ) 675 676 val csrCfg = FuConfig( 677 name = "csr", 678 fuGen = csrGen, 679 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 680 fuType = FuType.csr, 681 numIntSrc = 1, 682 numFpSrc = 0, 683 writeIntRf = true, 684 writeFpRf = false, 685 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 686 flushPipe = true 687 ) 688 689 val i2fCfg = FuConfig( 690 name = "i2f", 691 fuGen = i2fGen, 692 fuSel = i2fSel, 693 FuType.i2f, 694 numIntSrc = 1, 695 numFpSrc = 0, 696 writeIntRf = false, 697 writeFpRf = true, 698 writeFflags = true, 699 latency = CertainLatency(2), 700 fastUopOut = true, fastImplemented = true 701 ) 702 703 val divCfg = FuConfig( 704 name = "div", 705 fuGen = dividerGen, 706 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 707 FuType.div, 708 2, 709 0, 710 writeIntRf = true, 711 writeFpRf = false, 712 latency = UncertainLatency(), 713 fastUopOut = true, 714 fastImplemented = true, 715 hasInputBuffer = (true, 4, true) 716 ) 717 718 val mulCfg = FuConfig( 719 name = "mul", 720 fuGen = multiplierGen, 721 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 722 FuType.mul, 723 2, 724 0, 725 writeIntRf = true, 726 writeFpRf = false, 727 latency = CertainLatency(2), 728 fastUopOut = true, 729 fastImplemented = true 730 ) 731 732 val bkuCfg = FuConfig( 733 name = "bku", 734 fuGen = bkuGen, 735 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 736 fuType = FuType.bku, 737 numIntSrc = 2, 738 numFpSrc = 0, 739 writeIntRf = true, 740 writeFpRf = false, 741 latency = CertainLatency(1), 742 fastUopOut = true, 743 fastImplemented = true 744 ) 745 746 val fmacCfg = FuConfig( 747 name = "fmac", 748 fuGen = fmacGen, 749 fuSel = _ => true.B, 750 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 751 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 752 ) 753 754 val f2iCfg = FuConfig( 755 name = "f2i", 756 fuGen = f2iGen, 757 fuSel = f2iSel, 758 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 759 fastUopOut = true, fastImplemented = true 760 ) 761 762 val f2fCfg = FuConfig( 763 name = "f2f", 764 fuGen = f2fGen, 765 fuSel = f2fSel, 766 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 767 fastUopOut = true, fastImplemented = true 768 ) 769 770 val fdivSqrtCfg = FuConfig( 771 name = "fdivSqrt", 772 fuGen = fdivSqrtGen, 773 fuSel = fdivSqrtSel, 774 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 775 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 776 ) 777 778 val lduCfg = FuConfig( 779 "ldu", 780 null, // DontCare 781 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 782 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 783 latency = UncertainLatency(), 784 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 785 flushPipe = true, 786 replayInst = true, 787 hasLoadError = true 788 ) 789 790 val staCfg = FuConfig( 791 "sta", 792 null, 793 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 794 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 795 latency = UncertainLatency(), 796 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 797 ) 798 799 val stdCfg = FuConfig( 800 "std", 801 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 802 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 803 ) 804 805 val mouCfg = FuConfig( 806 "mou", 807 null, 808 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 809 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 810 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 811 ) 812 813 val mouDataCfg = FuConfig( 814 "mou", 815 mouDataGen, 816 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 817 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 818 latency = UncertainLatency() 819 ) 820 821 val vipuCfg = FuConfig( 822 name = "vipu", 823 fuGen = vipuGen, 824 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 825 fuType = FuType.vipu, 826 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 827 numVecSrc = 2, writeVecRf = true, 828 fastUopOut = true, // TODO: check 829 fastImplemented = true, //TODO: check 830 ) 831 832 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 833 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 834 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 835 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 836 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 837 val FmiscExeUnitCfg = ExuConfig( 838 "FmiscExeUnit", 839 "Fp", 840 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 841 Int.MaxValue, 1 842 ) 843 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 844 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 845 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 846 847 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 848 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 849 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 850 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 851 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 852 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 853 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 854 855 val aluRSMod = new RSMod( 856 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 857 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 858 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 859 ) 860 val fmaRSMod = new RSMod( 861 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 862 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 863 ) 864 val fmiscRSMod = new RSMod( 865 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 866 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 867 ) 868 val jumpRSMod = new RSMod( 869 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 870 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 871 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 872 ) 873 val loadRSMod = new RSMod( 874 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 875 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 876 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 877 ) 878 val mulRSMod = new RSMod( 879 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 880 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 881 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 882 ) 883 val staRSMod = new RSMod( 884 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 885 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 886 ) 887 val stdRSMod = new RSMod( 888 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 889 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 890 ) 891} 892