1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27import xiangshan.backend.decode.{Imm, ImmUnion} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 def no = "b000".U // this src read no reg but cannot be Any value 37 38 // alias 39 def reg = this.xp 40 def DC = imm // Don't Care 41 def X = BitPat("b000") 42 43 def isPc(srcType: UInt) = srcType===pc 44 def isImm(srcType: UInt) = srcType===imm 45 def isReg(srcType: UInt) = srcType(0) 46 def isXp(srcType: UInt) = srcType(0) 47 def isFp(srcType: UInt) = srcType(1) 48 def isVp(srcType: UInt) = srcType(2) 49 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 50 def isNotReg(srcType: UInt): Bool = !srcType.orR 51 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 61 def isReady(state: UInt): Bool = state === this.rdy 62 def isBusy(state: UInt): Bool = state === this.busy 63 } 64 65 def FuOpTypeWidth = 9 66 object FuOpType { 67 def apply() = UInt(FuOpTypeWidth.W) 68 def X = BitPat("b00000000") 69 } 70 71 object VlduType { 72 // bit encoding: | padding (2bit) || mop (2bit) | lumop(5bit) | 73 // only unit-stride use lumop 74 // mop [1:0] 75 // 0 0 : unit-stride 76 // 0 1 : indexed-unordered 77 // 1 0 : strided 78 // 1 1 : indexed-ordered 79 // lumop[4:0] 80 // 0 0 0 0 0 : unit-stride load 81 // 0 1 0 0 0 : unit-stride, whole register load 82 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 83 // 1 0 0 0 0 : unit-stride fault-only-first 84 def vle = "b00_00_00000".U 85 def vlr = "b00_00_01000".U 86 def vlm = "b00_00_01011".U 87 def vleff = "b00_00_10000".U 88 def vluxe = "b00_01_00000".U 89 def vlse = "b00_10_00000".U 90 def vloxe = "b00_11_00000".U 91 92 def isStrided(fuOpType: UInt): Bool = fuOpType === vlse 93 def isIndexed(fuOpType: UInt): Bool = fuOpType === vluxe || fuOpType === vloxe 94 def isMasked(fuOpType: UInt): Bool = fuOpType === vlm 95 } 96 97 object VstuType { 98 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 99 // only unit-stride use sumop 100 // mop [1:0] 101 // 0 0 : unit-stride 102 // 0 1 : indexed-unordered 103 // 1 0 : strided 104 // 1 1 : indexed-ordered 105 // sumop[4:0] 106 // 0 0 0 0 0 : unit-stride load 107 // 0 1 0 0 0 : unit-stride, whole register load 108 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 109 def vse = "b00_00_00000".U 110 def vsr = "b00_00_01000".U 111 def vsm = "b00_00_01011".U 112 def vsuxe = "b00_01_00000".U 113 def vsse = "b00_10_00000".U 114 def vsoxe = "b00_11_00000".U 115 116 def isStrided(fuOpType: UInt): Bool = fuOpType === vsse 117 def isIndexed(fuOpType: UInt): Bool = fuOpType === vsuxe || fuOpType === vsoxe 118 } 119 120 object IF2VectorType { 121 // use last 2 bits for vsew 122 def iDup2Vec = "b1_00".U 123 def fDup2Vec = "b1_01".U 124 def immDup2Vec = "b1_10".U 125 def i2Vec = "b0_00".U 126 def f2Vec = "b0_01".U 127 def imm2Vec = "b0_10".U 128 def needDup(bits: UInt): Bool = bits(2) 129 def isImm(bits: UInt): Bool = bits(1) 130 } 131 132 object CommitType { 133 def NORMAL = "b000".U // int/fp 134 def BRANCH = "b001".U // branch 135 def LOAD = "b010".U // load 136 def STORE = "b011".U // store 137 138 def apply() = UInt(3.W) 139 def isFused(commitType: UInt): Bool = commitType(2) 140 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 141 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 142 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 143 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 144 } 145 146 object RedirectLevel { 147 def flushAfter = "b0".U 148 def flush = "b1".U 149 150 def apply() = UInt(1.W) 151 // def isUnconditional(level: UInt) = level(1) 152 def flushItself(level: UInt) = level(0) 153 // def isException(level: UInt) = level(1) && level(0) 154 } 155 156 object ExceptionVec { 157 val ExceptionVecSize = 16 158 def apply() = Vec(ExceptionVecSize, Bool()) 159 } 160 161 object PMAMode { 162 def R = "b1".U << 0 //readable 163 def W = "b1".U << 1 //writeable 164 def X = "b1".U << 2 //executable 165 def I = "b1".U << 3 //cacheable: icache 166 def D = "b1".U << 4 //cacheable: dcache 167 def S = "b1".U << 5 //enable speculative access 168 def A = "b1".U << 6 //enable atomic operation, A imply R & W 169 def C = "b1".U << 7 //if it is cacheable is configable 170 def Reserved = "b0".U 171 172 def apply() = UInt(7.W) 173 174 def read(mode: UInt) = mode(0) 175 def write(mode: UInt) = mode(1) 176 def execute(mode: UInt) = mode(2) 177 def icache(mode: UInt) = mode(3) 178 def dcache(mode: UInt) = mode(4) 179 def speculate(mode: UInt) = mode(5) 180 def atomic(mode: UInt) = mode(6) 181 def configable_cache(mode: UInt) = mode(7) 182 183 def strToMode(s: String) = { 184 var result = 0.U(8.W) 185 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 186 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 187 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 188 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 189 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 190 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 191 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 192 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 193 result 194 } 195 } 196 197 198 object CSROpType { 199 def jmp = "b000".U 200 def wrt = "b001".U 201 def set = "b010".U 202 def clr = "b011".U 203 def wfi = "b100".U 204 def wrti = "b101".U 205 def seti = "b110".U 206 def clri = "b111".U 207 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 208 } 209 210 // jump 211 object JumpOpType { 212 def jal = "b00".U 213 def jalr = "b01".U 214 def auipc = "b10".U 215// def call = "b11_011".U 216// def ret = "b11_100".U 217 def jumpOpisJalr(op: UInt) = op(0) 218 def jumpOpisAuipc(op: UInt) = op(1) 219 } 220 221 object FenceOpType { 222 def fence = "b10000".U 223 def sfence = "b10001".U 224 def fencei = "b10010".U 225 def nofence= "b00000".U 226 } 227 228 object ALUOpType { 229 // shift optype 230 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 231 def sll = "b000_0001".U // sll: src1 << src2 232 233 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 234 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 235 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 236 237 def srl = "b000_0101".U // srl: src1 >> src2 238 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 239 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 240 241 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 242 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 243 244 // RV64 32bit optype 245 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 246 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 247 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 248 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 249 250 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 251 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 252 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 253 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 254 255 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 256 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 257 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 258 def rolw = "b001_1100".U 259 def rorw = "b001_1101".U 260 261 // ADD-op 262 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 263 def add = "b010_0001".U // add: src1 + src2 264 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 265 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 266 267 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 268 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 269 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 270 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 271 272 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 273 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 274 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 275 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 276 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 277 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 278 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 279 280 // SUB-op: src1 - src2 281 def sub = "b011_0000".U 282 def sltu = "b011_0001".U 283 def slt = "b011_0010".U 284 def maxu = "b011_0100".U 285 def minu = "b011_0101".U 286 def max = "b011_0110".U 287 def min = "b011_0111".U 288 289 // branch 290 def beq = "b111_0000".U 291 def bne = "b111_0010".U 292 def blt = "b111_1000".U 293 def bge = "b111_1010".U 294 def bltu = "b111_1100".U 295 def bgeu = "b111_1110".U 296 297 // misc optype 298 def and = "b100_0000".U 299 def andn = "b100_0001".U 300 def or = "b100_0010".U 301 def orn = "b100_0011".U 302 def xor = "b100_0100".U 303 def xnor = "b100_0101".U 304 def orcb = "b100_0110".U 305 306 def sextb = "b100_1000".U 307 def packh = "b100_1001".U 308 def sexth = "b100_1010".U 309 def packw = "b100_1011".U 310 311 def revb = "b101_0000".U 312 def rev8 = "b101_0001".U 313 def pack = "b101_0010".U 314 def orh48 = "b101_0011".U 315 316 def szewl1 = "b101_1000".U 317 def szewl2 = "b101_1001".U 318 def szewl3 = "b101_1010".U 319 def byte2 = "b101_1011".U 320 321 def andlsb = "b110_0000".U 322 def andzexth = "b110_0001".U 323 def orlsb = "b110_0010".U 324 def orzexth = "b110_0011".U 325 def xorlsb = "b110_0100".U 326 def xorzexth = "b110_0101".U 327 def orcblsb = "b110_0110".U 328 def orcbzexth = "b110_0111".U 329 330 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 331 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 332 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 333 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 334 335 def apply() = UInt(FuOpTypeWidth.W) 336 } 337 338 object VSETOpType { 339 val setVlmaxBit = 0 340 val keepVlBit = 1 341 // destTypeBit == 0: write vl to rd 342 // destTypeBit == 1: write vconfig 343 val destTypeBit = 5 344 345 // vsetvli's uop 346 // rs1!=x0, normal 347 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 348 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 349 def uvsetvcfg_xi = "b1010_0000".U 350 def uvsetrd_xi = "b1000_0000".U 351 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 352 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 353 // uop1: w(rd) | vlmax, vtypei -> x[rd] 354 def uvsetvcfg_vlmax_i = "b1010_0001".U 355 def uvsetrd_vlmax_i = "b1000_0001".U 356 // rs1==x0, rd==x0, keep vl, set vtype 357 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 358 def uvsetvcfg_keep_v = "b1010_0010".U 359 360 // vsetvl's uop 361 // rs1!=x0, normal 362 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 363 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 364 def uvsetvcfg_xx = "b0110_0000".U 365 def uvsetrd_xx = "b0100_0000".U 366 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 367 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 368 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 369 def uvsetvcfg_vlmax_x = "b0110_0001".U 370 def uvsetrd_vlmax_x = "b0100_0001".U 371 // rs1==x0, rd==x0, keep vl, set vtype 372 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 373 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 374 def uvmv_v_x = "b0110_0010".U 375 def uvsetvcfg_vv = "b0111_0010".U 376 377 // vsetivli's uop 378 // uop0: w(vconfig) | vli, vtypei -> vconfig 379 // uop1: w(rd) | vli, vtypei -> x[rd] 380 def uvsetvcfg_ii = "b0010_0000".U 381 def uvsetrd_ii = "b0000_0000".U 382 383 def isVsetvl (func: UInt) = func(6) 384 def isVsetvli (func: UInt) = func(7) 385 def isVsetivli(func: UInt) = func(7, 6) === 0.U 386 def isNormal (func: UInt) = func(1, 0) === 0.U 387 def isSetVlmax(func: UInt) = func(setVlmaxBit) 388 def isKeepVl (func: UInt) = func(keepVlBit) 389 // RG: region 390 def writeIntRG(func: UInt) = !func(5) 391 def writeVecRG(func: UInt) = func(5) 392 def readIntRG (func: UInt) = !func(4) 393 def readVecRG (func: UInt) = func(4) 394 // modify fuOpType 395 def keepVl(func: UInt) = func | (1 << keepVlBit).U 396 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 397 } 398 399 object BRUOpType { 400 // branch 401 def beq = "b000_000".U 402 def bne = "b000_001".U 403 def blt = "b000_100".U 404 def bge = "b000_101".U 405 def bltu = "b001_000".U 406 def bgeu = "b001_001".U 407 408 def getBranchType(func: UInt) = func(3, 1) 409 def isBranchInvert(func: UInt) = func(0) 410 } 411 412 object MULOpType { 413 // mul 414 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 415 def mul = "b00000".U 416 def mulh = "b00001".U 417 def mulhsu = "b00010".U 418 def mulhu = "b00011".U 419 def mulw = "b00100".U 420 421 def mulw7 = "b01100".U 422 def isSign(op: UInt) = !op(1) 423 def isW(op: UInt) = op(2) 424 def isH(op: UInt) = op(1, 0) =/= 0.U 425 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 426 } 427 428 object DIVOpType { 429 // div 430 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 431 def div = "b10000".U 432 def divu = "b10010".U 433 def rem = "b10001".U 434 def remu = "b10011".U 435 436 def divw = "b10100".U 437 def divuw = "b10110".U 438 def remw = "b10101".U 439 def remuw = "b10111".U 440 441 def isSign(op: UInt) = !op(1) 442 def isW(op: UInt) = op(2) 443 def isH(op: UInt) = op(0) 444 } 445 446 object MDUOpType { 447 // mul 448 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 449 def mul = "b00000".U 450 def mulh = "b00001".U 451 def mulhsu = "b00010".U 452 def mulhu = "b00011".U 453 def mulw = "b00100".U 454 455 def mulw7 = "b01100".U 456 457 // div 458 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 459 def div = "b10000".U 460 def divu = "b10010".U 461 def rem = "b10001".U 462 def remu = "b10011".U 463 464 def divw = "b10100".U 465 def divuw = "b10110".U 466 def remw = "b10101".U 467 def remuw = "b10111".U 468 469 def isMul(op: UInt) = !op(4) 470 def isDiv(op: UInt) = op(4) 471 472 def isDivSign(op: UInt) = isDiv(op) && !op(1) 473 def isW(op: UInt) = op(2) 474 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 475 def getMulOp(op: UInt) = op(1, 0) 476 } 477 478 object LSUOpType { 479 // load pipeline 480 481 // normal load 482 // Note: bit(1, 0) are size, DO NOT CHANGE 483 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 484 def lb = "b0000".U 485 def lh = "b0001".U 486 def lw = "b0010".U 487 def ld = "b0011".U 488 def lbu = "b0100".U 489 def lhu = "b0101".U 490 def lwu = "b0110".U 491 492 // Zicbop software prefetch 493 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 494 def prefetch_i = "b1000".U // TODO 495 def prefetch_r = "b1001".U 496 def prefetch_w = "b1010".U 497 498 def isPrefetch(op: UInt): Bool = op(3) 499 500 // store pipeline 501 // normal store 502 // bit encoding: | store 00 | size(2bit) | 503 def sb = "b0000".U 504 def sh = "b0001".U 505 def sw = "b0010".U 506 def sd = "b0011".U 507 508 // l1 cache op 509 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 510 def cbo_zero = "b0111".U 511 512 // llc op 513 // bit encoding: | prefetch 11 | suboptype(2bit) | 514 def cbo_clean = "b1100".U 515 def cbo_flush = "b1101".U 516 def cbo_inval = "b1110".U 517 518 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 519 520 // atomics 521 // bit(1, 0) are size 522 // since atomics use a different fu type 523 // so we can safely reuse other load/store's encodings 524 // bit encoding: | optype(4bit) | size (2bit) | 525 def lr_w = "b000010".U 526 def sc_w = "b000110".U 527 def amoswap_w = "b001010".U 528 def amoadd_w = "b001110".U 529 def amoxor_w = "b010010".U 530 def amoand_w = "b010110".U 531 def amoor_w = "b011010".U 532 def amomin_w = "b011110".U 533 def amomax_w = "b100010".U 534 def amominu_w = "b100110".U 535 def amomaxu_w = "b101010".U 536 537 def lr_d = "b000011".U 538 def sc_d = "b000111".U 539 def amoswap_d = "b001011".U 540 def amoadd_d = "b001111".U 541 def amoxor_d = "b010011".U 542 def amoand_d = "b010111".U 543 def amoor_d = "b011011".U 544 def amomin_d = "b011111".U 545 def amomax_d = "b100011".U 546 def amominu_d = "b100111".U 547 def amomaxu_d = "b101011".U 548 549 def size(op: UInt) = op(1,0) 550 } 551 552 object BKUOpType { 553 554 def clmul = "b000000".U 555 def clmulh = "b000001".U 556 def clmulr = "b000010".U 557 def xpermn = "b000100".U 558 def xpermb = "b000101".U 559 560 def clz = "b001000".U 561 def clzw = "b001001".U 562 def ctz = "b001010".U 563 def ctzw = "b001011".U 564 def cpop = "b001100".U 565 def cpopw = "b001101".U 566 567 // 01xxxx is reserve 568 def aes64es = "b100000".U 569 def aes64esm = "b100001".U 570 def aes64ds = "b100010".U 571 def aes64dsm = "b100011".U 572 def aes64im = "b100100".U 573 def aes64ks1i = "b100101".U 574 def aes64ks2 = "b100110".U 575 576 // merge to two instruction sm4ks & sm4ed 577 def sm4ed0 = "b101000".U 578 def sm4ed1 = "b101001".U 579 def sm4ed2 = "b101010".U 580 def sm4ed3 = "b101011".U 581 def sm4ks0 = "b101100".U 582 def sm4ks1 = "b101101".U 583 def sm4ks2 = "b101110".U 584 def sm4ks3 = "b101111".U 585 586 def sha256sum0 = "b110000".U 587 def sha256sum1 = "b110001".U 588 def sha256sig0 = "b110010".U 589 def sha256sig1 = "b110011".U 590 def sha512sum0 = "b110100".U 591 def sha512sum1 = "b110101".U 592 def sha512sig0 = "b110110".U 593 def sha512sig1 = "b110111".U 594 595 def sm3p0 = "b111000".U 596 def sm3p1 = "b111001".U 597 } 598 599 object BTBtype { 600 def B = "b00".U // branch 601 def J = "b01".U // jump 602 def I = "b10".U // indirect 603 def R = "b11".U // return 604 605 def apply() = UInt(2.W) 606 } 607 608 object SelImm { 609 def IMM_X = "b0111".U 610 def IMM_S = "b1110".U 611 def IMM_SB = "b0001".U 612 def IMM_U = "b0010".U 613 def IMM_UJ = "b0011".U 614 def IMM_I = "b0100".U 615 def IMM_Z = "b0101".U 616 def INVALID_INSTR = "b0110".U 617 def IMM_B6 = "b1000".U 618 619 def IMM_OPIVIS = "b1001".U 620 def IMM_OPIVIU = "b1010".U 621 def IMM_VSETVLI = "b1100".U 622 def IMM_VSETIVLI = "b1101".U 623 def IMM_LUI32 = "b1011".U 624 def IMM_VRORVI = "b1111".U 625 626 def X = BitPat("b0000") 627 628 def apply() = UInt(4.W) 629 630 def mkString(immType: UInt) : String = { 631 val strMap = Map( 632 IMM_S.litValue -> "S", 633 IMM_SB.litValue -> "SB", 634 IMM_U.litValue -> "U", 635 IMM_UJ.litValue -> "UJ", 636 IMM_I.litValue -> "I", 637 IMM_Z.litValue -> "Z", 638 IMM_B6.litValue -> "B6", 639 IMM_OPIVIS.litValue -> "VIS", 640 IMM_OPIVIU.litValue -> "VIU", 641 IMM_VSETVLI.litValue -> "VSETVLI", 642 IMM_VSETIVLI.litValue -> "VSETIVLI", 643 IMM_LUI32.litValue -> "LUI32", 644 IMM_VRORVI.litValue -> "VRORVI", 645 INVALID_INSTR.litValue -> "INVALID", 646 ) 647 strMap(immType.litValue) 648 } 649 650 def getImmUnion(immType: UInt) : Imm = { 651 val iuMap = Map( 652 IMM_S.litValue -> ImmUnion.S, 653 IMM_SB.litValue -> ImmUnion.B, 654 IMM_U.litValue -> ImmUnion.U, 655 IMM_UJ.litValue -> ImmUnion.J, 656 IMM_I.litValue -> ImmUnion.I, 657 IMM_Z.litValue -> ImmUnion.Z, 658 IMM_B6.litValue -> ImmUnion.B6, 659 IMM_OPIVIS.litValue -> ImmUnion.OPIVIS, 660 IMM_OPIVIU.litValue -> ImmUnion.OPIVIU, 661 IMM_VSETVLI.litValue -> ImmUnion.VSETVLI, 662 IMM_VSETIVLI.litValue -> ImmUnion.VSETIVLI, 663 IMM_LUI32.litValue -> ImmUnion.LUI32, 664 IMM_VRORVI.litValue -> ImmUnion.VRORVI, 665 ) 666 iuMap(immType.litValue) 667 } 668 } 669 670 object UopSplitType { 671 def SCA_SIM = "b000000".U // 672 def VSET = "b010001".U // dirty: vset 673 def VEC_VVV = "b010010".U // VEC_VVV 674 def VEC_VXV = "b010011".U // VEC_VXV 675 def VEC_0XV = "b010100".U // VEC_0XV 676 def VEC_VVW = "b010101".U // VEC_VVW 677 def VEC_WVW = "b010110".U // VEC_WVW 678 def VEC_VXW = "b010111".U // VEC_VXW 679 def VEC_WXW = "b011000".U // VEC_WXW 680 def VEC_WVV = "b011001".U // VEC_WVV 681 def VEC_WXV = "b011010".U // VEC_WXV 682 def VEC_EXT2 = "b011011".U // VF2 0 -> V 683 def VEC_EXT4 = "b011100".U // VF4 0 -> V 684 def VEC_EXT8 = "b011101".U // VF8 0 -> V 685 def VEC_VVM = "b011110".U // VEC_VVM 686 def VEC_VXM = "b011111".U // VEC_VXM 687 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 688 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 689 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 690 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 691 def VEC_VRED = "b100100".U // VEC_VRED 692 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 693 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 694 def VEC_M0X = "b101001".U // VEC_M0X 0MV 695 def VEC_MVV = "b101010".U // VEC_MVV VMV 696 def VEC_M0X_VFIRST = "b101011".U // 697 def VEC_VWW = "b101100".U // 698 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 699 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 700 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 701 def VEC_COMPRESS = "b110000".U // vcompress.vm 702 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 703 def VEC_S_LDST = "b110010".U // vector strided load/store 704 def VEC_I_LDST = "b110011".U // vector indexed load/store 705 def VEC_VFV = "b111000".U // VEC_VFV 706 def VEC_VFW = "b111001".U // VEC_VFW 707 def VEC_WFW = "b111010".U // VEC_WVW 708 def VEC_VFM = "b111011".U // VEC_VFM 709 def VEC_VFRED = "b111100".U // VEC_VFRED 710 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 711 def VEC_M0M = "b000000".U // VEC_M0M 712 def VEC_MMM = "b000000".U // VEC_MMM 713 def VEC_MVNR = "b000100".U // vmvnr 714 def dummy = "b111111".U 715 716 def X = BitPat("b000000") 717 718 def apply() = UInt(6.W) 719 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 720 } 721 722 object ExceptionNO { 723 def instrAddrMisaligned = 0 724 def instrAccessFault = 1 725 def illegalInstr = 2 726 def breakPoint = 3 727 def loadAddrMisaligned = 4 728 def loadAccessFault = 5 729 def storeAddrMisaligned = 6 730 def storeAccessFault = 7 731 def ecallU = 8 732 def ecallS = 9 733 def ecallM = 11 734 def instrPageFault = 12 735 def loadPageFault = 13 736 // def singleStep = 14 737 def storePageFault = 15 738 def priorities = Seq( 739 breakPoint, // TODO: different BP has different priority 740 instrPageFault, 741 instrAccessFault, 742 illegalInstr, 743 instrAddrMisaligned, 744 ecallM, ecallS, ecallU, 745 storeAddrMisaligned, 746 loadAddrMisaligned, 747 storePageFault, 748 loadPageFault, 749 storeAccessFault, 750 loadAccessFault 751 ) 752 def all = priorities.distinct.sorted 753 def frontendSet = Seq( 754 instrAddrMisaligned, 755 instrAccessFault, 756 illegalInstr, 757 instrPageFault 758 ) 759 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 760 val new_vec = Wire(ExceptionVec()) 761 new_vec.foreach(_ := false.B) 762 select.foreach(i => new_vec(i) := vec(i)) 763 new_vec 764 } 765 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 766 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 767 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 768 partialSelect(vec, fuConfig.exceptionOut) 769 } 770 771 object TopDownCounters extends Enumeration { 772 val NoStall = Value("NoStall") // Base 773 // frontend 774 val OverrideBubble = Value("OverrideBubble") 775 val FtqUpdateBubble = Value("FtqUpdateBubble") 776 // val ControlRedirectBubble = Value("ControlRedirectBubble") 777 val TAGEMissBubble = Value("TAGEMissBubble") 778 val SCMissBubble = Value("SCMissBubble") 779 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 780 val RASMissBubble = Value("RASMissBubble") 781 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 782 val OtherRedirectBubble = Value("OtherRedirectBubble") 783 val FtqFullStall = Value("FtqFullStall") 784 785 val ICacheMissBubble = Value("ICacheMissBubble") 786 val ITLBMissBubble = Value("ITLBMissBubble") 787 val BTBMissBubble = Value("BTBMissBubble") 788 val FetchFragBubble = Value("FetchFragBubble") 789 790 // backend 791 // long inst stall at rob head 792 val DivStall = Value("DivStall") // int div, float div/sqrt 793 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 794 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 795 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 796 // freelist full 797 val IntFlStall = Value("IntFlStall") 798 val FpFlStall = Value("FpFlStall") 799 // dispatch queue full 800 val IntDqStall = Value("IntDqStall") 801 val FpDqStall = Value("FpDqStall") 802 val LsDqStall = Value("LsDqStall") 803 804 // memblock 805 val LoadTLBStall = Value("LoadTLBStall") 806 val LoadL1Stall = Value("LoadL1Stall") 807 val LoadL2Stall = Value("LoadL2Stall") 808 val LoadL3Stall = Value("LoadL3Stall") 809 val LoadMemStall = Value("LoadMemStall") 810 val StoreStall = Value("StoreStall") // include store tlb miss 811 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 812 813 // xs replay (different to gem5) 814 val LoadVioReplayStall = Value("LoadVioReplayStall") 815 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 816 817 // bad speculation 818 val ControlRecoveryStall = Value("ControlRecoveryStall") 819 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 820 val OtherRecoveryStall = Value("OtherRecoveryStall") 821 822 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 823 824 val OtherCoreStall = Value("OtherCoreStall") 825 826 val NumStallReasons = Value("NumStallReasons") 827 } 828} 829