1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isFp(srcType: UInt) = srcType(1) 46 def isVp(srcType: UInt) = srcType(2) 47 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 48 49 def apply() = UInt(3.W) 50 } 51 52 object SrcState { 53 def busy = "b0".U 54 def rdy = "b1".U 55 // def specRdy = "b10".U // speculative ready, for future use 56 def apply() = UInt(1.W) 57 } 58 59 // Todo: Use OH instead 60 object FuType { 61 def jmp = "b00000".U 62 def i2f = "b00001".U 63 def csr = "b00010".U 64 def alu = "b00110".U 65 def mul = "b00100".U 66 def div = "b00101".U 67 def fence = "b00011".U 68 def bku = "b00111".U 69 70 def fmac = "b01000".U 71 def fmisc = "b01011".U 72 def fDivSqrt = "b01010".U 73 74 def ldu = "b01100".U 75 def stu = "b01101".U 76 def mou = "b01111".U // for amo, lr, sc, fence 77 def vipu = "b10000".U 78 def vfpu = "b11000".U 79 def vldu = "b11100".U 80 def vstu = "b11101".U 81 def X = BitPat("b00000") 82 83 def num = 18 84 85 def apply() = UInt(log2Up(num).W) 86 87 def isIntExu(fuType: UInt) = !fuType(3) 88 def isJumpExu(fuType: UInt) = fuType === jmp 89 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 90 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 91 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 92 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 93 def isAMO(fuType: UInt) = fuType(1) 94 def isFence(fuType: UInt) = fuType === fence 95 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 96 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 97 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 98 def isVpu(fuType: UInt) = fuType(4) 99 100 def jmpCanAccept(fuType: UInt) = !fuType(2) 101 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 102 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 103 104 def fmacCanAccept(fuType: UInt) = !fuType(1) 105 def fmiscCanAccept(fuType: UInt) = fuType(1) 106 107 def loadCanAccept(fuType: UInt) = !fuType(0) 108 def storeCanAccept(fuType: UInt) = fuType(0) 109 110 def storeIsAMO(fuType: UInt) = fuType(1) 111 112 val functionNameMap = Map( 113 jmp.litValue() -> "jmp", 114 i2f.litValue() -> "int_to_float", 115 csr.litValue() -> "csr", 116 alu.litValue() -> "alu", 117 mul.litValue() -> "mul", 118 div.litValue() -> "div", 119 fence.litValue() -> "fence", 120 bku.litValue() -> "bku", 121 fmac.litValue() -> "fmac", 122 fmisc.litValue() -> "fmisc", 123 fDivSqrt.litValue() -> "fdiv_fsqrt", 124 ldu.litValue() -> "load", 125 stu.litValue() -> "store", 126 mou.litValue() -> "mou" 127 ) 128 } 129 130 def FuOpTypeWidth = 8 131 object FuOpType { 132 def apply() = UInt(FuOpTypeWidth.W) 133 def X = BitPat("b00000000") 134 } 135 136 // move VipuType and VfpuType into YunSuan/package.scala 137 // object VipuType { 138 // def dummy = 0.U(7.W) 139 // } 140 141 // object VfpuType { 142 // def dummy = 0.U(7.W) 143 // } 144 145 object VlduType { 146 def dummy = 0.U 147 } 148 149 object VstuType { 150 def dummy = 0.U 151 } 152 153 object CommitType { 154 def NORMAL = "b000".U // int/fp 155 def BRANCH = "b001".U // branch 156 def LOAD = "b010".U // load 157 def STORE = "b011".U // store 158 159 def apply() = UInt(3.W) 160 def isFused(commitType: UInt): Bool = commitType(2) 161 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 162 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 163 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 164 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 165 } 166 167 object RedirectLevel { 168 def flushAfter = "b0".U 169 def flush = "b1".U 170 171 def apply() = UInt(1.W) 172 // def isUnconditional(level: UInt) = level(1) 173 def flushItself(level: UInt) = level(0) 174 // def isException(level: UInt) = level(1) && level(0) 175 } 176 177 object ExceptionVec { 178 def apply() = Vec(16, Bool()) 179 } 180 181 object PMAMode { 182 def R = "b1".U << 0 //readable 183 def W = "b1".U << 1 //writeable 184 def X = "b1".U << 2 //executable 185 def I = "b1".U << 3 //cacheable: icache 186 def D = "b1".U << 4 //cacheable: dcache 187 def S = "b1".U << 5 //enable speculative access 188 def A = "b1".U << 6 //enable atomic operation, A imply R & W 189 def C = "b1".U << 7 //if it is cacheable is configable 190 def Reserved = "b0".U 191 192 def apply() = UInt(7.W) 193 194 def read(mode: UInt) = mode(0) 195 def write(mode: UInt) = mode(1) 196 def execute(mode: UInt) = mode(2) 197 def icache(mode: UInt) = mode(3) 198 def dcache(mode: UInt) = mode(4) 199 def speculate(mode: UInt) = mode(5) 200 def atomic(mode: UInt) = mode(6) 201 def configable_cache(mode: UInt) = mode(7) 202 203 def strToMode(s: String) = { 204 var result = 0.U(8.W) 205 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 206 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 207 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 208 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 209 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 210 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 211 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 212 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 213 result 214 } 215 } 216 217 218 object CSROpType { 219 def jmp = "b000".U 220 def wrt = "b001".U 221 def set = "b010".U 222 def clr = "b011".U 223 def wfi = "b100".U 224 def wrti = "b101".U 225 def seti = "b110".U 226 def clri = "b111".U 227 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 228 } 229 230 // jump 231 object JumpOpType { 232 def jal = "b00".U 233 def jalr = "b01".U 234 def auipc = "b10".U 235// def call = "b11_011".U 236// def ret = "b11_100".U 237 def jumpOpisJalr(op: UInt) = op(0) 238 def jumpOpisAuipc(op: UInt) = op(1) 239 } 240 241 object FenceOpType { 242 def fence = "b10000".U 243 def sfence = "b10001".U 244 def fencei = "b10010".U 245 def nofence= "b00000".U 246 } 247 248 object ALUOpType { 249 // shift optype 250 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 251 def sll = "b000_0001".U // sll: src1 << src2 252 253 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 254 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 255 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 256 257 def srl = "b000_0101".U // srl: src1 >> src2 258 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 259 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 260 261 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 262 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 263 264 // RV64 32bit optype 265 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 266 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 267 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 268 269 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 270 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 271 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 272 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 273 274 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 275 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 276 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 277 def rolw = "b001_1100".U 278 def rorw = "b001_1101".U 279 280 // ADD-op 281 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 282 def add = "b010_0001".U // add: src1 + src2 283 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 284 285 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 286 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 287 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 288 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 289 290 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 291 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 292 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 293 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 294 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 295 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 296 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 297 298 // SUB-op: src1 - src2 299 def sub = "b011_0000".U 300 def sltu = "b011_0001".U 301 def slt = "b011_0010".U 302 def maxu = "b011_0100".U 303 def minu = "b011_0101".U 304 def max = "b011_0110".U 305 def min = "b011_0111".U 306 307 // branch 308 def beq = "b111_0000".U 309 def bne = "b111_0010".U 310 def blt = "b111_1000".U 311 def bge = "b111_1010".U 312 def bltu = "b111_1100".U 313 def bgeu = "b111_1110".U 314 315 // misc optype 316 def and = "b100_0000".U 317 def andn = "b100_0001".U 318 def or = "b100_0010".U 319 def orn = "b100_0011".U 320 def xor = "b100_0100".U 321 def xnor = "b100_0101".U 322 def orcb = "b100_0110".U 323 324 def sextb = "b100_1000".U 325 def packh = "b100_1001".U 326 def sexth = "b100_1010".U 327 def packw = "b100_1011".U 328 329 def revb = "b101_0000".U 330 def rev8 = "b101_0001".U 331 def pack = "b101_0010".U 332 def orh48 = "b101_0011".U 333 334 def szewl1 = "b101_1000".U 335 def szewl2 = "b101_1001".U 336 def szewl3 = "b101_1010".U 337 def byte2 = "b101_1011".U 338 339 def andlsb = "b110_0000".U 340 def andzexth = "b110_0001".U 341 def orlsb = "b110_0010".U 342 def orzexth = "b110_0011".U 343 def xorlsb = "b110_0100".U 344 def xorzexth = "b110_0101".U 345 def orcblsb = "b110_0110".U 346 def orcbzexth = "b110_0111".U 347 def vsetvli1 = "b1000_0000".U 348 def vsetvli2 = "b1000_0100".U 349 def vsetvl1 = "b1000_0001".U 350 def vsetvl2 = "b1000_0101".U 351 def vsetivli1 = "b1000_0010".U 352 def vsetivli2 = "b1000_0110".U 353 354 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 355 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 356 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 357 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 358 def isBranch(func: UInt) = func(6, 4) === "b111".U 359 def getBranchType(func: UInt) = func(3, 2) 360 def isBranchInvert(func: UInt) = func(1) 361 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 362 def isVsetvl(func: UInt) = isVset(func) && func(0) 363 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 364 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 365 366 def apply() = UInt(FuOpTypeWidth.W) 367 } 368 369 object MDUOpType { 370 // mul 371 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 372 def mul = "b00000".U 373 def mulh = "b00001".U 374 def mulhsu = "b00010".U 375 def mulhu = "b00011".U 376 def mulw = "b00100".U 377 378 def mulw7 = "b01100".U 379 380 // div 381 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 382 def div = "b10000".U 383 def divu = "b10010".U 384 def rem = "b10001".U 385 def remu = "b10011".U 386 387 def divw = "b10100".U 388 def divuw = "b10110".U 389 def remw = "b10101".U 390 def remuw = "b10111".U 391 392 def isMul(op: UInt) = !op(4) 393 def isDiv(op: UInt) = op(4) 394 395 def isDivSign(op: UInt) = isDiv(op) && !op(1) 396 def isW(op: UInt) = op(2) 397 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 398 def getMulOp(op: UInt) = op(1, 0) 399 } 400 401 object LSUOpType { 402 // load pipeline 403 404 // normal load 405 // Note: bit(1, 0) are size, DO NOT CHANGE 406 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 407 def lb = "b0000".U 408 def lh = "b0001".U 409 def lw = "b0010".U 410 def ld = "b0011".U 411 def lbu = "b0100".U 412 def lhu = "b0101".U 413 def lwu = "b0110".U 414 415 // Zicbop software prefetch 416 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 417 def prefetch_i = "b1000".U // TODO 418 def prefetch_r = "b1001".U 419 def prefetch_w = "b1010".U 420 421 def isPrefetch(op: UInt): Bool = op(3) 422 423 // store pipeline 424 // normal store 425 // bit encoding: | store 00 | size(2bit) | 426 def sb = "b0000".U 427 def sh = "b0001".U 428 def sw = "b0010".U 429 def sd = "b0011".U 430 431 // l1 cache op 432 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 433 def cbo_zero = "b0111".U 434 435 // llc op 436 // bit encoding: | prefetch 11 | suboptype(2bit) | 437 def cbo_clean = "b1100".U 438 def cbo_flush = "b1101".U 439 def cbo_inval = "b1110".U 440 441 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 442 443 // atomics 444 // bit(1, 0) are size 445 // since atomics use a different fu type 446 // so we can safely reuse other load/store's encodings 447 // bit encoding: | optype(4bit) | size (2bit) | 448 def lr_w = "b000010".U 449 def sc_w = "b000110".U 450 def amoswap_w = "b001010".U 451 def amoadd_w = "b001110".U 452 def amoxor_w = "b010010".U 453 def amoand_w = "b010110".U 454 def amoor_w = "b011010".U 455 def amomin_w = "b011110".U 456 def amomax_w = "b100010".U 457 def amominu_w = "b100110".U 458 def amomaxu_w = "b101010".U 459 460 def lr_d = "b000011".U 461 def sc_d = "b000111".U 462 def amoswap_d = "b001011".U 463 def amoadd_d = "b001111".U 464 def amoxor_d = "b010011".U 465 def amoand_d = "b010111".U 466 def amoor_d = "b011011".U 467 def amomin_d = "b011111".U 468 def amomax_d = "b100011".U 469 def amominu_d = "b100111".U 470 def amomaxu_d = "b101011".U 471 472 def size(op: UInt) = op(1,0) 473 } 474 475 object BKUOpType { 476 477 def clmul = "b000000".U 478 def clmulh = "b000001".U 479 def clmulr = "b000010".U 480 def xpermn = "b000100".U 481 def xpermb = "b000101".U 482 483 def clz = "b001000".U 484 def clzw = "b001001".U 485 def ctz = "b001010".U 486 def ctzw = "b001011".U 487 def cpop = "b001100".U 488 def cpopw = "b001101".U 489 490 // 01xxxx is reserve 491 def aes64es = "b100000".U 492 def aes64esm = "b100001".U 493 def aes64ds = "b100010".U 494 def aes64dsm = "b100011".U 495 def aes64im = "b100100".U 496 def aes64ks1i = "b100101".U 497 def aes64ks2 = "b100110".U 498 499 // merge to two instruction sm4ks & sm4ed 500 def sm4ed0 = "b101000".U 501 def sm4ed1 = "b101001".U 502 def sm4ed2 = "b101010".U 503 def sm4ed3 = "b101011".U 504 def sm4ks0 = "b101100".U 505 def sm4ks1 = "b101101".U 506 def sm4ks2 = "b101110".U 507 def sm4ks3 = "b101111".U 508 509 def sha256sum0 = "b110000".U 510 def sha256sum1 = "b110001".U 511 def sha256sig0 = "b110010".U 512 def sha256sig1 = "b110011".U 513 def sha512sum0 = "b110100".U 514 def sha512sum1 = "b110101".U 515 def sha512sig0 = "b110110".U 516 def sha512sig1 = "b110111".U 517 518 def sm3p0 = "b111000".U 519 def sm3p1 = "b111001".U 520 } 521 522 object BTBtype { 523 def B = "b00".U // branch 524 def J = "b01".U // jump 525 def I = "b10".U // indirect 526 def R = "b11".U // return 527 528 def apply() = UInt(2.W) 529 } 530 531 object SelImm { 532 def IMM_X = "b0111".U 533 def IMM_S = "b0000".U 534 def IMM_SB = "b0001".U 535 def IMM_U = "b0010".U 536 def IMM_UJ = "b0011".U 537 def IMM_I = "b0100".U 538 def IMM_Z = "b0101".U 539 def INVALID_INSTR = "b0110".U 540 def IMM_B6 = "b1000".U 541 542 def IMM_OPIVIS = "b1001".U 543 def IMM_OPIVIU = "b1010".U 544 def IMM_VSETVLI = "b1100".U 545 def IMM_VSETIVLI = "b1101".U 546 547 def X = BitPat("b0000") 548 549 def apply() = UInt(4.W) 550 } 551 552 object ExceptionNO { 553 def instrAddrMisaligned = 0 554 def instrAccessFault = 1 555 def illegalInstr = 2 556 def breakPoint = 3 557 def loadAddrMisaligned = 4 558 def loadAccessFault = 5 559 def storeAddrMisaligned = 6 560 def storeAccessFault = 7 561 def ecallU = 8 562 def ecallS = 9 563 def ecallM = 11 564 def instrPageFault = 12 565 def loadPageFault = 13 566 // def singleStep = 14 567 def storePageFault = 15 568 def priorities = Seq( 569 breakPoint, // TODO: different BP has different priority 570 instrPageFault, 571 instrAccessFault, 572 illegalInstr, 573 instrAddrMisaligned, 574 ecallM, ecallS, ecallU, 575 storeAddrMisaligned, 576 loadAddrMisaligned, 577 storePageFault, 578 loadPageFault, 579 storeAccessFault, 580 loadAccessFault 581 ) 582 def all = priorities.distinct.sorted 583 def frontendSet = Seq( 584 instrAddrMisaligned, 585 instrAccessFault, 586 illegalInstr, 587 instrPageFault 588 ) 589 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 590 val new_vec = Wire(ExceptionVec()) 591 new_vec.foreach(_ := false.B) 592 select.foreach(i => new_vec(i) := vec(i)) 593 new_vec 594 } 595 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 596 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 597 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 598 partialSelect(vec, fuConfig.exceptionOut) 599 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 600 partialSelect(vec, exuConfig.exceptionOut) 601 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 602 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 603 } 604 605 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 606 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 607 def aluGen(p: Parameters) = new Alu()(p) 608 def bkuGen(p: Parameters) = new Bku()(p) 609 def jmpGen(p: Parameters) = new Jump()(p) 610 def fenceGen(p: Parameters) = new Fence()(p) 611 def csrGen(p: Parameters) = new CSR()(p) 612 def i2fGen(p: Parameters) = new IntToFP()(p) 613 def fmacGen(p: Parameters) = new FMA()(p) 614 def f2iGen(p: Parameters) = new FPToInt()(p) 615 def f2fGen(p: Parameters) = new FPToFP()(p) 616 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 617 def stdGen(p: Parameters) = new Std()(p) 618 def mouDataGen(p: Parameters) = new Std()(p) 619 def vipuGen(p: Parameters) = new VIPU()(p) 620 621 def f2iSel(uop: MicroOp): Bool = { 622 uop.ctrl.rfWen 623 } 624 625 def i2fSel(uop: MicroOp): Bool = { 626 uop.ctrl.fpu.fromInt 627 } 628 629 def f2fSel(uop: MicroOp): Bool = { 630 val ctrl = uop.ctrl.fpu 631 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 632 } 633 634 def fdivSqrtSel(uop: MicroOp): Bool = { 635 val ctrl = uop.ctrl.fpu 636 ctrl.div || ctrl.sqrt 637 } 638 639 val aluCfg = FuConfig( 640 name = "alu", 641 fuGen = aluGen, 642 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 643 fuType = FuType.alu, 644 numIntSrc = 2, 645 numFpSrc = 0, 646 writeIntRf = true, 647 writeFpRf = false, 648 hasRedirect = true, 649 ) 650 651 val jmpCfg = FuConfig( 652 name = "jmp", 653 fuGen = jmpGen, 654 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 655 fuType = FuType.jmp, 656 numIntSrc = 1, 657 numFpSrc = 0, 658 writeIntRf = true, 659 writeFpRf = false, 660 hasRedirect = true, 661 ) 662 663 val fenceCfg = FuConfig( 664 name = "fence", 665 fuGen = fenceGen, 666 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 667 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 668 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 669 flushPipe = true 670 ) 671 672 val csrCfg = FuConfig( 673 name = "csr", 674 fuGen = csrGen, 675 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 676 fuType = FuType.csr, 677 numIntSrc = 1, 678 numFpSrc = 0, 679 writeIntRf = true, 680 writeFpRf = false, 681 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 682 flushPipe = true 683 ) 684 685 val i2fCfg = FuConfig( 686 name = "i2f", 687 fuGen = i2fGen, 688 fuSel = i2fSel, 689 FuType.i2f, 690 numIntSrc = 1, 691 numFpSrc = 0, 692 writeIntRf = false, 693 writeFpRf = true, 694 writeFflags = true, 695 latency = CertainLatency(2), 696 fastUopOut = true, fastImplemented = true 697 ) 698 699 val divCfg = FuConfig( 700 name = "div", 701 fuGen = dividerGen, 702 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 703 FuType.div, 704 2, 705 0, 706 writeIntRf = true, 707 writeFpRf = false, 708 latency = UncertainLatency(), 709 fastUopOut = true, 710 fastImplemented = true, 711 hasInputBuffer = (true, 4, true) 712 ) 713 714 val mulCfg = FuConfig( 715 name = "mul", 716 fuGen = multiplierGen, 717 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 718 FuType.mul, 719 2, 720 0, 721 writeIntRf = true, 722 writeFpRf = false, 723 latency = CertainLatency(2), 724 fastUopOut = true, 725 fastImplemented = true 726 ) 727 728 val bkuCfg = FuConfig( 729 name = "bku", 730 fuGen = bkuGen, 731 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 732 fuType = FuType.bku, 733 numIntSrc = 2, 734 numFpSrc = 0, 735 writeIntRf = true, 736 writeFpRf = false, 737 latency = CertainLatency(1), 738 fastUopOut = true, 739 fastImplemented = true 740 ) 741 742 val fmacCfg = FuConfig( 743 name = "fmac", 744 fuGen = fmacGen, 745 fuSel = _ => true.B, 746 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 747 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 748 ) 749 750 val f2iCfg = FuConfig( 751 name = "f2i", 752 fuGen = f2iGen, 753 fuSel = f2iSel, 754 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 755 fastUopOut = true, fastImplemented = true 756 ) 757 758 val f2fCfg = FuConfig( 759 name = "f2f", 760 fuGen = f2fGen, 761 fuSel = f2fSel, 762 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 763 fastUopOut = true, fastImplemented = true 764 ) 765 766 val fdivSqrtCfg = FuConfig( 767 name = "fdivSqrt", 768 fuGen = fdivSqrtGen, 769 fuSel = fdivSqrtSel, 770 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 771 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 772 ) 773 774 val lduCfg = FuConfig( 775 "ldu", 776 null, // DontCare 777 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 778 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 779 latency = UncertainLatency(), 780 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 781 flushPipe = true, 782 replayInst = true, 783 hasLoadError = true 784 ) 785 786 val staCfg = FuConfig( 787 "sta", 788 null, 789 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 790 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 791 latency = UncertainLatency(), 792 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 793 ) 794 795 val stdCfg = FuConfig( 796 "std", 797 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 798 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 799 ) 800 801 val mouCfg = FuConfig( 802 "mou", 803 null, 804 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 805 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 806 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 807 ) 808 809 val mouDataCfg = FuConfig( 810 "mou", 811 mouDataGen, 812 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 813 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 814 latency = UncertainLatency() 815 ) 816 817 val vipuCfg = FuConfig( 818 name = "vipu", 819 fuGen = vipuGen, 820 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 821 fuType = FuType.vipu, 822 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 823 numVecSrc = 2, writeVecRf = true, 824 fastUopOut = true, // TODO: check 825 fastImplemented = true, //TODO: check 826 ) 827 828 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 829 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 830 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 831 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 832 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 833 val FmiscExeUnitCfg = ExuConfig( 834 "FmiscExeUnit", 835 "Fp", 836 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 837 Int.MaxValue, 1 838 ) 839 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 840 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 841 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 842 843 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 844 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 845 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 846 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 847 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 848 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 849 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 850 851 val aluRSMod = new RSMod( 852 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 853 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 854 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 855 ) 856 val fmaRSMod = new RSMod( 857 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 858 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 859 ) 860 val fmiscRSMod = new RSMod( 861 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 862 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 863 ) 864 val jumpRSMod = new RSMod( 865 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 866 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 867 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 868 ) 869 val loadRSMod = new RSMod( 870 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 871 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 872 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 873 ) 874 val mulRSMod = new RSMod( 875 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 876 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 877 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 878 ) 879 val staRSMod = new RSMod( 880 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 881 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 882 ) 883 val stdRSMod = new RSMod( 884 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 885 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 886 ) 887} 888