1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 def no = "b000".U // this src read no reg but cannot be Any value 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 51 def apply() = UInt(3.W) 52 } 53 54 object SrcState { 55 def busy = "b0".U 56 def rdy = "b1".U 57 // def specRdy = "b10".U // speculative ready, for future use 58 def apply() = UInt(1.W) 59 60 def isReady(state: UInt): Bool = state === this.rdy 61 def isBusy(state: UInt): Bool = state === this.busy 62 } 63 64 def FuOpTypeWidth = 9 65 object FuOpType { 66 def apply() = UInt(FuOpTypeWidth.W) 67 def X = BitPat("b00000000") 68 } 69 70 object VlduType { 71 def dummy = 0.U 72 } 73 74 object VstuType { 75 def dummy = 0.U 76 } 77 78 object IF2VectorType { 79 // use last 3 bits for vsew 80 def i2vector = "b00_00".U 81 def f2vector = "b00_01".U 82 def imm2vector = "b00_10".U 83 def permImm2vector = "b00_11".U 84 } 85 86 object CommitType { 87 def NORMAL = "b000".U // int/fp 88 def BRANCH = "b001".U // branch 89 def LOAD = "b010".U // load 90 def STORE = "b011".U // store 91 92 def apply() = UInt(3.W) 93 def isFused(commitType: UInt): Bool = commitType(2) 94 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 95 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 96 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 97 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 98 } 99 100 object RedirectLevel { 101 def flushAfter = "b0".U 102 def flush = "b1".U 103 104 def apply() = UInt(1.W) 105 // def isUnconditional(level: UInt) = level(1) 106 def flushItself(level: UInt) = level(0) 107 // def isException(level: UInt) = level(1) && level(0) 108 } 109 110 object ExceptionVec { 111 val ExceptionVecSize = 16 112 def apply() = Vec(ExceptionVecSize, Bool()) 113 } 114 115 object PMAMode { 116 def R = "b1".U << 0 //readable 117 def W = "b1".U << 1 //writeable 118 def X = "b1".U << 2 //executable 119 def I = "b1".U << 3 //cacheable: icache 120 def D = "b1".U << 4 //cacheable: dcache 121 def S = "b1".U << 5 //enable speculative access 122 def A = "b1".U << 6 //enable atomic operation, A imply R & W 123 def C = "b1".U << 7 //if it is cacheable is configable 124 def Reserved = "b0".U 125 126 def apply() = UInt(7.W) 127 128 def read(mode: UInt) = mode(0) 129 def write(mode: UInt) = mode(1) 130 def execute(mode: UInt) = mode(2) 131 def icache(mode: UInt) = mode(3) 132 def dcache(mode: UInt) = mode(4) 133 def speculate(mode: UInt) = mode(5) 134 def atomic(mode: UInt) = mode(6) 135 def configable_cache(mode: UInt) = mode(7) 136 137 def strToMode(s: String) = { 138 var result = 0.U(8.W) 139 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 140 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 141 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 142 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 143 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 144 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 145 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 146 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 147 result 148 } 149 } 150 151 152 object CSROpType { 153 def jmp = "b000".U 154 def wrt = "b001".U 155 def set = "b010".U 156 def clr = "b011".U 157 def wfi = "b100".U 158 def wrti = "b101".U 159 def seti = "b110".U 160 def clri = "b111".U 161 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 162 } 163 164 // jump 165 object JumpOpType { 166 def jal = "b00".U 167 def jalr = "b01".U 168 def auipc = "b10".U 169// def call = "b11_011".U 170// def ret = "b11_100".U 171 def jumpOpisJalr(op: UInt) = op(0) 172 def jumpOpisAuipc(op: UInt) = op(1) 173 } 174 175 object FenceOpType { 176 def fence = "b10000".U 177 def sfence = "b10001".U 178 def fencei = "b10010".U 179 def nofence= "b00000".U 180 } 181 182 object ALUOpType { 183 // shift optype 184 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 185 def sll = "b000_0001".U // sll: src1 << src2 186 187 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 188 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 189 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 190 191 def srl = "b000_0101".U // srl: src1 >> src2 192 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 193 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 194 195 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 196 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 197 198 // RV64 32bit optype 199 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 200 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 201 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 202 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 203 204 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 205 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 206 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 207 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 208 209 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 210 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 211 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 212 def rolw = "b001_1100".U 213 def rorw = "b001_1101".U 214 215 // ADD-op 216 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 217 def add = "b010_0001".U // add: src1 + src2 218 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 219 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 220 221 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 222 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 223 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 224 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 225 226 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 227 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 228 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 229 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 230 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 231 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 232 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 233 234 // SUB-op: src1 - src2 235 def sub = "b011_0000".U 236 def sltu = "b011_0001".U 237 def slt = "b011_0010".U 238 def maxu = "b011_0100".U 239 def minu = "b011_0101".U 240 def max = "b011_0110".U 241 def min = "b011_0111".U 242 243 // branch 244 def beq = "b111_0000".U 245 def bne = "b111_0010".U 246 def blt = "b111_1000".U 247 def bge = "b111_1010".U 248 def bltu = "b111_1100".U 249 def bgeu = "b111_1110".U 250 251 // misc optype 252 def and = "b100_0000".U 253 def andn = "b100_0001".U 254 def or = "b100_0010".U 255 def orn = "b100_0011".U 256 def xor = "b100_0100".U 257 def xnor = "b100_0101".U 258 def orcb = "b100_0110".U 259 260 def sextb = "b100_1000".U 261 def packh = "b100_1001".U 262 def sexth = "b100_1010".U 263 def packw = "b100_1011".U 264 265 def revb = "b101_0000".U 266 def rev8 = "b101_0001".U 267 def pack = "b101_0010".U 268 def orh48 = "b101_0011".U 269 270 def szewl1 = "b101_1000".U 271 def szewl2 = "b101_1001".U 272 def szewl3 = "b101_1010".U 273 def byte2 = "b101_1011".U 274 275 def andlsb = "b110_0000".U 276 def andzexth = "b110_0001".U 277 def orlsb = "b110_0010".U 278 def orzexth = "b110_0011".U 279 def xorlsb = "b110_0100".U 280 def xorzexth = "b110_0101".U 281 def orcblsb = "b110_0110".U 282 def orcbzexth = "b110_0111".U 283 284 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 285 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 286 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 287 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 288 289 def apply() = UInt(FuOpTypeWidth.W) 290 } 291 292 object VSETOpType { 293 val setVlmaxBit = 0 294 val keepVlBit = 1 295 // destTypeBit == 0: write vl to rd 296 // destTypeBit == 1: write vconfig 297 val destTypeBit = 5 298 299 // vsetvli's uop 300 // rs1!=x0, normal 301 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 302 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 303 def uvsetvcfg_xi = "b1010_0000".U 304 def uvsetrd_xi = "b1000_0000".U 305 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 306 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 307 // uop1: w(rd) | vlmax, vtypei -> x[rd] 308 def uvsetvcfg_vlmax_i = "b1010_0001".U 309 def uvsetrd_vlmax_i = "b1000_0001".U 310 // rs1==x0, rd==x0, keep vl, set vtype 311 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 312 def uvsetvcfg_keep_v = "b1010_0010".U 313 314 // vsetvl's uop 315 // rs1!=x0, normal 316 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 317 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 318 def uvsetvcfg_xx = "b0110_0000".U 319 def uvsetrd_xx = "b0100_0000".U 320 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 321 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 322 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 323 def uvsetvcfg_vlmax_x = "b0110_0001".U 324 def uvsetrd_vlmax_x = "b0100_0001".U 325 // rs1==x0, rd==x0, keep vl, set vtype 326 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 327 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 328 def uvmv_v_x = "b0110_0010".U 329 def uvsetvcfg_vv = "b0111_0010".U 330 331 // vsetivli's uop 332 // uop0: w(vconfig) | vli, vtypei -> vconfig 333 // uop1: w(rd) | vli, vtypei -> x[rd] 334 def uvsetvcfg_ii = "b0010_0000".U 335 def uvsetrd_ii = "b0000_0000".U 336 337 def isVsetvl (func: UInt) = func(6) 338 def isVsetvli (func: UInt) = func(7) 339 def isVsetivli(func: UInt) = func(7, 6) === 0.U 340 def isNormal (func: UInt) = func(1, 0) === 0.U 341 def isSetVlmax(func: UInt) = func(setVlmaxBit) 342 def isKeepVl (func: UInt) = func(keepVlBit) 343 // RG: region 344 def writeIntRG(func: UInt) = !func(5) 345 def writeVecRG(func: UInt) = func(5) 346 def readIntRG (func: UInt) = !func(4) 347 def readVecRG (func: UInt) = func(4) 348 // modify fuOpType 349 def switchDest(func: UInt) = func ^ (1 << destTypeBit).U 350 def keepVl(func: UInt) = func | (1 << keepVlBit).U 351 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 352 } 353 354 object BRUOpType { 355 // branch 356 def beq = "b000_000".U 357 def bne = "b000_001".U 358 def blt = "b000_100".U 359 def bge = "b000_101".U 360 def bltu = "b001_000".U 361 def bgeu = "b001_001".U 362 363 def getBranchType(func: UInt) = func(3, 1) 364 def isBranchInvert(func: UInt) = func(0) 365 } 366 367 object MULOpType { 368 // mul 369 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 370 def mul = "b00000".U 371 def mulh = "b00001".U 372 def mulhsu = "b00010".U 373 def mulhu = "b00011".U 374 def mulw = "b00100".U 375 376 def mulw7 = "b01100".U 377 def isSign(op: UInt) = !op(1) 378 def isW(op: UInt) = op(2) 379 def isH(op: UInt) = op(1, 0) =/= 0.U 380 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 381 } 382 383 object DIVOpType { 384 // div 385 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 386 def div = "b10000".U 387 def divu = "b10010".U 388 def rem = "b10001".U 389 def remu = "b10011".U 390 391 def divw = "b10100".U 392 def divuw = "b10110".U 393 def remw = "b10101".U 394 def remuw = "b10111".U 395 396 def isSign(op: UInt) = !op(1) 397 def isW(op: UInt) = op(2) 398 def isH(op: UInt) = op(0) 399 } 400 401 object MDUOpType { 402 // mul 403 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 404 def mul = "b00000".U 405 def mulh = "b00001".U 406 def mulhsu = "b00010".U 407 def mulhu = "b00011".U 408 def mulw = "b00100".U 409 410 def mulw7 = "b01100".U 411 412 // div 413 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 414 def div = "b10000".U 415 def divu = "b10010".U 416 def rem = "b10001".U 417 def remu = "b10011".U 418 419 def divw = "b10100".U 420 def divuw = "b10110".U 421 def remw = "b10101".U 422 def remuw = "b10111".U 423 424 def isMul(op: UInt) = !op(4) 425 def isDiv(op: UInt) = op(4) 426 427 def isDivSign(op: UInt) = isDiv(op) && !op(1) 428 def isW(op: UInt) = op(2) 429 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 430 def getMulOp(op: UInt) = op(1, 0) 431 } 432 433 object LSUOpType { 434 // load pipeline 435 436 // normal load 437 // Note: bit(1, 0) are size, DO NOT CHANGE 438 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 439 def lb = "b0000".U 440 def lh = "b0001".U 441 def lw = "b0010".U 442 def ld = "b0011".U 443 def lbu = "b0100".U 444 def lhu = "b0101".U 445 def lwu = "b0110".U 446 447 // Zicbop software prefetch 448 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 449 def prefetch_i = "b1000".U // TODO 450 def prefetch_r = "b1001".U 451 def prefetch_w = "b1010".U 452 453 def isPrefetch(op: UInt): Bool = op(3) 454 455 // store pipeline 456 // normal store 457 // bit encoding: | store 00 | size(2bit) | 458 def sb = "b0000".U 459 def sh = "b0001".U 460 def sw = "b0010".U 461 def sd = "b0011".U 462 463 // l1 cache op 464 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 465 def cbo_zero = "b0111".U 466 467 // llc op 468 // bit encoding: | prefetch 11 | suboptype(2bit) | 469 def cbo_clean = "b1100".U 470 def cbo_flush = "b1101".U 471 def cbo_inval = "b1110".U 472 473 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 474 475 // atomics 476 // bit(1, 0) are size 477 // since atomics use a different fu type 478 // so we can safely reuse other load/store's encodings 479 // bit encoding: | optype(4bit) | size (2bit) | 480 def lr_w = "b000010".U 481 def sc_w = "b000110".U 482 def amoswap_w = "b001010".U 483 def amoadd_w = "b001110".U 484 def amoxor_w = "b010010".U 485 def amoand_w = "b010110".U 486 def amoor_w = "b011010".U 487 def amomin_w = "b011110".U 488 def amomax_w = "b100010".U 489 def amominu_w = "b100110".U 490 def amomaxu_w = "b101010".U 491 492 def lr_d = "b000011".U 493 def sc_d = "b000111".U 494 def amoswap_d = "b001011".U 495 def amoadd_d = "b001111".U 496 def amoxor_d = "b010011".U 497 def amoand_d = "b010111".U 498 def amoor_d = "b011011".U 499 def amomin_d = "b011111".U 500 def amomax_d = "b100011".U 501 def amominu_d = "b100111".U 502 def amomaxu_d = "b101011".U 503 504 def size(op: UInt) = op(1,0) 505 } 506 507 object BKUOpType { 508 509 def clmul = "b000000".U 510 def clmulh = "b000001".U 511 def clmulr = "b000010".U 512 def xpermn = "b000100".U 513 def xpermb = "b000101".U 514 515 def clz = "b001000".U 516 def clzw = "b001001".U 517 def ctz = "b001010".U 518 def ctzw = "b001011".U 519 def cpop = "b001100".U 520 def cpopw = "b001101".U 521 522 // 01xxxx is reserve 523 def aes64es = "b100000".U 524 def aes64esm = "b100001".U 525 def aes64ds = "b100010".U 526 def aes64dsm = "b100011".U 527 def aes64im = "b100100".U 528 def aes64ks1i = "b100101".U 529 def aes64ks2 = "b100110".U 530 531 // merge to two instruction sm4ks & sm4ed 532 def sm4ed0 = "b101000".U 533 def sm4ed1 = "b101001".U 534 def sm4ed2 = "b101010".U 535 def sm4ed3 = "b101011".U 536 def sm4ks0 = "b101100".U 537 def sm4ks1 = "b101101".U 538 def sm4ks2 = "b101110".U 539 def sm4ks3 = "b101111".U 540 541 def sha256sum0 = "b110000".U 542 def sha256sum1 = "b110001".U 543 def sha256sig0 = "b110010".U 544 def sha256sig1 = "b110011".U 545 def sha512sum0 = "b110100".U 546 def sha512sum1 = "b110101".U 547 def sha512sig0 = "b110110".U 548 def sha512sig1 = "b110111".U 549 550 def sm3p0 = "b111000".U 551 def sm3p1 = "b111001".U 552 } 553 554 object BTBtype { 555 def B = "b00".U // branch 556 def J = "b01".U // jump 557 def I = "b10".U // indirect 558 def R = "b11".U // return 559 560 def apply() = UInt(2.W) 561 } 562 563 object SelImm { 564 def IMM_X = "b0111".U 565 def IMM_S = "b1110".U 566 def IMM_SB = "b0001".U 567 def IMM_U = "b0010".U 568 def IMM_UJ = "b0011".U 569 def IMM_I = "b0100".U 570 def IMM_Z = "b0101".U 571 def INVALID_INSTR = "b0110".U 572 def IMM_B6 = "b1000".U 573 574 def IMM_OPIVIS = "b1001".U 575 def IMM_OPIVIU = "b1010".U 576 def IMM_VSETVLI = "b1100".U 577 def IMM_VSETIVLI = "b1101".U 578 def IMM_LUI32 = "b1011".U 579 580 def X = BitPat("b0000") 581 582 def apply() = UInt(4.W) 583 584 def mkString(immType: UInt) : String = { 585 val strMap = Map( 586 IMM_S.litValue -> "S", 587 IMM_SB.litValue -> "SB", 588 IMM_U.litValue -> "U", 589 IMM_UJ.litValue -> "UJ", 590 IMM_I.litValue -> "I", 591 IMM_Z.litValue -> "Z", 592 IMM_B6.litValue -> "B6", 593 IMM_OPIVIS.litValue -> "VIS", 594 IMM_OPIVIU.litValue -> "VIU", 595 IMM_VSETVLI.litValue -> "VSETVLI", 596 IMM_VSETIVLI.litValue -> "VSETIVLI", 597 IMM_LUI32.litValue -> "LUI32", 598 INVALID_INSTR.litValue -> "INVALID", 599 ) 600 strMap(immType.litValue) 601 } 602 } 603 604 object UopSplitType { 605 def SCA_SIM = "b000000".U // 606 def DIR = "b010001".U // dirty: vset 607 def VEC_VVV = "b010010".U // VEC_VVV 608 def VEC_VXV = "b010011".U // VEC_VXV 609 def VEC_0XV = "b010100".U // VEC_0XV 610 def VEC_VVW = "b010101".U // VEC_VVW 611 def VEC_WVW = "b010110".U // VEC_WVW 612 def VEC_VXW = "b010111".U // VEC_VXW 613 def VEC_WXW = "b011000".U // VEC_WXW 614 def VEC_WVV = "b011001".U // VEC_WVV 615 def VEC_WXV = "b011010".U // VEC_WXV 616 def VEC_EXT2 = "b011011".U // VF2 0 -> V 617 def VEC_EXT4 = "b011100".U // VF4 0 -> V 618 def VEC_EXT8 = "b011101".U // VF8 0 -> V 619 def VEC_VVM = "b011110".U // VEC_VVM 620 def VEC_VXM = "b011111".U // VEC_VXM 621 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 622 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 623 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 624 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 625 def VEC_VRED = "b100100".U // VEC_VRED 626 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 627 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 628 def VEC_M0X = "b101001".U // VEC_M0X 0MV 629 def VEC_MVV = "b101010".U // VEC_MVV VMV 630 def VEC_M0X_VFIRST = "b101011".U // 631 def VEC_VWW = "b101100".U // 632 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 633 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 634 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 635 def VEC_COMPRESS = "b110000".U // vcompress.vm 636 def VEC_US_LD = "b110001".U // vector unit strided load 637 def VEC_VFV = "b111000".U // VEC_VFV 638 def VEC_VFW = "b111001".U // VEC_VFW 639 def VEC_WFW = "b111010".U // VEC_WVW 640 def VEC_VFM = "b111011".U // VEC_VFM 641 def VEC_VFRED = "b111100".U // VEC_VFRED 642 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 643 def VEC_M0M = "b000000".U // VEC_M0M 644 def VEC_MMM = "b000000".U // VEC_MMM 645 def VEC_MVNR = "b000100".U // vmvnr 646 def dummy = "b111111".U 647 648 def X = BitPat("b000000") 649 650 def apply() = UInt(6.W) 651 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 652 } 653 654 object ExceptionNO { 655 def instrAddrMisaligned = 0 656 def instrAccessFault = 1 657 def illegalInstr = 2 658 def breakPoint = 3 659 def loadAddrMisaligned = 4 660 def loadAccessFault = 5 661 def storeAddrMisaligned = 6 662 def storeAccessFault = 7 663 def ecallU = 8 664 def ecallS = 9 665 def ecallM = 11 666 def instrPageFault = 12 667 def loadPageFault = 13 668 // def singleStep = 14 669 def storePageFault = 15 670 def priorities = Seq( 671 breakPoint, // TODO: different BP has different priority 672 instrPageFault, 673 instrAccessFault, 674 illegalInstr, 675 instrAddrMisaligned, 676 ecallM, ecallS, ecallU, 677 storeAddrMisaligned, 678 loadAddrMisaligned, 679 storePageFault, 680 loadPageFault, 681 storeAccessFault, 682 loadAccessFault 683 ) 684 def all = priorities.distinct.sorted 685 def frontendSet = Seq( 686 instrAddrMisaligned, 687 instrAccessFault, 688 illegalInstr, 689 instrPageFault 690 ) 691 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 692 val new_vec = Wire(ExceptionVec()) 693 new_vec.foreach(_ := false.B) 694 select.foreach(i => new_vec(i) := vec(i)) 695 new_vec 696 } 697 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 698 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 699 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 700 partialSelect(vec, fuConfig.exceptionOut) 701 } 702 703 object TopDownCounters extends Enumeration { 704 val NoStall = Value("NoStall") // Base 705 // frontend 706 val OverrideBubble = Value("OverrideBubble") 707 val FtqUpdateBubble = Value("FtqUpdateBubble") 708 // val ControlRedirectBubble = Value("ControlRedirectBubble") 709 val TAGEMissBubble = Value("TAGEMissBubble") 710 val SCMissBubble = Value("SCMissBubble") 711 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 712 val RASMissBubble = Value("RASMissBubble") 713 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 714 val OtherRedirectBubble = Value("OtherRedirectBubble") 715 val FtqFullStall = Value("FtqFullStall") 716 717 val ICacheMissBubble = Value("ICacheMissBubble") 718 val ITLBMissBubble = Value("ITLBMissBubble") 719 val BTBMissBubble = Value("BTBMissBubble") 720 val FetchFragBubble = Value("FetchFragBubble") 721 722 // backend 723 // long inst stall at rob head 724 val DivStall = Value("DivStall") // int div, float div/sqrt 725 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 726 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 727 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 728 // freelist full 729 val IntFlStall = Value("IntFlStall") 730 val FpFlStall = Value("FpFlStall") 731 // dispatch queue full 732 val IntDqStall = Value("IntDqStall") 733 val FpDqStall = Value("FpDqStall") 734 val LsDqStall = Value("LsDqStall") 735 736 // memblock 737 val LoadTLBStall = Value("LoadTLBStall") 738 val LoadL1Stall = Value("LoadL1Stall") 739 val LoadL2Stall = Value("LoadL2Stall") 740 val LoadL3Stall = Value("LoadL3Stall") 741 val LoadMemStall = Value("LoadMemStall") 742 val StoreStall = Value("StoreStall") // include store tlb miss 743 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 744 745 // xs replay (different to gem5) 746 val LoadVioReplayStall = Value("LoadVioReplayStall") 747 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 748 749 // bad speculation 750 val ControlRecoveryStall = Value("ControlRecoveryStall") 751 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 752 val OtherRecoveryStall = Value("OtherRecoveryStall") 753 754 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 755 756 val OtherCoreStall = Value("OtherCoreStall") 757 758 val NumStallReasons = Value("NumStallReasons") 759 } 760} 761