1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.exu._ 26import xiangshan.backend.{Std, ScheLaneConfig} 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 36 // alias 37 def reg = this.xp 38 def DC = imm // Don't Care 39 def X = BitPat("b???") 40 41 def isPc(srcType: UInt) = srcType===pc 42 def isImm(srcType: UInt) = srcType===imm 43 def isReg(srcType: UInt) = srcType(0) 44 def isFp(srcType: UInt) = srcType(1) 45 def isVp(srcType: UInt) = srcType(2) 46 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 47 48 def apply() = UInt(3.W) 49 } 50 51 object SrcState { 52 def busy = "b0".U 53 def rdy = "b1".U 54 // def specRdy = "b10".U // speculative ready, for future use 55 def apply() = UInt(1.W) 56 } 57 58 // Todo: Use OH instead 59 object FuType { 60 def jmp = "b0000".U 61 def i2f = "b0001".U 62 def csr = "b0010".U 63 def alu = "b0110".U 64 def mul = "b0100".U 65 def div = "b0101".U 66 def fence = "b0011".U 67 def bku = "b0111".U 68 69 def fmac = "b1000".U 70 def fmisc = "b1011".U 71 def fDivSqrt = "b1010".U 72 73 def ldu = "b1100".U 74 def stu = "b1101".U 75 def mou = "b1111".U // for amo, lr, sc, fence 76 def vipu = "b10000".U 77 def vfpu = "b11000".U 78 def vldu = "b11100".U 79 def vstu = "b11101".U 80 def X = BitPat("b????") 81 82 def num = 18 83 84 def apply() = UInt(log2Up(num).W) 85 86 def isIntExu(fuType: UInt) = !fuType(3) 87 def isJumpExu(fuType: UInt) = fuType === jmp 88 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 89 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 90 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 91 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 92 def isAMO(fuType: UInt) = fuType(1) 93 def isFence(fuType: UInt) = fuType === fence 94 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 95 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 96 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 97 98 99 def jmpCanAccept(fuType: UInt) = !fuType(2) 100 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 101 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 102 103 def fmacCanAccept(fuType: UInt) = !fuType(1) 104 def fmiscCanAccept(fuType: UInt) = fuType(1) 105 106 def loadCanAccept(fuType: UInt) = !fuType(0) 107 def storeCanAccept(fuType: UInt) = fuType(0) 108 109 def storeIsAMO(fuType: UInt) = fuType(1) 110 111 val functionNameMap = Map( 112 jmp.litValue() -> "jmp", 113 i2f.litValue() -> "int_to_float", 114 csr.litValue() -> "csr", 115 alu.litValue() -> "alu", 116 mul.litValue() -> "mul", 117 div.litValue() -> "div", 118 fence.litValue() -> "fence", 119 bku.litValue() -> "bku", 120 fmac.litValue() -> "fmac", 121 fmisc.litValue() -> "fmisc", 122 fDivSqrt.litValue() -> "fdiv_fsqrt", 123 ldu.litValue() -> "load", 124 stu.litValue() -> "store", 125 mou.litValue() -> "mou" 126 ) 127 } 128 129 object FuOpType { 130 def apply() = UInt(7.W) 131 def X = BitPat("b???????") 132 } 133 134 object VipuType { 135 def dummy = 0.U(7.W) 136 } 137 138 object VfpuType { 139 def dummy = 0.U(7.W) 140 } 141 142 object VlduType { 143 def dummy = 0.U(7.W) 144 } 145 146 object VstuType { 147 def dummy = 0.U(7.W) 148 } 149 150 object CommitType { 151 def NORMAL = "b000".U // int/fp 152 def BRANCH = "b001".U // branch 153 def LOAD = "b010".U // load 154 def STORE = "b011".U // store 155 156 def apply() = UInt(3.W) 157 def isFused(commitType: UInt): Bool = commitType(2) 158 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 159 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 160 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 161 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 162 } 163 164 object RedirectLevel { 165 def flushAfter = "b0".U 166 def flush = "b1".U 167 168 def apply() = UInt(1.W) 169 // def isUnconditional(level: UInt) = level(1) 170 def flushItself(level: UInt) = level(0) 171 // def isException(level: UInt) = level(1) && level(0) 172 } 173 174 object ExceptionVec { 175 def apply() = Vec(16, Bool()) 176 } 177 178 object PMAMode { 179 def R = "b1".U << 0 //readable 180 def W = "b1".U << 1 //writeable 181 def X = "b1".U << 2 //executable 182 def I = "b1".U << 3 //cacheable: icache 183 def D = "b1".U << 4 //cacheable: dcache 184 def S = "b1".U << 5 //enable speculative access 185 def A = "b1".U << 6 //enable atomic operation, A imply R & W 186 def C = "b1".U << 7 //if it is cacheable is configable 187 def Reserved = "b0".U 188 189 def apply() = UInt(7.W) 190 191 def read(mode: UInt) = mode(0) 192 def write(mode: UInt) = mode(1) 193 def execute(mode: UInt) = mode(2) 194 def icache(mode: UInt) = mode(3) 195 def dcache(mode: UInt) = mode(4) 196 def speculate(mode: UInt) = mode(5) 197 def atomic(mode: UInt) = mode(6) 198 def configable_cache(mode: UInt) = mode(7) 199 200 def strToMode(s: String) = { 201 var result = 0.U(8.W) 202 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 203 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 204 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 205 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 206 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 207 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 208 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 209 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 210 result 211 } 212 } 213 214 215 object CSROpType { 216 def jmp = "b000".U 217 def wrt = "b001".U 218 def set = "b010".U 219 def clr = "b011".U 220 def wfi = "b100".U 221 def wrti = "b101".U 222 def seti = "b110".U 223 def clri = "b111".U 224 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 225 } 226 227 // jump 228 object JumpOpType { 229 def jal = "b00".U 230 def jalr = "b01".U 231 def auipc = "b10".U 232// def call = "b11_011".U 233// def ret = "b11_100".U 234 def jumpOpisJalr(op: UInt) = op(0) 235 def jumpOpisAuipc(op: UInt) = op(1) 236 } 237 238 object FenceOpType { 239 def fence = "b10000".U 240 def sfence = "b10001".U 241 def fencei = "b10010".U 242 def nofence= "b00000".U 243 } 244 245 object ALUOpType { 246 // shift optype 247 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 248 def sll = "b000_0001".U // sll: src1 << src2 249 250 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 251 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 252 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 253 254 def srl = "b000_0101".U // srl: src1 >> src2 255 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 256 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 257 258 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 259 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 260 261 // RV64 32bit optype 262 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 263 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 264 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 265 266 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 267 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 268 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 269 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 270 271 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 272 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 273 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 274 def rolw = "b001_1100".U 275 def rorw = "b001_1101".U 276 277 // ADD-op 278 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 279 def add = "b010_0001".U // add: src1 + src2 280 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 281 282 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 283 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 284 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 285 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 286 287 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 288 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 289 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 290 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 291 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 292 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 293 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 294 295 // SUB-op: src1 - src2 296 def sub = "b011_0000".U 297 def sltu = "b011_0001".U 298 def slt = "b011_0010".U 299 def maxu = "b011_0100".U 300 def minu = "b011_0101".U 301 def max = "b011_0110".U 302 def min = "b011_0111".U 303 304 // branch 305 def beq = "b111_0000".U 306 def bne = "b111_0010".U 307 def blt = "b111_1000".U 308 def bge = "b111_1010".U 309 def bltu = "b111_1100".U 310 def bgeu = "b111_1110".U 311 312 // misc optype 313 def and = "b100_0000".U 314 def andn = "b100_0001".U 315 def or = "b100_0010".U 316 def orn = "b100_0011".U 317 def xor = "b100_0100".U 318 def xnor = "b100_0101".U 319 def orcb = "b100_0110".U 320 321 def sextb = "b100_1000".U 322 def packh = "b100_1001".U 323 def sexth = "b100_1010".U 324 def packw = "b100_1011".U 325 326 def revb = "b101_0000".U 327 def rev8 = "b101_0001".U 328 def pack = "b101_0010".U 329 def orh48 = "b101_0011".U 330 331 def szewl1 = "b101_1000".U 332 def szewl2 = "b101_1001".U 333 def szewl3 = "b101_1010".U 334 def byte2 = "b101_1011".U 335 336 def andlsb = "b110_0000".U 337 def andzexth = "b110_0001".U 338 def orlsb = "b110_0010".U 339 def orzexth = "b110_0011".U 340 def xorlsb = "b110_0100".U 341 def xorzexth = "b110_0101".U 342 def orcblsb = "b110_0110".U 343 def orcbzexth = "b110_0111".U 344 345 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 346 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 347 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 348 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 349 def isBranch(func: UInt) = func(6, 4) === "b111".U 350 def getBranchType(func: UInt) = func(3, 2) 351 def isBranchInvert(func: UInt) = func(1) 352 353 def apply() = UInt(7.W) 354 } 355 356 object MDUOpType { 357 // mul 358 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 359 def mul = "b00000".U 360 def mulh = "b00001".U 361 def mulhsu = "b00010".U 362 def mulhu = "b00011".U 363 def mulw = "b00100".U 364 365 def mulw7 = "b01100".U 366 367 // div 368 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 369 def div = "b10000".U 370 def divu = "b10010".U 371 def rem = "b10001".U 372 def remu = "b10011".U 373 374 def divw = "b10100".U 375 def divuw = "b10110".U 376 def remw = "b10101".U 377 def remuw = "b10111".U 378 379 def isMul(op: UInt) = !op(4) 380 def isDiv(op: UInt) = op(4) 381 382 def isDivSign(op: UInt) = isDiv(op) && !op(1) 383 def isW(op: UInt) = op(2) 384 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 385 def getMulOp(op: UInt) = op(1, 0) 386 } 387 388 object LSUOpType { 389 // load pipeline 390 391 // normal load 392 // Note: bit(1, 0) are size, DO NOT CHANGE 393 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 394 def lb = "b0000".U 395 def lh = "b0001".U 396 def lw = "b0010".U 397 def ld = "b0011".U 398 def lbu = "b0100".U 399 def lhu = "b0101".U 400 def lwu = "b0110".U 401 402 // Zicbop software prefetch 403 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 404 def prefetch_i = "b1000".U // TODO 405 def prefetch_r = "b1001".U 406 def prefetch_w = "b1010".U 407 408 def isPrefetch(op: UInt): Bool = op(3) 409 410 // store pipeline 411 // normal store 412 // bit encoding: | store 00 | size(2bit) | 413 def sb = "b0000".U 414 def sh = "b0001".U 415 def sw = "b0010".U 416 def sd = "b0011".U 417 418 // l1 cache op 419 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 420 def cbo_zero = "b0111".U 421 422 // llc op 423 // bit encoding: | prefetch 11 | suboptype(2bit) | 424 def cbo_clean = "b1100".U 425 def cbo_flush = "b1101".U 426 def cbo_inval = "b1110".U 427 428 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 429 430 // atomics 431 // bit(1, 0) are size 432 // since atomics use a different fu type 433 // so we can safely reuse other load/store's encodings 434 // bit encoding: | optype(4bit) | size (2bit) | 435 def lr_w = "b000010".U 436 def sc_w = "b000110".U 437 def amoswap_w = "b001010".U 438 def amoadd_w = "b001110".U 439 def amoxor_w = "b010010".U 440 def amoand_w = "b010110".U 441 def amoor_w = "b011010".U 442 def amomin_w = "b011110".U 443 def amomax_w = "b100010".U 444 def amominu_w = "b100110".U 445 def amomaxu_w = "b101010".U 446 447 def lr_d = "b000011".U 448 def sc_d = "b000111".U 449 def amoswap_d = "b001011".U 450 def amoadd_d = "b001111".U 451 def amoxor_d = "b010011".U 452 def amoand_d = "b010111".U 453 def amoor_d = "b011011".U 454 def amomin_d = "b011111".U 455 def amomax_d = "b100011".U 456 def amominu_d = "b100111".U 457 def amomaxu_d = "b101011".U 458 459 def size(op: UInt) = op(1,0) 460 } 461 462 object BKUOpType { 463 464 def clmul = "b000000".U 465 def clmulh = "b000001".U 466 def clmulr = "b000010".U 467 def xpermn = "b000100".U 468 def xpermb = "b000101".U 469 470 def clz = "b001000".U 471 def clzw = "b001001".U 472 def ctz = "b001010".U 473 def ctzw = "b001011".U 474 def cpop = "b001100".U 475 def cpopw = "b001101".U 476 477 // 01xxxx is reserve 478 def aes64es = "b100000".U 479 def aes64esm = "b100001".U 480 def aes64ds = "b100010".U 481 def aes64dsm = "b100011".U 482 def aes64im = "b100100".U 483 def aes64ks1i = "b100101".U 484 def aes64ks2 = "b100110".U 485 486 // merge to two instruction sm4ks & sm4ed 487 def sm4ed0 = "b101000".U 488 def sm4ed1 = "b101001".U 489 def sm4ed2 = "b101010".U 490 def sm4ed3 = "b101011".U 491 def sm4ks0 = "b101100".U 492 def sm4ks1 = "b101101".U 493 def sm4ks2 = "b101110".U 494 def sm4ks3 = "b101111".U 495 496 def sha256sum0 = "b110000".U 497 def sha256sum1 = "b110001".U 498 def sha256sig0 = "b110010".U 499 def sha256sig1 = "b110011".U 500 def sha512sum0 = "b110100".U 501 def sha512sum1 = "b110101".U 502 def sha512sig0 = "b110110".U 503 def sha512sig1 = "b110111".U 504 505 def sm3p0 = "b111000".U 506 def sm3p1 = "b111001".U 507 } 508 509 object BTBtype { 510 def B = "b00".U // branch 511 def J = "b01".U // jump 512 def I = "b10".U // indirect 513 def R = "b11".U // return 514 515 def apply() = UInt(2.W) 516 } 517 518 object SelImm { 519 def IMM_X = "b0111".U 520 def IMM_S = "b0000".U 521 def IMM_SB = "b0001".U 522 def IMM_U = "b0010".U 523 def IMM_UJ = "b0011".U 524 def IMM_I = "b0100".U 525 def IMM_Z = "b0101".U 526 def INVALID_INSTR = "b0110".U 527 def IMM_B6 = "b1000".U 528 529 def X = BitPat("b????") 530 531 def apply() = UInt(4.W) 532 } 533 534 object ExceptionNO { 535 def instrAddrMisaligned = 0 536 def instrAccessFault = 1 537 def illegalInstr = 2 538 def breakPoint = 3 539 def loadAddrMisaligned = 4 540 def loadAccessFault = 5 541 def storeAddrMisaligned = 6 542 def storeAccessFault = 7 543 def ecallU = 8 544 def ecallS = 9 545 def ecallM = 11 546 def instrPageFault = 12 547 def loadPageFault = 13 548 // def singleStep = 14 549 def storePageFault = 15 550 def priorities = Seq( 551 breakPoint, // TODO: different BP has different priority 552 instrPageFault, 553 instrAccessFault, 554 illegalInstr, 555 instrAddrMisaligned, 556 ecallM, ecallS, ecallU, 557 storeAddrMisaligned, 558 loadAddrMisaligned, 559 storePageFault, 560 loadPageFault, 561 storeAccessFault, 562 loadAccessFault 563 ) 564 def all = priorities.distinct.sorted 565 def frontendSet = Seq( 566 instrAddrMisaligned, 567 instrAccessFault, 568 illegalInstr, 569 instrPageFault 570 ) 571 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 572 val new_vec = Wire(ExceptionVec()) 573 new_vec.foreach(_ := false.B) 574 select.foreach(i => new_vec(i) := vec(i)) 575 new_vec 576 } 577 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 578 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 579 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 580 partialSelect(vec, fuConfig.exceptionOut) 581 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 582 partialSelect(vec, exuConfig.exceptionOut) 583 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 584 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 585 } 586 587 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 588 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 589 def aluGen(p: Parameters) = new Alu()(p) 590 def bkuGen(p: Parameters) = new Bku()(p) 591 def jmpGen(p: Parameters) = new Jump()(p) 592 def fenceGen(p: Parameters) = new Fence()(p) 593 def csrGen(p: Parameters) = new CSR()(p) 594 def i2fGen(p: Parameters) = new IntToFP()(p) 595 def fmacGen(p: Parameters) = new FMA()(p) 596 def f2iGen(p: Parameters) = new FPToInt()(p) 597 def f2fGen(p: Parameters) = new FPToFP()(p) 598 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 599 def stdGen(p: Parameters) = new Std()(p) 600 def mouDataGen(p: Parameters) = new Std()(p) 601 602 def f2iSel(uop: MicroOp): Bool = { 603 uop.ctrl.rfWen 604 } 605 606 def i2fSel(uop: MicroOp): Bool = { 607 uop.ctrl.fpu.fromInt 608 } 609 610 def f2fSel(uop: MicroOp): Bool = { 611 val ctrl = uop.ctrl.fpu 612 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 613 } 614 615 def fdivSqrtSel(uop: MicroOp): Bool = { 616 val ctrl = uop.ctrl.fpu 617 ctrl.div || ctrl.sqrt 618 } 619 620 val aluCfg = FuConfig( 621 name = "alu", 622 fuGen = aluGen, 623 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 624 fuType = FuType.alu, 625 numIntSrc = 2, 626 numFpSrc = 0, 627 writeIntRf = true, 628 writeFpRf = false, 629 hasRedirect = true, 630 ) 631 632 val jmpCfg = FuConfig( 633 name = "jmp", 634 fuGen = jmpGen, 635 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 636 fuType = FuType.jmp, 637 numIntSrc = 1, 638 numFpSrc = 0, 639 writeIntRf = true, 640 writeFpRf = false, 641 hasRedirect = true, 642 ) 643 644 val fenceCfg = FuConfig( 645 name = "fence", 646 fuGen = fenceGen, 647 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 648 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 649 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 650 flushPipe = true 651 ) 652 653 val csrCfg = FuConfig( 654 name = "csr", 655 fuGen = csrGen, 656 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 657 fuType = FuType.csr, 658 numIntSrc = 1, 659 numFpSrc = 0, 660 writeIntRf = true, 661 writeFpRf = false, 662 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 663 flushPipe = true 664 ) 665 666 val i2fCfg = FuConfig( 667 name = "i2f", 668 fuGen = i2fGen, 669 fuSel = i2fSel, 670 FuType.i2f, 671 numIntSrc = 1, 672 numFpSrc = 0, 673 writeIntRf = false, 674 writeFpRf = true, 675 writeFflags = true, 676 latency = CertainLatency(2), 677 fastUopOut = true, fastImplemented = true 678 ) 679 680 val divCfg = FuConfig( 681 name = "div", 682 fuGen = dividerGen, 683 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 684 FuType.div, 685 2, 686 0, 687 writeIntRf = true, 688 writeFpRf = false, 689 latency = UncertainLatency(), 690 fastUopOut = true, 691 fastImplemented = true, 692 hasInputBuffer = (true, 4, true) 693 ) 694 695 val mulCfg = FuConfig( 696 name = "mul", 697 fuGen = multiplierGen, 698 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 699 FuType.mul, 700 2, 701 0, 702 writeIntRf = true, 703 writeFpRf = false, 704 latency = CertainLatency(2), 705 fastUopOut = true, 706 fastImplemented = true 707 ) 708 709 val bkuCfg = FuConfig( 710 name = "bku", 711 fuGen = bkuGen, 712 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 713 fuType = FuType.bku, 714 numIntSrc = 2, 715 numFpSrc = 0, 716 writeIntRf = true, 717 writeFpRf = false, 718 latency = CertainLatency(1), 719 fastUopOut = true, 720 fastImplemented = true 721 ) 722 723 val fmacCfg = FuConfig( 724 name = "fmac", 725 fuGen = fmacGen, 726 fuSel = _ => true.B, 727 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 728 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 729 ) 730 731 val f2iCfg = FuConfig( 732 name = "f2i", 733 fuGen = f2iGen, 734 fuSel = f2iSel, 735 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 736 fastUopOut = true, fastImplemented = true 737 ) 738 739 val f2fCfg = FuConfig( 740 name = "f2f", 741 fuGen = f2fGen, 742 fuSel = f2fSel, 743 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 744 fastUopOut = true, fastImplemented = true 745 ) 746 747 val fdivSqrtCfg = FuConfig( 748 name = "fdivSqrt", 749 fuGen = fdivSqrtGen, 750 fuSel = fdivSqrtSel, 751 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 752 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 753 ) 754 755 val lduCfg = FuConfig( 756 "ldu", 757 null, // DontCare 758 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 759 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 760 latency = UncertainLatency(), 761 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 762 flushPipe = true, 763 replayInst = true, 764 hasLoadError = true 765 ) 766 767 val staCfg = FuConfig( 768 "sta", 769 null, 770 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 771 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 772 latency = UncertainLatency(), 773 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 774 ) 775 776 val stdCfg = FuConfig( 777 "std", 778 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 779 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 780 ) 781 782 val mouCfg = FuConfig( 783 "mou", 784 null, 785 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 786 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 787 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 788 ) 789 790 val mouDataCfg = FuConfig( 791 "mou", 792 mouDataGen, 793 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 794 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 795 latency = UncertainLatency() 796 ) 797 798 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 799 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 800 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 801 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 802 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 803 val FmiscExeUnitCfg = ExuConfig( 804 "FmiscExeUnit", 805 "Fp", 806 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 807 Int.MaxValue, 1 808 ) 809 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 810 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 811 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 812 813 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 814 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 815 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 816 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 817 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 818 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 819 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 820 821 val aluRSMod = new RSMod( 822 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 823 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 824 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 825 ) 826 val fmaRSMod = new RSMod( 827 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 828 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 829 ) 830 val fmiscRSMod = new RSMod( 831 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 832 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 833 ) 834 val jumpRSMod = new RSMod( 835 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 836 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 837 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 838 ) 839 val loadRSMod = new RSMod( 840 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 841 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 842 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 843 ) 844 val mulRSMod = new RSMod( 845 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 846 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 847 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 848 ) 849 val staRSMod = new RSMod( 850 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 851 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 852 ) 853 val stdRSMod = new RSMod( 854 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 855 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 856 ) 857} 858