1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 def no = "b000".U // this src read no reg but cannot be Any value 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 51 def apply() = UInt(3.W) 52 } 53 54 object SrcState { 55 def busy = "b0".U 56 def rdy = "b1".U 57 // def specRdy = "b10".U // speculative ready, for future use 58 def apply() = UInt(1.W) 59 60 def isReady(state: UInt): Bool = state === this.rdy 61 def isBusy(state: UInt): Bool = state === this.busy 62 } 63 64 def FuOpTypeWidth = 9 65 object FuOpType { 66 def apply() = UInt(FuOpTypeWidth.W) 67 def X = BitPat("b00000000") 68 } 69 70 object VlduType { 71 def dummy = 0.U 72 } 73 74 object VstuType { 75 def dummy = 0.U 76 } 77 78 object CommitType { 79 def NORMAL = "b000".U // int/fp 80 def BRANCH = "b001".U // branch 81 def LOAD = "b010".U // load 82 def STORE = "b011".U // store 83 84 def apply() = UInt(3.W) 85 def isFused(commitType: UInt): Bool = commitType(2) 86 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 87 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 88 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 89 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 90 } 91 92 object RedirectLevel { 93 def flushAfter = "b0".U 94 def flush = "b1".U 95 96 def apply() = UInt(1.W) 97 // def isUnconditional(level: UInt) = level(1) 98 def flushItself(level: UInt) = level(0) 99 // def isException(level: UInt) = level(1) && level(0) 100 } 101 102 object ExceptionVec { 103 val ExceptionVecSize = 16 104 def apply() = Vec(ExceptionVecSize, Bool()) 105 } 106 107 object PMAMode { 108 def R = "b1".U << 0 //readable 109 def W = "b1".U << 1 //writeable 110 def X = "b1".U << 2 //executable 111 def I = "b1".U << 3 //cacheable: icache 112 def D = "b1".U << 4 //cacheable: dcache 113 def S = "b1".U << 5 //enable speculative access 114 def A = "b1".U << 6 //enable atomic operation, A imply R & W 115 def C = "b1".U << 7 //if it is cacheable is configable 116 def Reserved = "b0".U 117 118 def apply() = UInt(7.W) 119 120 def read(mode: UInt) = mode(0) 121 def write(mode: UInt) = mode(1) 122 def execute(mode: UInt) = mode(2) 123 def icache(mode: UInt) = mode(3) 124 def dcache(mode: UInt) = mode(4) 125 def speculate(mode: UInt) = mode(5) 126 def atomic(mode: UInt) = mode(6) 127 def configable_cache(mode: UInt) = mode(7) 128 129 def strToMode(s: String) = { 130 var result = 0.U(8.W) 131 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 132 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 133 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 134 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 135 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 136 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 137 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 138 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 139 result 140 } 141 } 142 143 144 object CSROpType { 145 def jmp = "b000".U 146 def wrt = "b001".U 147 def set = "b010".U 148 def clr = "b011".U 149 def wfi = "b100".U 150 def wrti = "b101".U 151 def seti = "b110".U 152 def clri = "b111".U 153 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 154 } 155 156 // jump 157 object JumpOpType { 158 def jal = "b00".U 159 def jalr = "b01".U 160 def auipc = "b10".U 161// def call = "b11_011".U 162// def ret = "b11_100".U 163 def jumpOpisJalr(op: UInt) = op(0) 164 def jumpOpisAuipc(op: UInt) = op(1) 165 } 166 167 object FenceOpType { 168 def fence = "b10000".U 169 def sfence = "b10001".U 170 def fencei = "b10010".U 171 def nofence= "b00000".U 172 } 173 174 object ALUOpType { 175 // shift optype 176 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 177 def sll = "b000_0001".U // sll: src1 << src2 178 179 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 180 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 181 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 182 183 def srl = "b000_0101".U // srl: src1 >> src2 184 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 185 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 186 187 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 188 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 189 190 // RV64 32bit optype 191 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 192 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 193 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 194 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 195 196 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 197 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 198 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 199 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 200 201 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 202 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 203 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 204 def rolw = "b001_1100".U 205 def rorw = "b001_1101".U 206 207 // ADD-op 208 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 209 def add = "b010_0001".U // add: src1 + src2 210 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 211 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 212 213 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 214 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 215 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 216 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 217 218 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 219 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 220 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 221 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 222 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 223 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 224 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 225 226 // SUB-op: src1 - src2 227 def sub = "b011_0000".U 228 def sltu = "b011_0001".U 229 def slt = "b011_0010".U 230 def maxu = "b011_0100".U 231 def minu = "b011_0101".U 232 def max = "b011_0110".U 233 def min = "b011_0111".U 234 235 // branch 236 def beq = "b111_0000".U 237 def bne = "b111_0010".U 238 def blt = "b111_1000".U 239 def bge = "b111_1010".U 240 def bltu = "b111_1100".U 241 def bgeu = "b111_1110".U 242 243 // misc optype 244 def and = "b100_0000".U 245 def andn = "b100_0001".U 246 def or = "b100_0010".U 247 def orn = "b100_0011".U 248 def xor = "b100_0100".U 249 def xnor = "b100_0101".U 250 def orcb = "b100_0110".U 251 252 def sextb = "b100_1000".U 253 def packh = "b100_1001".U 254 def sexth = "b100_1010".U 255 def packw = "b100_1011".U 256 257 def revb = "b101_0000".U 258 def rev8 = "b101_0001".U 259 def pack = "b101_0010".U 260 def orh48 = "b101_0011".U 261 262 def szewl1 = "b101_1000".U 263 def szewl2 = "b101_1001".U 264 def szewl3 = "b101_1010".U 265 def byte2 = "b101_1011".U 266 267 def andlsb = "b110_0000".U 268 def andzexth = "b110_0001".U 269 def orlsb = "b110_0010".U 270 def orzexth = "b110_0011".U 271 def xorlsb = "b110_0100".U 272 def xorzexth = "b110_0101".U 273 def orcblsb = "b110_0110".U 274 def orcbzexth = "b110_0111".U 275 276 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 277 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 278 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 279 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 280 281 def apply() = UInt(FuOpTypeWidth.W) 282 } 283 284 object VSETOpType { 285 val setVlmaxBit = 0 286 val keepVlBit = 1 287 // destTypeBit == 0: write vl to rd 288 // destTypeBit == 1: write vconfig 289 val destTypeBit = 5 290 291 // vsetvli's uop 292 // rs1!=x0, normal 293 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 294 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 295 def uvsetvcfg_xi = "b1010_0000".U 296 def uvsetrd_xi = "b1000_0000".U 297 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 298 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 299 // uop1: w(rd) | vlmax, vtypei -> x[rd] 300 def uvsetvcfg_vlmax_i = "b1010_0001".U 301 def uvsetrd_vlmax_i = "b1000_0001".U 302 // rs1==x0, rd==x0, keep vl, set vtype 303 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 304 def uvsetvcfg_keep_v = "b1010_0010".U 305 306 // vsetvl's uop 307 // rs1!=x0, normal 308 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 309 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 310 def uvsetvcfg_xx = "b0110_0000".U 311 def uvsetrd_xx = "b0100_0000".U 312 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 313 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 314 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 315 def uvsetvcfg_vlmax_x = "b0110_0001".U 316 def uvsetrd_vlmax_x = "b0100_0001".U 317 // rs1==x0, rd==x0, keep vl, set vtype 318 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 319 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 320 def uvmv_v_x = "b0110_0010".U 321 def uvsetvcfg_vv = "b0111_0010".U 322 323 // vsetivli's uop 324 // uop0: w(vconfig) | vli, vtypei -> vconfig 325 // uop1: w(rd) | vli, vtypei -> x[rd] 326 def uvsetvcfg_ii = "b0010_0000".U 327 def uvsetrd_ii = "b0000_0000".U 328 329 def isVsetvl (func: UInt) = func(6) 330 def isVsetvli (func: UInt) = func(7) 331 def isVsetivli(func: UInt) = func(7, 6) === 0.U 332 def isNormal (func: UInt) = func(1, 0) === 0.U 333 def isSetVlmax(func: UInt) = func(setVlmaxBit) 334 def isKeepVl (func: UInt) = func(keepVlBit) 335 // RG: region 336 def writeIntRG(func: UInt) = !func(5) 337 def writeVecRG(func: UInt) = func(5) 338 def readIntRG (func: UInt) = !func(4) 339 def readVecRG (func: UInt) = func(4) 340 // modify fuOpType 341 def switchDest(func: UInt) = func ^ (1 << destTypeBit).U 342 def keepVl(func: UInt) = func | (1 << keepVlBit).U 343 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 344 } 345 346 object BRUOpType { 347 // branch 348 def beq = "b000_000".U 349 def bne = "b000_001".U 350 def blt = "b000_100".U 351 def bge = "b000_101".U 352 def bltu = "b001_000".U 353 def bgeu = "b001_001".U 354 355 def getBranchType(func: UInt) = func(3, 1) 356 def isBranchInvert(func: UInt) = func(0) 357 } 358 359 object MULOpType { 360 // mul 361 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 362 def mul = "b00000".U 363 def mulh = "b00001".U 364 def mulhsu = "b00010".U 365 def mulhu = "b00011".U 366 def mulw = "b00100".U 367 368 def mulw7 = "b01100".U 369 def isSign(op: UInt) = !op(1) 370 def isW(op: UInt) = op(2) 371 def isH(op: UInt) = op(1, 0) =/= 0.U 372 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 373 } 374 375 object DIVOpType { 376 // div 377 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 378 def div = "b10000".U 379 def divu = "b10010".U 380 def rem = "b10001".U 381 def remu = "b10011".U 382 383 def divw = "b10100".U 384 def divuw = "b10110".U 385 def remw = "b10101".U 386 def remuw = "b10111".U 387 388 def isSign(op: UInt) = !op(1) 389 def isW(op: UInt) = op(2) 390 def isH(op: UInt) = op(0) 391 } 392 393 object MDUOpType { 394 // mul 395 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 396 def mul = "b00000".U 397 def mulh = "b00001".U 398 def mulhsu = "b00010".U 399 def mulhu = "b00011".U 400 def mulw = "b00100".U 401 402 def mulw7 = "b01100".U 403 404 // div 405 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 406 def div = "b10000".U 407 def divu = "b10010".U 408 def rem = "b10001".U 409 def remu = "b10011".U 410 411 def divw = "b10100".U 412 def divuw = "b10110".U 413 def remw = "b10101".U 414 def remuw = "b10111".U 415 416 def isMul(op: UInt) = !op(4) 417 def isDiv(op: UInt) = op(4) 418 419 def isDivSign(op: UInt) = isDiv(op) && !op(1) 420 def isW(op: UInt) = op(2) 421 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 422 def getMulOp(op: UInt) = op(1, 0) 423 } 424 425 object LSUOpType { 426 // load pipeline 427 428 // normal load 429 // Note: bit(1, 0) are size, DO NOT CHANGE 430 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 431 def lb = "b0000".U 432 def lh = "b0001".U 433 def lw = "b0010".U 434 def ld = "b0011".U 435 def lbu = "b0100".U 436 def lhu = "b0101".U 437 def lwu = "b0110".U 438 439 // Zicbop software prefetch 440 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 441 def prefetch_i = "b1000".U // TODO 442 def prefetch_r = "b1001".U 443 def prefetch_w = "b1010".U 444 445 def isPrefetch(op: UInt): Bool = op(3) 446 447 // store pipeline 448 // normal store 449 // bit encoding: | store 00 | size(2bit) | 450 def sb = "b0000".U 451 def sh = "b0001".U 452 def sw = "b0010".U 453 def sd = "b0011".U 454 455 // l1 cache op 456 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 457 def cbo_zero = "b0111".U 458 459 // llc op 460 // bit encoding: | prefetch 11 | suboptype(2bit) | 461 def cbo_clean = "b1100".U 462 def cbo_flush = "b1101".U 463 def cbo_inval = "b1110".U 464 465 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 466 467 // atomics 468 // bit(1, 0) are size 469 // since atomics use a different fu type 470 // so we can safely reuse other load/store's encodings 471 // bit encoding: | optype(4bit) | size (2bit) | 472 def lr_w = "b000010".U 473 def sc_w = "b000110".U 474 def amoswap_w = "b001010".U 475 def amoadd_w = "b001110".U 476 def amoxor_w = "b010010".U 477 def amoand_w = "b010110".U 478 def amoor_w = "b011010".U 479 def amomin_w = "b011110".U 480 def amomax_w = "b100010".U 481 def amominu_w = "b100110".U 482 def amomaxu_w = "b101010".U 483 484 def lr_d = "b000011".U 485 def sc_d = "b000111".U 486 def amoswap_d = "b001011".U 487 def amoadd_d = "b001111".U 488 def amoxor_d = "b010011".U 489 def amoand_d = "b010111".U 490 def amoor_d = "b011011".U 491 def amomin_d = "b011111".U 492 def amomax_d = "b100011".U 493 def amominu_d = "b100111".U 494 def amomaxu_d = "b101011".U 495 496 def size(op: UInt) = op(1,0) 497 } 498 499 object BKUOpType { 500 501 def clmul = "b000000".U 502 def clmulh = "b000001".U 503 def clmulr = "b000010".U 504 def xpermn = "b000100".U 505 def xpermb = "b000101".U 506 507 def clz = "b001000".U 508 def clzw = "b001001".U 509 def ctz = "b001010".U 510 def ctzw = "b001011".U 511 def cpop = "b001100".U 512 def cpopw = "b001101".U 513 514 // 01xxxx is reserve 515 def aes64es = "b100000".U 516 def aes64esm = "b100001".U 517 def aes64ds = "b100010".U 518 def aes64dsm = "b100011".U 519 def aes64im = "b100100".U 520 def aes64ks1i = "b100101".U 521 def aes64ks2 = "b100110".U 522 523 // merge to two instruction sm4ks & sm4ed 524 def sm4ed0 = "b101000".U 525 def sm4ed1 = "b101001".U 526 def sm4ed2 = "b101010".U 527 def sm4ed3 = "b101011".U 528 def sm4ks0 = "b101100".U 529 def sm4ks1 = "b101101".U 530 def sm4ks2 = "b101110".U 531 def sm4ks3 = "b101111".U 532 533 def sha256sum0 = "b110000".U 534 def sha256sum1 = "b110001".U 535 def sha256sig0 = "b110010".U 536 def sha256sig1 = "b110011".U 537 def sha512sum0 = "b110100".U 538 def sha512sum1 = "b110101".U 539 def sha512sig0 = "b110110".U 540 def sha512sig1 = "b110111".U 541 542 def sm3p0 = "b111000".U 543 def sm3p1 = "b111001".U 544 } 545 546 object BTBtype { 547 def B = "b00".U // branch 548 def J = "b01".U // jump 549 def I = "b10".U // indirect 550 def R = "b11".U // return 551 552 def apply() = UInt(2.W) 553 } 554 555 object SelImm { 556 def IMM_X = "b0111".U 557 def IMM_S = "b1110".U 558 def IMM_SB = "b0001".U 559 def IMM_U = "b0010".U 560 def IMM_UJ = "b0011".U 561 def IMM_I = "b0100".U 562 def IMM_Z = "b0101".U 563 def INVALID_INSTR = "b0110".U 564 def IMM_B6 = "b1000".U 565 566 def IMM_OPIVIS = "b1001".U 567 def IMM_OPIVIU = "b1010".U 568 def IMM_VSETVLI = "b1100".U 569 def IMM_VSETIVLI = "b1101".U 570 def IMM_LUI32 = "b1011".U 571 572 def X = BitPat("b0000") 573 574 def apply() = UInt(4.W) 575 576 def mkString(immType: UInt) : String = { 577 val strMap = Map( 578 IMM_S.litValue -> "S", 579 IMM_SB.litValue -> "SB", 580 IMM_U.litValue -> "U", 581 IMM_UJ.litValue -> "UJ", 582 IMM_I.litValue -> "I", 583 IMM_Z.litValue -> "Z", 584 IMM_B6.litValue -> "B6", 585 IMM_OPIVIS.litValue -> "VIS", 586 IMM_OPIVIU.litValue -> "VIU", 587 IMM_VSETVLI.litValue -> "VSETVLI", 588 IMM_VSETIVLI.litValue -> "VSETIVLI", 589 IMM_LUI32.litValue -> "LUI32", 590 INVALID_INSTR.litValue -> "INVALID", 591 ) 592 strMap(immType.litValue) 593 } 594 } 595 596 object UopSplitType { 597 def SCA_SIM = "b000000".U // 598 def DIR = "b010001".U // dirty: vset 599 def VEC_VVV = "b010010".U // VEC_VVV 600 def VEC_VXV = "b010011".U // VEC_VXV 601 def VEC_0XV = "b010100".U // VEC_0XV 602 def VEC_VVW = "b010101".U // VEC_VVW 603 def VEC_WVW = "b010110".U // VEC_WVW 604 def VEC_VXW = "b010111".U // VEC_VXW 605 def VEC_WXW = "b011000".U // VEC_WXW 606 def VEC_WVV = "b011001".U // VEC_WVV 607 def VEC_WXV = "b011010".U // VEC_WXV 608 def VEC_EXT2 = "b011011".U // VF2 0 -> V 609 def VEC_EXT4 = "b011100".U // VF4 0 -> V 610 def VEC_EXT8 = "b011101".U // VF8 0 -> V 611 def VEC_VVM = "b011110".U // VEC_VVM 612 def VEC_VXM = "b011111".U // VEC_VXM 613 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 614 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 615 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 616 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 617 def VEC_VRED = "b100100".U // VEC_VRED 618 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 619 def VEC_ISLIDEUP = "b100110".U // VEC_ISLIDEUP 620 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 621 def VEC_ISLIDEDOWN = "b101000".U // VEC_ISLIDEDOWN 622 def VEC_M0X = "b101001".U // VEC_M0X 0MV 623 def VEC_MVV = "b101010".U // VEC_MVV VMV 624 def VEC_M0X_VFIRST = "b101011".U // 625 def VEC_VWW = "b101100".U // 626 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 627 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 628 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 629 def VEC_COMPRESS = "b110000".U // vcompress.vm 630 def VEC_US_LD = "b110001".U // vector unit strided load 631 def VEC_VFV = "b111000".U // VEC_VFV 632 def VEC_VFW = "b111001".U // VEC_VFW 633 def VEC_WFW = "b111010".U // VEC_WVW 634 def VEC_VFM = "b111011".U // VEC_VFM 635 def VEC_VFRED = "b111100".U // VEC_VFRED 636 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 637 def VEC_M0M = "b000000".U // VEC_M0M 638 def VEC_MMM = "b000000".U // VEC_MMM 639 def dummy = "b111111".U 640 641 def X = BitPat("b000000") 642 643 def apply() = UInt(6.W) 644 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 645 } 646 647 object ExceptionNO { 648 def instrAddrMisaligned = 0 649 def instrAccessFault = 1 650 def illegalInstr = 2 651 def breakPoint = 3 652 def loadAddrMisaligned = 4 653 def loadAccessFault = 5 654 def storeAddrMisaligned = 6 655 def storeAccessFault = 7 656 def ecallU = 8 657 def ecallS = 9 658 def ecallM = 11 659 def instrPageFault = 12 660 def loadPageFault = 13 661 // def singleStep = 14 662 def storePageFault = 15 663 def priorities = Seq( 664 breakPoint, // TODO: different BP has different priority 665 instrPageFault, 666 instrAccessFault, 667 illegalInstr, 668 instrAddrMisaligned, 669 ecallM, ecallS, ecallU, 670 storeAddrMisaligned, 671 loadAddrMisaligned, 672 storePageFault, 673 loadPageFault, 674 storeAccessFault, 675 loadAccessFault 676 ) 677 def all = priorities.distinct.sorted 678 def frontendSet = Seq( 679 instrAddrMisaligned, 680 instrAccessFault, 681 illegalInstr, 682 instrPageFault 683 ) 684 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 685 val new_vec = Wire(ExceptionVec()) 686 new_vec.foreach(_ := false.B) 687 select.foreach(i => new_vec(i) := vec(i)) 688 new_vec 689 } 690 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 691 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 692 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 693 partialSelect(vec, fuConfig.exceptionOut) 694 } 695 696 object TopDownCounters extends Enumeration { 697 val NoStall = Value("NoStall") // Base 698 // frontend 699 val OverrideBubble = Value("OverrideBubble") 700 val FtqUpdateBubble = Value("FtqUpdateBubble") 701 // val ControlRedirectBubble = Value("ControlRedirectBubble") 702 val TAGEMissBubble = Value("TAGEMissBubble") 703 val SCMissBubble = Value("SCMissBubble") 704 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 705 val RASMissBubble = Value("RASMissBubble") 706 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 707 val OtherRedirectBubble = Value("OtherRedirectBubble") 708 val FtqFullStall = Value("FtqFullStall") 709 710 val ICacheMissBubble = Value("ICacheMissBubble") 711 val ITLBMissBubble = Value("ITLBMissBubble") 712 val BTBMissBubble = Value("BTBMissBubble") 713 val FetchFragBubble = Value("FetchFragBubble") 714 715 // backend 716 // long inst stall at rob head 717 val DivStall = Value("DivStall") // int div, float div/sqrt 718 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 719 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 720 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 721 // freelist full 722 val IntFlStall = Value("IntFlStall") 723 val FpFlStall = Value("FpFlStall") 724 // dispatch queue full 725 val IntDqStall = Value("IntDqStall") 726 val FpDqStall = Value("FpDqStall") 727 val LsDqStall = Value("LsDqStall") 728 729 // memblock 730 val LoadTLBStall = Value("LoadTLBStall") 731 val LoadL1Stall = Value("LoadL1Stall") 732 val LoadL2Stall = Value("LoadL2Stall") 733 val LoadL3Stall = Value("LoadL3Stall") 734 val LoadMemStall = Value("LoadMemStall") 735 val StoreStall = Value("StoreStall") // include store tlb miss 736 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 737 738 // xs replay (different to gem5) 739 val LoadVioReplayStall = Value("LoadVioReplayStall") 740 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 741 742 // bad speculation 743 val ControlRecoveryStall = Value("ControlRecoveryStall") 744 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 745 val OtherRecoveryStall = Value("OtherRecoveryStall") 746 747 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 748 749 val OtherCoreStall = Value("OtherCoreStall") 750 751 val NumStallReasons = Value("NumStallReasons") 752 } 753} 754