1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType(1) 40 def isPcOrImm(srcType: UInt) = srcType(0) 41 def isRegOrFp(srcType: UInt) = !srcType(0) 42 def regIsFp(srcType: UInt) = srcType(1) 43 44 def apply() = UInt(2.W) 45 } 46 47 object SrcState { 48 def busy = "b0".U 49 def rdy = "b1".U 50 // def specRdy = "b10".U // speculative ready, for future use 51 def apply() = UInt(1.W) 52 } 53 54 object FuType { 55 def jmp = "b0000".U 56 def i2f = "b0001".U 57 def csr = "b0010".U 58 def alu = "b0110".U 59 def mul = "b0100".U 60 def div = "b0101".U 61 def fence = "b0011".U 62 def bku = "b0111".U 63 64 def fmac = "b1000".U 65 def fmisc = "b1011".U 66 def fDivSqrt = "b1010".U 67 68 def ldu = "b1100".U 69 def stu = "b1101".U 70 def mou = "b1111".U // for amo, lr, sc, fence 71 72 def num = 14 73 74 def apply() = UInt(log2Up(num).W) 75 76 def isIntExu(fuType: UInt) = !fuType(3) 77 def isJumpExu(fuType: UInt) = fuType === jmp 78 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 79 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 80 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 81 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 82 def isAMO(fuType: UInt) = fuType(1) 83 def isFence(fuType: UInt) = fuType === fence 84 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 85 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 86 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 87 88 89 def jmpCanAccept(fuType: UInt) = !fuType(2) 90 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 91 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 92 93 def fmacCanAccept(fuType: UInt) = !fuType(1) 94 def fmiscCanAccept(fuType: UInt) = fuType(1) 95 96 def loadCanAccept(fuType: UInt) = !fuType(0) 97 def storeCanAccept(fuType: UInt) = fuType(0) 98 99 def storeIsAMO(fuType: UInt) = fuType(1) 100 101 val functionNameMap = Map( 102 jmp.litValue() -> "jmp", 103 i2f.litValue() -> "int_to_float", 104 csr.litValue() -> "csr", 105 alu.litValue() -> "alu", 106 mul.litValue() -> "mul", 107 div.litValue() -> "div", 108 fence.litValue() -> "fence", 109 bku.litValue() -> "bku", 110 fmac.litValue() -> "fmac", 111 fmisc.litValue() -> "fmisc", 112 fDivSqrt.litValue() -> "fdiv/fsqrt", 113 ldu.litValue() -> "load", 114 stu.litValue() -> "store", 115 mou.litValue() -> "mou" 116 ) 117 } 118 119 object FuOpType { 120 def apply() = UInt(7.W) 121 } 122 123 object CommitType { 124 def NORMAL = "b000".U // int/fp 125 def BRANCH = "b001".U // branch 126 def LOAD = "b010".U // load 127 def STORE = "b011".U // store 128 129 def apply() = UInt(3.W) 130 def isFused(commitType: UInt): Bool = commitType(2) 131 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 132 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 133 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 134 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 135 } 136 137 object RedirectLevel { 138 def flushAfter = "b0".U 139 def flush = "b1".U 140 141 def apply() = UInt(1.W) 142 // def isUnconditional(level: UInt) = level(1) 143 def flushItself(level: UInt) = level(0) 144 // def isException(level: UInt) = level(1) && level(0) 145 } 146 147 object ExceptionVec { 148 def apply() = Vec(16, Bool()) 149 } 150 151 object PMAMode { 152 def R = "b1".U << 0 //readable 153 def W = "b1".U << 1 //writeable 154 def X = "b1".U << 2 //executable 155 def I = "b1".U << 3 //cacheable: icache 156 def D = "b1".U << 4 //cacheable: dcache 157 def S = "b1".U << 5 //enable speculative access 158 def A = "b1".U << 6 //enable atomic operation, A imply R & W 159 def C = "b1".U << 7 //if it is cacheable is configable 160 def Reserved = "b0".U 161 162 def apply() = UInt(7.W) 163 164 def read(mode: UInt) = mode(0) 165 def write(mode: UInt) = mode(1) 166 def execute(mode: UInt) = mode(2) 167 def icache(mode: UInt) = mode(3) 168 def dcache(mode: UInt) = mode(4) 169 def speculate(mode: UInt) = mode(5) 170 def atomic(mode: UInt) = mode(6) 171 def configable_cache(mode: UInt) = mode(7) 172 173 def strToMode(s: String) = { 174 var result = 0.U(8.W) 175 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 176 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 177 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 178 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 179 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 180 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 181 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 182 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 183 result 184 } 185 } 186 187 188 object CSROpType { 189 def jmp = "b000".U 190 def wrt = "b001".U 191 def set = "b010".U 192 def clr = "b011".U 193 def wfi = "b100".U 194 def wrti = "b101".U 195 def seti = "b110".U 196 def clri = "b111".U 197 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 198 } 199 200 // jump 201 object JumpOpType { 202 def jal = "b00".U 203 def jalr = "b01".U 204 def auipc = "b10".U 205// def call = "b11_011".U 206// def ret = "b11_100".U 207 def jumpOpisJalr(op: UInt) = op(0) 208 def jumpOpisAuipc(op: UInt) = op(1) 209 } 210 211 object FenceOpType { 212 def fence = "b10000".U 213 def sfence = "b10001".U 214 def fencei = "b10010".U 215 def nofence= "b00000".U 216 } 217 218 object ALUOpType { 219 // shift optype 220 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 221 def sll = "b000_0001".U // sll: src1 << src2 222 223 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 224 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 225 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 226 227 def srl = "b000_0101".U // srl: src1 >> src2 228 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 229 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 230 231 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 232 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 233 234 // RV64 32bit optype 235 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 236 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 237 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 238 239 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 240 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 241 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 242 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 243 244 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 245 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 246 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 247 def rolw = "b001_1100".U 248 def rorw = "b001_1101".U 249 250 // ADD-op 251 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 252 def add = "b010_0001".U // add: src1 + src2 253 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 254 255 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 256 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 257 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 258 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 259 260 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 261 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 262 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 263 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 264 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 265 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 266 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 267 268 // SUB-op: src1 - src2 269 def sub = "b011_0000".U 270 def sltu = "b011_0001".U 271 def slt = "b011_0010".U 272 def maxu = "b011_0100".U 273 def minu = "b011_0101".U 274 def max = "b011_0110".U 275 def min = "b011_0111".U 276 277 // branch 278 def beq = "b111_0000".U 279 def bne = "b111_0010".U 280 def blt = "b111_1000".U 281 def bge = "b111_1010".U 282 def bltu = "b111_1100".U 283 def bgeu = "b111_1110".U 284 285 // misc optype 286 def and = "b100_0000".U 287 def andn = "b100_0001".U 288 def or = "b100_0010".U 289 def orn = "b100_0011".U 290 def xor = "b100_0100".U 291 def xnor = "b100_0101".U 292 def orcb = "b100_0110".U 293 294 def sextb = "b100_1000".U 295 def packh = "b100_1001".U 296 def sexth = "b100_1010".U 297 def packw = "b100_1011".U 298 299 def revb = "b101_0000".U 300 def rev8 = "b101_0001".U 301 def pack = "b101_0010".U 302 def orh48 = "b101_0011".U 303 304 def szewl1 = "b101_1000".U 305 def szewl2 = "b101_1001".U 306 def szewl3 = "b101_1010".U 307 def byte2 = "b101_1011".U 308 309 def andlsb = "b110_0000".U 310 def andzexth = "b110_0001".U 311 def orlsb = "b110_0010".U 312 def orzexth = "b110_0011".U 313 def xorlsb = "b110_0100".U 314 def xorzexth = "b110_0101".U 315 def orcblsb = "b110_0110".U 316 def orcbzexth = "b110_0111".U 317 318 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 319 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 320 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 321 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 322 def isBranch(func: UInt) = func(6, 4) === "b111".U 323 def getBranchType(func: UInt) = func(3, 2) 324 def isBranchInvert(func: UInt) = func(1) 325 326 def apply() = UInt(7.W) 327 } 328 329 object MDUOpType { 330 // mul 331 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 332 def mul = "b00000".U 333 def mulh = "b00001".U 334 def mulhsu = "b00010".U 335 def mulhu = "b00011".U 336 def mulw = "b00100".U 337 338 def mulw7 = "b01100".U 339 340 // div 341 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 342 def div = "b10000".U 343 def divu = "b10010".U 344 def rem = "b10001".U 345 def remu = "b10011".U 346 347 def divw = "b10100".U 348 def divuw = "b10110".U 349 def remw = "b10101".U 350 def remuw = "b10111".U 351 352 def isMul(op: UInt) = !op(4) 353 def isDiv(op: UInt) = op(4) 354 355 def isDivSign(op: UInt) = isDiv(op) && !op(1) 356 def isW(op: UInt) = op(2) 357 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 358 def getMulOp(op: UInt) = op(1, 0) 359 } 360 361 object LSUOpType { 362 // load pipeline 363 364 // normal load 365 // Note: bit(1, 0) are size, DO NOT CHANGE 366 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 367 def lb = "b0000".U 368 def lh = "b0001".U 369 def lw = "b0010".U 370 def ld = "b0011".U 371 def lbu = "b0100".U 372 def lhu = "b0101".U 373 def lwu = "b0110".U 374 375 // Zicbop software prefetch 376 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 377 def prefetch_i = "b1000".U // TODO 378 def prefetch_r = "b1001".U 379 def prefetch_w = "b1010".U 380 381 def isPrefetch(op: UInt): Bool = op(3) 382 383 // store pipeline 384 // normal store 385 // bit encoding: | store 00 | size(2bit) | 386 def sb = "b0000".U 387 def sh = "b0001".U 388 def sw = "b0010".U 389 def sd = "b0011".U 390 391 // l1 cache op 392 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 393 def cbo_zero = "b0111".U 394 395 // llc op 396 // bit encoding: | prefetch 11 | suboptype(2bit) | 397 def cbo_clean = "b1100".U 398 def cbo_flush = "b1101".U 399 def cbo_inval = "b1110".U 400 401 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 402 403 // atomics 404 // bit(1, 0) are size 405 // since atomics use a different fu type 406 // so we can safely reuse other load/store's encodings 407 // bit encoding: | optype(4bit) | size (2bit) | 408 def lr_w = "b000010".U 409 def sc_w = "b000110".U 410 def amoswap_w = "b001010".U 411 def amoadd_w = "b001110".U 412 def amoxor_w = "b010010".U 413 def amoand_w = "b010110".U 414 def amoor_w = "b011010".U 415 def amomin_w = "b011110".U 416 def amomax_w = "b100010".U 417 def amominu_w = "b100110".U 418 def amomaxu_w = "b101010".U 419 420 def lr_d = "b000011".U 421 def sc_d = "b000111".U 422 def amoswap_d = "b001011".U 423 def amoadd_d = "b001111".U 424 def amoxor_d = "b010011".U 425 def amoand_d = "b010111".U 426 def amoor_d = "b011011".U 427 def amomin_d = "b011111".U 428 def amomax_d = "b100011".U 429 def amominu_d = "b100111".U 430 def amomaxu_d = "b101011".U 431 432 def size(op: UInt) = op(1,0) 433 } 434 435 object BKUOpType { 436 437 def clmul = "b000000".U 438 def clmulh = "b000001".U 439 def clmulr = "b000010".U 440 def xpermn = "b000100".U 441 def xpermb = "b000101".U 442 443 def clz = "b001000".U 444 def clzw = "b001001".U 445 def ctz = "b001010".U 446 def ctzw = "b001011".U 447 def cpop = "b001100".U 448 def cpopw = "b001101".U 449 450 // 01xxxx is reserve 451 def aes64es = "b100000".U 452 def aes64esm = "b100001".U 453 def aes64ds = "b100010".U 454 def aes64dsm = "b100011".U 455 def aes64im = "b100100".U 456 def aes64ks1i = "b100101".U 457 def aes64ks2 = "b100110".U 458 459 // merge to two instruction sm4ks & sm4ed 460 def sm4ed0 = "b101000".U 461 def sm4ed1 = "b101001".U 462 def sm4ed2 = "b101010".U 463 def sm4ed3 = "b101011".U 464 def sm4ks0 = "b101100".U 465 def sm4ks1 = "b101101".U 466 def sm4ks2 = "b101110".U 467 def sm4ks3 = "b101111".U 468 469 def sha256sum0 = "b110000".U 470 def sha256sum1 = "b110001".U 471 def sha256sig0 = "b110010".U 472 def sha256sig1 = "b110011".U 473 def sha512sum0 = "b110100".U 474 def sha512sum1 = "b110101".U 475 def sha512sig0 = "b110110".U 476 def sha512sig1 = "b110111".U 477 478 def sm3p0 = "b111000".U 479 def sm3p1 = "b111001".U 480 } 481 482 object BTBtype { 483 def B = "b00".U // branch 484 def J = "b01".U // jump 485 def I = "b10".U // indirect 486 def R = "b11".U // return 487 488 def apply() = UInt(2.W) 489 } 490 491 object SelImm { 492 def IMM_X = "b0111".U 493 def IMM_S = "b0000".U 494 def IMM_SB = "b0001".U 495 def IMM_U = "b0010".U 496 def IMM_UJ = "b0011".U 497 def IMM_I = "b0100".U 498 def IMM_Z = "b0101".U 499 def INVALID_INSTR = "b0110".U 500 def IMM_B6 = "b1000".U 501 502 def apply() = UInt(4.W) 503 } 504 505 object ExceptionNO { 506 def instrAddrMisaligned = 0 507 def instrAccessFault = 1 508 def illegalInstr = 2 509 def breakPoint = 3 510 def loadAddrMisaligned = 4 511 def loadAccessFault = 5 512 def storeAddrMisaligned = 6 513 def storeAccessFault = 7 514 def ecallU = 8 515 def ecallS = 9 516 def ecallM = 11 517 def instrPageFault = 12 518 def loadPageFault = 13 519 // def singleStep = 14 520 def storePageFault = 15 521 def priorities = Seq( 522 breakPoint, // TODO: different BP has different priority 523 instrPageFault, 524 instrAccessFault, 525 illegalInstr, 526 instrAddrMisaligned, 527 ecallM, ecallS, ecallU, 528 storePageFault, 529 loadPageFault, 530 storeAccessFault, 531 loadAccessFault, 532 storeAddrMisaligned, 533 loadAddrMisaligned 534 ) 535 def all = priorities.distinct.sorted 536 def frontendSet = Seq( 537 instrAddrMisaligned, 538 instrAccessFault, 539 illegalInstr, 540 instrPageFault 541 ) 542 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 543 val new_vec = Wire(ExceptionVec()) 544 new_vec.foreach(_ := false.B) 545 select.foreach(i => new_vec(i) := vec(i)) 546 new_vec 547 } 548 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 549 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 550 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 551 partialSelect(vec, fuConfig.exceptionOut) 552 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 553 partialSelect(vec, exuConfig.exceptionOut) 554 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 555 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 556 } 557 558 def dividerGen(p: Parameters) = new SRT16Divider(p(XLen))(p) 559 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 560 def aluGen(p: Parameters) = new Alu()(p) 561 def bkuGen(p: Parameters) = new Bku()(p) 562 def jmpGen(p: Parameters) = new Jump()(p) 563 def fenceGen(p: Parameters) = new Fence()(p) 564 def csrGen(p: Parameters) = new CSR()(p) 565 def i2fGen(p: Parameters) = new IntToFP()(p) 566 def fmacGen(p: Parameters) = new FMA()(p) 567 def f2iGen(p: Parameters) = new FPToInt()(p) 568 def f2fGen(p: Parameters) = new FPToFP()(p) 569 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 570 def stdGen(p: Parameters) = new Std()(p) 571 def mouDataGen(p: Parameters) = new Std()(p) 572 573 def f2iSel(uop: MicroOp): Bool = { 574 uop.ctrl.rfWen 575 } 576 577 def i2fSel(uop: MicroOp): Bool = { 578 uop.ctrl.fpu.fromInt 579 } 580 581 def f2fSel(uop: MicroOp): Bool = { 582 val ctrl = uop.ctrl.fpu 583 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 584 } 585 586 def fdivSqrtSel(uop: MicroOp): Bool = { 587 val ctrl = uop.ctrl.fpu 588 ctrl.div || ctrl.sqrt 589 } 590 591 val aluCfg = FuConfig( 592 name = "alu", 593 fuGen = aluGen, 594 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 595 fuType = FuType.alu, 596 numIntSrc = 2, 597 numFpSrc = 0, 598 writeIntRf = true, 599 writeFpRf = false, 600 hasRedirect = true, 601 ) 602 603 val jmpCfg = FuConfig( 604 name = "jmp", 605 fuGen = jmpGen, 606 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 607 fuType = FuType.jmp, 608 numIntSrc = 1, 609 numFpSrc = 0, 610 writeIntRf = true, 611 writeFpRf = false, 612 hasRedirect = true, 613 ) 614 615 val fenceCfg = FuConfig( 616 name = "fence", 617 fuGen = fenceGen, 618 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 619 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 620 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr) // TODO: need rewrite latency structure, not just this value, 621 ) 622 623 val csrCfg = FuConfig( 624 name = "csr", 625 fuGen = csrGen, 626 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 627 fuType = FuType.csr, 628 numIntSrc = 1, 629 numFpSrc = 0, 630 writeIntRf = true, 631 writeFpRf = false, 632 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 633 flushPipe = true 634 ) 635 636 val i2fCfg = FuConfig( 637 name = "i2f", 638 fuGen = i2fGen, 639 fuSel = i2fSel, 640 FuType.i2f, 641 numIntSrc = 1, 642 numFpSrc = 0, 643 writeIntRf = false, 644 writeFpRf = true, 645 writeFflags = true, 646 latency = CertainLatency(2), 647 fastUopOut = true, fastImplemented = true 648 ) 649 650 val divCfg = FuConfig( 651 name = "div", 652 fuGen = dividerGen, 653 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 654 FuType.div, 655 2, 656 0, 657 writeIntRf = true, 658 writeFpRf = false, 659 latency = UncertainLatency(), 660 fastUopOut = true, 661 fastImplemented = true 662 ) 663 664 val mulCfg = FuConfig( 665 name = "mul", 666 fuGen = multiplierGen, 667 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 668 FuType.mul, 669 2, 670 0, 671 writeIntRf = true, 672 writeFpRf = false, 673 latency = CertainLatency(2), 674 fastUopOut = true, 675 fastImplemented = true 676 ) 677 678 val bkuCfg = FuConfig( 679 name = "bku", 680 fuGen = bkuGen, 681 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 682 fuType = FuType.bku, 683 numIntSrc = 2, 684 numFpSrc = 0, 685 writeIntRf = true, 686 writeFpRf = false, 687 latency = CertainLatency(1), 688 fastUopOut = true, 689 fastImplemented = true 690 ) 691 692 val fmacCfg = FuConfig( 693 name = "fmac", 694 fuGen = fmacGen, 695 fuSel = _ => true.B, 696 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 697 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 698 ) 699 700 val f2iCfg = FuConfig( 701 name = "f2i", 702 fuGen = f2iGen, 703 fuSel = f2iSel, 704 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 705 fastUopOut = true, fastImplemented = true 706 ) 707 708 val f2fCfg = FuConfig( 709 name = "f2f", 710 fuGen = f2fGen, 711 fuSel = f2fSel, 712 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 713 fastUopOut = true, fastImplemented = true 714 ) 715 716 val fdivSqrtCfg = FuConfig( 717 name = "fdivSqrt", 718 fuGen = fdivSqrtGen, 719 fuSel = fdivSqrtSel, 720 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 721 fastUopOut = true, fastImplemented = true, hasInputBuffer = true 722 ) 723 724 val lduCfg = FuConfig( 725 "ldu", 726 null, // DontCare 727 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 728 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 729 latency = UncertainLatency(), 730 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 731 flushPipe = true, 732 replayInst = true 733 ) 734 735 val staCfg = FuConfig( 736 "sta", 737 null, 738 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 739 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 740 latency = UncertainLatency(), 741 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 742 ) 743 744 val stdCfg = FuConfig( 745 "std", 746 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 747 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 748 ) 749 750 val mouCfg = FuConfig( 751 "mou", 752 null, 753 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 754 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 755 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 756 ) 757 758 val mouDataCfg = FuConfig( 759 "mou", 760 mouDataGen, 761 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 762 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 763 latency = UncertainLatency() 764 ) 765 766 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 767 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 768 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 769 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 770 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 771 val FmiscExeUnitCfg = ExuConfig( 772 "FmiscExeUnit", 773 "Fp", 774 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 775 Int.MaxValue, 1 776 ) 777 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 778 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 779 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 780} 781