1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 def no = "b000".U // this src read no reg but cannot be Any value 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 51 def apply() = UInt(3.W) 52 } 53 54 object SrcState { 55 def busy = "b0".U 56 def rdy = "b1".U 57 // def specRdy = "b10".U // speculative ready, for future use 58 def apply() = UInt(1.W) 59 60 def isReady(state: UInt): Bool = state === this.rdy 61 def isBusy(state: UInt): Bool = state === this.busy 62 } 63 64 def FuOpTypeWidth = 9 65 object FuOpType { 66 def apply() = UInt(FuOpTypeWidth.W) 67 def X = BitPat("b00000000") 68 } 69 70 object VlduType { 71 // bit encoding: | padding (2bit) || mop (2bit) | lumop(5bit) | 72 // only unit-stride use lumop 73 // mop [1:0] 74 // 0 0 : unit-stride 75 // 0 1 : indexed-unordered 76 // 1 0 : strided 77 // 1 1 : indexed-ordered 78 // lumop[4:0] 79 // 0 0 0 0 0 : unit-stride load 80 // 0 1 0 0 0 : unit-stride, whole register load 81 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 82 // 1 0 0 0 0 : unit-stride fault-only-first 83 def vle = "b00_00_00000".U 84 def vlr = "b00_00_01000".U 85 def vlm = "b00_00_01011".U 86 def vleff = "b00_00_10000".U 87 def vluxe = "b00_01_00000".U 88 def vlse = "b00_10_00000".U 89 def vloxe = "b00_11_00000".U 90 } 91 92 object VstuType { 93 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 94 // only unit-stride use sumop 95 // mop [1:0] 96 // 0 0 : unit-stride 97 // 0 1 : indexed-unordered 98 // 1 0 : strided 99 // 1 1 : indexed-ordered 100 // sumop[4:0] 101 // 0 0 0 0 0 : unit-stride load 102 // 0 1 0 0 0 : unit-stride, whole register load 103 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 104 def vse = "b00_00_00000".U 105 def vsr = "b00_00_01000".U 106 def vsm = "b00_00_01011".U 107 def vsuxe = "b00_01_00000".U 108 def vsse = "b00_10_00000".U 109 def vsoxe = "b00_11_00000".U 110 } 111 112 object IF2VectorType { 113 // use last 3 bits for vsew 114 def i2vector = "b00_00".U 115 def f2vector = "b00_01".U 116 def imm2vector = "b00_10".U 117 def permImm2vector = "b00_11".U 118 } 119 120 object CommitType { 121 def NORMAL = "b000".U // int/fp 122 def BRANCH = "b001".U // branch 123 def LOAD = "b010".U // load 124 def STORE = "b011".U // store 125 126 def apply() = UInt(3.W) 127 def isFused(commitType: UInt): Bool = commitType(2) 128 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 129 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 130 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 131 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 132 } 133 134 object RedirectLevel { 135 def flushAfter = "b0".U 136 def flush = "b1".U 137 138 def apply() = UInt(1.W) 139 // def isUnconditional(level: UInt) = level(1) 140 def flushItself(level: UInt) = level(0) 141 // def isException(level: UInt) = level(1) && level(0) 142 } 143 144 object ExceptionVec { 145 val ExceptionVecSize = 16 146 def apply() = Vec(ExceptionVecSize, Bool()) 147 } 148 149 object PMAMode { 150 def R = "b1".U << 0 //readable 151 def W = "b1".U << 1 //writeable 152 def X = "b1".U << 2 //executable 153 def I = "b1".U << 3 //cacheable: icache 154 def D = "b1".U << 4 //cacheable: dcache 155 def S = "b1".U << 5 //enable speculative access 156 def A = "b1".U << 6 //enable atomic operation, A imply R & W 157 def C = "b1".U << 7 //if it is cacheable is configable 158 def Reserved = "b0".U 159 160 def apply() = UInt(7.W) 161 162 def read(mode: UInt) = mode(0) 163 def write(mode: UInt) = mode(1) 164 def execute(mode: UInt) = mode(2) 165 def icache(mode: UInt) = mode(3) 166 def dcache(mode: UInt) = mode(4) 167 def speculate(mode: UInt) = mode(5) 168 def atomic(mode: UInt) = mode(6) 169 def configable_cache(mode: UInt) = mode(7) 170 171 def strToMode(s: String) = { 172 var result = 0.U(8.W) 173 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 174 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 175 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 176 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 177 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 178 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 179 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 180 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 181 result 182 } 183 } 184 185 186 object CSROpType { 187 def jmp = "b000".U 188 def wrt = "b001".U 189 def set = "b010".U 190 def clr = "b011".U 191 def wfi = "b100".U 192 def wrti = "b101".U 193 def seti = "b110".U 194 def clri = "b111".U 195 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 196 } 197 198 // jump 199 object JumpOpType { 200 def jal = "b00".U 201 def jalr = "b01".U 202 def auipc = "b10".U 203// def call = "b11_011".U 204// def ret = "b11_100".U 205 def jumpOpisJalr(op: UInt) = op(0) 206 def jumpOpisAuipc(op: UInt) = op(1) 207 } 208 209 object FenceOpType { 210 def fence = "b10000".U 211 def sfence = "b10001".U 212 def fencei = "b10010".U 213 def nofence= "b00000".U 214 } 215 216 object ALUOpType { 217 // shift optype 218 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 219 def sll = "b000_0001".U // sll: src1 << src2 220 221 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 222 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 223 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 224 225 def srl = "b000_0101".U // srl: src1 >> src2 226 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 227 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 228 229 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 230 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 231 232 // RV64 32bit optype 233 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 234 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 235 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 236 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 237 238 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 239 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 240 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 241 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 242 243 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 244 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 245 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 246 def rolw = "b001_1100".U 247 def rorw = "b001_1101".U 248 249 // ADD-op 250 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 251 def add = "b010_0001".U // add: src1 + src2 252 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 253 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 254 255 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 256 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 257 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 258 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 259 260 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 261 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 262 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 263 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 264 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 265 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 266 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 267 268 // SUB-op: src1 - src2 269 def sub = "b011_0000".U 270 def sltu = "b011_0001".U 271 def slt = "b011_0010".U 272 def maxu = "b011_0100".U 273 def minu = "b011_0101".U 274 def max = "b011_0110".U 275 def min = "b011_0111".U 276 277 // branch 278 def beq = "b111_0000".U 279 def bne = "b111_0010".U 280 def blt = "b111_1000".U 281 def bge = "b111_1010".U 282 def bltu = "b111_1100".U 283 def bgeu = "b111_1110".U 284 285 // misc optype 286 def and = "b100_0000".U 287 def andn = "b100_0001".U 288 def or = "b100_0010".U 289 def orn = "b100_0011".U 290 def xor = "b100_0100".U 291 def xnor = "b100_0101".U 292 def orcb = "b100_0110".U 293 294 def sextb = "b100_1000".U 295 def packh = "b100_1001".U 296 def sexth = "b100_1010".U 297 def packw = "b100_1011".U 298 299 def revb = "b101_0000".U 300 def rev8 = "b101_0001".U 301 def pack = "b101_0010".U 302 def orh48 = "b101_0011".U 303 304 def szewl1 = "b101_1000".U 305 def szewl2 = "b101_1001".U 306 def szewl3 = "b101_1010".U 307 def byte2 = "b101_1011".U 308 309 def andlsb = "b110_0000".U 310 def andzexth = "b110_0001".U 311 def orlsb = "b110_0010".U 312 def orzexth = "b110_0011".U 313 def xorlsb = "b110_0100".U 314 def xorzexth = "b110_0101".U 315 def orcblsb = "b110_0110".U 316 def orcbzexth = "b110_0111".U 317 318 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 319 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 320 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 321 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 322 323 def apply() = UInt(FuOpTypeWidth.W) 324 } 325 326 object VSETOpType { 327 val setVlmaxBit = 0 328 val keepVlBit = 1 329 // destTypeBit == 0: write vl to rd 330 // destTypeBit == 1: write vconfig 331 val destTypeBit = 5 332 333 // vsetvli's uop 334 // rs1!=x0, normal 335 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 336 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 337 def uvsetvcfg_xi = "b1010_0000".U 338 def uvsetrd_xi = "b1000_0000".U 339 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 340 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 341 // uop1: w(rd) | vlmax, vtypei -> x[rd] 342 def uvsetvcfg_vlmax_i = "b1010_0001".U 343 def uvsetrd_vlmax_i = "b1000_0001".U 344 // rs1==x0, rd==x0, keep vl, set vtype 345 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 346 def uvsetvcfg_keep_v = "b1010_0010".U 347 348 // vsetvl's uop 349 // rs1!=x0, normal 350 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 351 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 352 def uvsetvcfg_xx = "b0110_0000".U 353 def uvsetrd_xx = "b0100_0000".U 354 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 355 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 356 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 357 def uvsetvcfg_vlmax_x = "b0110_0001".U 358 def uvsetrd_vlmax_x = "b0100_0001".U 359 // rs1==x0, rd==x0, keep vl, set vtype 360 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 361 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 362 def uvmv_v_x = "b0110_0010".U 363 def uvsetvcfg_vv = "b0111_0010".U 364 365 // vsetivli's uop 366 // uop0: w(vconfig) | vli, vtypei -> vconfig 367 // uop1: w(rd) | vli, vtypei -> x[rd] 368 def uvsetvcfg_ii = "b0010_0000".U 369 def uvsetrd_ii = "b0000_0000".U 370 371 def isVsetvl (func: UInt) = func(6) 372 def isVsetvli (func: UInt) = func(7) 373 def isVsetivli(func: UInt) = func(7, 6) === 0.U 374 def isNormal (func: UInt) = func(1, 0) === 0.U 375 def isSetVlmax(func: UInt) = func(setVlmaxBit) 376 def isKeepVl (func: UInt) = func(keepVlBit) 377 // RG: region 378 def writeIntRG(func: UInt) = !func(5) 379 def writeVecRG(func: UInt) = func(5) 380 def readIntRG (func: UInt) = !func(4) 381 def readVecRG (func: UInt) = func(4) 382 // modify fuOpType 383 def switchDest(func: UInt) = func ^ (1 << destTypeBit).U 384 def keepVl(func: UInt) = func | (1 << keepVlBit).U 385 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 386 } 387 388 object BRUOpType { 389 // branch 390 def beq = "b000_000".U 391 def bne = "b000_001".U 392 def blt = "b000_100".U 393 def bge = "b000_101".U 394 def bltu = "b001_000".U 395 def bgeu = "b001_001".U 396 397 def getBranchType(func: UInt) = func(3, 1) 398 def isBranchInvert(func: UInt) = func(0) 399 } 400 401 object MULOpType { 402 // mul 403 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 404 def mul = "b00000".U 405 def mulh = "b00001".U 406 def mulhsu = "b00010".U 407 def mulhu = "b00011".U 408 def mulw = "b00100".U 409 410 def mulw7 = "b01100".U 411 def isSign(op: UInt) = !op(1) 412 def isW(op: UInt) = op(2) 413 def isH(op: UInt) = op(1, 0) =/= 0.U 414 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 415 } 416 417 object DIVOpType { 418 // div 419 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 420 def div = "b10000".U 421 def divu = "b10010".U 422 def rem = "b10001".U 423 def remu = "b10011".U 424 425 def divw = "b10100".U 426 def divuw = "b10110".U 427 def remw = "b10101".U 428 def remuw = "b10111".U 429 430 def isSign(op: UInt) = !op(1) 431 def isW(op: UInt) = op(2) 432 def isH(op: UInt) = op(0) 433 } 434 435 object MDUOpType { 436 // mul 437 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 438 def mul = "b00000".U 439 def mulh = "b00001".U 440 def mulhsu = "b00010".U 441 def mulhu = "b00011".U 442 def mulw = "b00100".U 443 444 def mulw7 = "b01100".U 445 446 // div 447 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 448 def div = "b10000".U 449 def divu = "b10010".U 450 def rem = "b10001".U 451 def remu = "b10011".U 452 453 def divw = "b10100".U 454 def divuw = "b10110".U 455 def remw = "b10101".U 456 def remuw = "b10111".U 457 458 def isMul(op: UInt) = !op(4) 459 def isDiv(op: UInt) = op(4) 460 461 def isDivSign(op: UInt) = isDiv(op) && !op(1) 462 def isW(op: UInt) = op(2) 463 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 464 def getMulOp(op: UInt) = op(1, 0) 465 } 466 467 object LSUOpType { 468 // load pipeline 469 470 // normal load 471 // Note: bit(1, 0) are size, DO NOT CHANGE 472 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 473 def lb = "b0000".U 474 def lh = "b0001".U 475 def lw = "b0010".U 476 def ld = "b0011".U 477 def lbu = "b0100".U 478 def lhu = "b0101".U 479 def lwu = "b0110".U 480 481 // Zicbop software prefetch 482 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 483 def prefetch_i = "b1000".U // TODO 484 def prefetch_r = "b1001".U 485 def prefetch_w = "b1010".U 486 487 def isPrefetch(op: UInt): Bool = op(3) 488 489 // store pipeline 490 // normal store 491 // bit encoding: | store 00 | size(2bit) | 492 def sb = "b0000".U 493 def sh = "b0001".U 494 def sw = "b0010".U 495 def sd = "b0011".U 496 497 // l1 cache op 498 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 499 def cbo_zero = "b0111".U 500 501 // llc op 502 // bit encoding: | prefetch 11 | suboptype(2bit) | 503 def cbo_clean = "b1100".U 504 def cbo_flush = "b1101".U 505 def cbo_inval = "b1110".U 506 507 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 508 509 // atomics 510 // bit(1, 0) are size 511 // since atomics use a different fu type 512 // so we can safely reuse other load/store's encodings 513 // bit encoding: | optype(4bit) | size (2bit) | 514 def lr_w = "b000010".U 515 def sc_w = "b000110".U 516 def amoswap_w = "b001010".U 517 def amoadd_w = "b001110".U 518 def amoxor_w = "b010010".U 519 def amoand_w = "b010110".U 520 def amoor_w = "b011010".U 521 def amomin_w = "b011110".U 522 def amomax_w = "b100010".U 523 def amominu_w = "b100110".U 524 def amomaxu_w = "b101010".U 525 526 def lr_d = "b000011".U 527 def sc_d = "b000111".U 528 def amoswap_d = "b001011".U 529 def amoadd_d = "b001111".U 530 def amoxor_d = "b010011".U 531 def amoand_d = "b010111".U 532 def amoor_d = "b011011".U 533 def amomin_d = "b011111".U 534 def amomax_d = "b100011".U 535 def amominu_d = "b100111".U 536 def amomaxu_d = "b101011".U 537 538 def size(op: UInt) = op(1,0) 539 } 540 541 object BKUOpType { 542 543 def clmul = "b000000".U 544 def clmulh = "b000001".U 545 def clmulr = "b000010".U 546 def xpermn = "b000100".U 547 def xpermb = "b000101".U 548 549 def clz = "b001000".U 550 def clzw = "b001001".U 551 def ctz = "b001010".U 552 def ctzw = "b001011".U 553 def cpop = "b001100".U 554 def cpopw = "b001101".U 555 556 // 01xxxx is reserve 557 def aes64es = "b100000".U 558 def aes64esm = "b100001".U 559 def aes64ds = "b100010".U 560 def aes64dsm = "b100011".U 561 def aes64im = "b100100".U 562 def aes64ks1i = "b100101".U 563 def aes64ks2 = "b100110".U 564 565 // merge to two instruction sm4ks & sm4ed 566 def sm4ed0 = "b101000".U 567 def sm4ed1 = "b101001".U 568 def sm4ed2 = "b101010".U 569 def sm4ed3 = "b101011".U 570 def sm4ks0 = "b101100".U 571 def sm4ks1 = "b101101".U 572 def sm4ks2 = "b101110".U 573 def sm4ks3 = "b101111".U 574 575 def sha256sum0 = "b110000".U 576 def sha256sum1 = "b110001".U 577 def sha256sig0 = "b110010".U 578 def sha256sig1 = "b110011".U 579 def sha512sum0 = "b110100".U 580 def sha512sum1 = "b110101".U 581 def sha512sig0 = "b110110".U 582 def sha512sig1 = "b110111".U 583 584 def sm3p0 = "b111000".U 585 def sm3p1 = "b111001".U 586 } 587 588 object BTBtype { 589 def B = "b00".U // branch 590 def J = "b01".U // jump 591 def I = "b10".U // indirect 592 def R = "b11".U // return 593 594 def apply() = UInt(2.W) 595 } 596 597 object SelImm { 598 def IMM_X = "b0111".U 599 def IMM_S = "b1110".U 600 def IMM_SB = "b0001".U 601 def IMM_U = "b0010".U 602 def IMM_UJ = "b0011".U 603 def IMM_I = "b0100".U 604 def IMM_Z = "b0101".U 605 def INVALID_INSTR = "b0110".U 606 def IMM_B6 = "b1000".U 607 608 def IMM_OPIVIS = "b1001".U 609 def IMM_OPIVIU = "b1010".U 610 def IMM_VSETVLI = "b1100".U 611 def IMM_VSETIVLI = "b1101".U 612 def IMM_LUI32 = "b1011".U 613 614 def X = BitPat("b0000") 615 616 def apply() = UInt(4.W) 617 618 def mkString(immType: UInt) : String = { 619 val strMap = Map( 620 IMM_S.litValue -> "S", 621 IMM_SB.litValue -> "SB", 622 IMM_U.litValue -> "U", 623 IMM_UJ.litValue -> "UJ", 624 IMM_I.litValue -> "I", 625 IMM_Z.litValue -> "Z", 626 IMM_B6.litValue -> "B6", 627 IMM_OPIVIS.litValue -> "VIS", 628 IMM_OPIVIU.litValue -> "VIU", 629 IMM_VSETVLI.litValue -> "VSETVLI", 630 IMM_VSETIVLI.litValue -> "VSETIVLI", 631 IMM_LUI32.litValue -> "LUI32", 632 INVALID_INSTR.litValue -> "INVALID", 633 ) 634 strMap(immType.litValue) 635 } 636 } 637 638 object UopSplitType { 639 def SCA_SIM = "b000000".U // 640 def DIR = "b010001".U // dirty: vset 641 def VEC_VVV = "b010010".U // VEC_VVV 642 def VEC_VXV = "b010011".U // VEC_VXV 643 def VEC_0XV = "b010100".U // VEC_0XV 644 def VEC_VVW = "b010101".U // VEC_VVW 645 def VEC_WVW = "b010110".U // VEC_WVW 646 def VEC_VXW = "b010111".U // VEC_VXW 647 def VEC_WXW = "b011000".U // VEC_WXW 648 def VEC_WVV = "b011001".U // VEC_WVV 649 def VEC_WXV = "b011010".U // VEC_WXV 650 def VEC_EXT2 = "b011011".U // VF2 0 -> V 651 def VEC_EXT4 = "b011100".U // VF4 0 -> V 652 def VEC_EXT8 = "b011101".U // VF8 0 -> V 653 def VEC_VVM = "b011110".U // VEC_VVM 654 def VEC_VXM = "b011111".U // VEC_VXM 655 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 656 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 657 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 658 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 659 def VEC_VRED = "b100100".U // VEC_VRED 660 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 661 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 662 def VEC_M0X = "b101001".U // VEC_M0X 0MV 663 def VEC_MVV = "b101010".U // VEC_MVV VMV 664 def VEC_M0X_VFIRST = "b101011".U // 665 def VEC_VWW = "b101100".U // 666 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 667 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 668 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 669 def VEC_COMPRESS = "b110000".U // vcompress.vm 670 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 671 def VEC_S_LDST = "b110010".U // vector strided load/store 672 def VEC_I_LDST = "b110011".U // vector indexed load/store 673 def VEC_VFV = "b111000".U // VEC_VFV 674 def VEC_VFW = "b111001".U // VEC_VFW 675 def VEC_WFW = "b111010".U // VEC_WVW 676 def VEC_VFM = "b111011".U // VEC_VFM 677 def VEC_VFRED = "b111100".U // VEC_VFRED 678 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 679 def VEC_M0M = "b000000".U // VEC_M0M 680 def VEC_MMM = "b000000".U // VEC_MMM 681 def VEC_MVNR = "b000100".U // vmvnr 682 def dummy = "b111111".U 683 684 def X = BitPat("b000000") 685 686 def apply() = UInt(6.W) 687 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 688 } 689 690 object ExceptionNO { 691 def instrAddrMisaligned = 0 692 def instrAccessFault = 1 693 def illegalInstr = 2 694 def breakPoint = 3 695 def loadAddrMisaligned = 4 696 def loadAccessFault = 5 697 def storeAddrMisaligned = 6 698 def storeAccessFault = 7 699 def ecallU = 8 700 def ecallS = 9 701 def ecallM = 11 702 def instrPageFault = 12 703 def loadPageFault = 13 704 // def singleStep = 14 705 def storePageFault = 15 706 def priorities = Seq( 707 breakPoint, // TODO: different BP has different priority 708 instrPageFault, 709 instrAccessFault, 710 illegalInstr, 711 instrAddrMisaligned, 712 ecallM, ecallS, ecallU, 713 storeAddrMisaligned, 714 loadAddrMisaligned, 715 storePageFault, 716 loadPageFault, 717 storeAccessFault, 718 loadAccessFault 719 ) 720 def all = priorities.distinct.sorted 721 def frontendSet = Seq( 722 instrAddrMisaligned, 723 instrAccessFault, 724 illegalInstr, 725 instrPageFault 726 ) 727 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 728 val new_vec = Wire(ExceptionVec()) 729 new_vec.foreach(_ := false.B) 730 select.foreach(i => new_vec(i) := vec(i)) 731 new_vec 732 } 733 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 734 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 735 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 736 partialSelect(vec, fuConfig.exceptionOut) 737 } 738 739 object TopDownCounters extends Enumeration { 740 val NoStall = Value("NoStall") // Base 741 // frontend 742 val OverrideBubble = Value("OverrideBubble") 743 val FtqUpdateBubble = Value("FtqUpdateBubble") 744 // val ControlRedirectBubble = Value("ControlRedirectBubble") 745 val TAGEMissBubble = Value("TAGEMissBubble") 746 val SCMissBubble = Value("SCMissBubble") 747 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 748 val RASMissBubble = Value("RASMissBubble") 749 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 750 val OtherRedirectBubble = Value("OtherRedirectBubble") 751 val FtqFullStall = Value("FtqFullStall") 752 753 val ICacheMissBubble = Value("ICacheMissBubble") 754 val ITLBMissBubble = Value("ITLBMissBubble") 755 val BTBMissBubble = Value("BTBMissBubble") 756 val FetchFragBubble = Value("FetchFragBubble") 757 758 // backend 759 // long inst stall at rob head 760 val DivStall = Value("DivStall") // int div, float div/sqrt 761 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 762 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 763 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 764 // freelist full 765 val IntFlStall = Value("IntFlStall") 766 val FpFlStall = Value("FpFlStall") 767 // dispatch queue full 768 val IntDqStall = Value("IntDqStall") 769 val FpDqStall = Value("FpDqStall") 770 val LsDqStall = Value("LsDqStall") 771 772 // memblock 773 val LoadTLBStall = Value("LoadTLBStall") 774 val LoadL1Stall = Value("LoadL1Stall") 775 val LoadL2Stall = Value("LoadL2Stall") 776 val LoadL3Stall = Value("LoadL3Stall") 777 val LoadMemStall = Value("LoadMemStall") 778 val StoreStall = Value("StoreStall") // include store tlb miss 779 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 780 781 // xs replay (different to gem5) 782 val LoadVioReplayStall = Value("LoadVioReplayStall") 783 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 784 785 // bad speculation 786 val ControlRecoveryStall = Value("ControlRecoveryStall") 787 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 788 val OtherRecoveryStall = Value("OtherRecoveryStall") 789 790 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 791 792 val OtherCoreStall = Value("OtherCoreStall") 793 794 val NumStallReasons = Value("NumStallReasons") 795 } 796} 797