1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import xiangshan.ExceptionNO._ 20import xiangshan.backend.exu._ 21import xiangshan.backend.fu._ 22import xiangshan.backend.fu.fpu._ 23import xiangshan.backend.fu.vector._ 24import xiangshan.backend.issue._ 25import xiangshan.v2backend.FuConfig 26 27package object xiangshan { 28 object SrcType { 29 def imm = "b000".U 30 def pc = "b000".U 31 def xp = "b001".U 32 def fp = "b010".U 33 def vp = "b100".U 34 35 // alias 36 def reg = this.xp 37 def DC = imm // Don't Care 38 def X = BitPat("b000") 39 40 def isPc(srcType: UInt) = srcType===pc 41 def isImm(srcType: UInt) = srcType===imm 42 def isReg(srcType: UInt) = srcType(0) 43 def isXp(srcType: UInt) = srcType(0) 44 def isFp(srcType: UInt) = srcType(1) 45 def isVp(srcType: UInt) = srcType(2) 46 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 47 def isNotReg(srcType: UInt): Bool = !srcType.orR 48 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 49 def apply() = UInt(3.W) 50 } 51 52 object SrcState { 53 def busy = "b0".U 54 def rdy = "b1".U 55 // def specRdy = "b10".U // speculative ready, for future use 56 def apply() = UInt(1.W) 57 58 def isReady(state: UInt): Bool = state === this.rdy 59 def isBusy(state: UInt): Bool = state === this.busy 60 } 61 62 // Todo: Use OH instead 63// object FuType { 64// def jmp = (BigInt(1) << 0).U 65// def brh = (BigInt(1) << 1).U 66// def i2f = (BigInt(1) << 2).U 67// def csr = (BigInt(1) << 3).U 68// def alu = (BigInt(1) << 4).U 69// def mul = (BigInt(1) << 5).U 70// def div = (BigInt(1) << 6).U 71// def fence = (BigInt(1) << 7).U 72// def bku = (BigInt(1) << 8).U 73// def vset = (BigInt(1) << 9).U 74// 75// def fmac = (BigInt(1) << 10).U 76// def fmisc = (BigInt(1) << 11).U 77// def fDivSqrt = (BigInt(1) << 12).U 78// 79// def ldu = (BigInt(1) << 13).U 80// def stu = (BigInt(1) << 14).U 81// def mou = (BigInt(1) << 15).U // for amo, lr, sc, fence 82// def vipu = (BigInt(1) << 16).U 83// def vfpu = (BigInt(1) << 17).U 84// def vldu = (BigInt(1) << 18).U 85// def vstu = (BigInt(1) << 19).U 86// def X = BitPat.dontCare(num) 87// 88// def num = 20 89// 90// def apply() = UInt(log2Up(num).W) 91// 92// def isIntExu(fuType: UInt) = !fuType(3) 93// def isJumpExu(fuType: UInt) = fuType === jmp 94// def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 95// def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 96// def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 97// def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 98// def isAMO(fuType: UInt) = fuType(1) 99// def isFence(fuType: UInt) = fuType === fence 100// def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 101// def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 102// def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 103// def isVpu(fuType: UInt) = fuType(4) 104// 105// def jmpCanAccept(fuType: UInt) = !fuType(2) 106// def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 107// def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 108// 109// def fmacCanAccept(fuType: UInt) = !fuType(1) 110// def fmiscCanAccept(fuType: UInt) = fuType(1) 111// 112// def loadCanAccept(fuType: UInt) = !fuType(0) 113// def storeCanAccept(fuType: UInt) = fuType(0) 114// 115// def storeIsAMO(fuType: UInt) = fuType(1) 116// 117// val functionNameMap = Map( 118// jmp.litValue() -> "jmp", 119// i2f.litValue() -> "int_to_float", 120// csr.litValue() -> "csr", 121// alu.litValue() -> "alu", 122// mul.litValue() -> "mul", 123// div.litValue() -> "div", 124// fence.litValue() -> "fence", 125// bku.litValue() -> "bku", 126// fmac.litValue() -> "fmac", 127// fmisc.litValue() -> "fmisc", 128// fDivSqrt.litValue() -> "fdiv_fsqrt", 129// ldu.litValue() -> "load", 130// stu.litValue() -> "store", 131// mou.litValue() -> "mou" 132// ) 133// } 134 135 def FuOpTypeWidth = 8 136 object FuOpType { 137 def apply() = UInt(FuOpTypeWidth.W) 138 def X = BitPat("b00000000") 139 } 140 141 // move VipuType and VfpuType into YunSuan/package.scala 142 // object VipuType { 143 // def dummy = 0.U(7.W) 144 // } 145 146 // object VfpuType { 147 // def dummy = 0.U(7.W) 148 // } 149 150 object VlduType { 151 def dummy = 0.U 152 } 153 154 object VstuType { 155 def dummy = 0.U 156 } 157 158 object CommitType { 159 def NORMAL = "b000".U // int/fp 160 def BRANCH = "b001".U // branch 161 def LOAD = "b010".U // load 162 def STORE = "b011".U // store 163 164 def apply() = UInt(3.W) 165 def isFused(commitType: UInt): Bool = commitType(2) 166 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 167 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 168 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 169 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 170 } 171 172 object RedirectLevel { 173 def flushAfter = "b0".U 174 def flush = "b1".U 175 176 def apply() = UInt(1.W) 177 // def isUnconditional(level: UInt) = level(1) 178 def flushItself(level: UInt) = level(0) 179 // def isException(level: UInt) = level(1) && level(0) 180 } 181 182 object ExceptionVec { 183 def apply() = Vec(16, Bool()) 184 } 185 186 object PMAMode { 187 def R = "b1".U << 0 //readable 188 def W = "b1".U << 1 //writeable 189 def X = "b1".U << 2 //executable 190 def I = "b1".U << 3 //cacheable: icache 191 def D = "b1".U << 4 //cacheable: dcache 192 def S = "b1".U << 5 //enable speculative access 193 def A = "b1".U << 6 //enable atomic operation, A imply R & W 194 def C = "b1".U << 7 //if it is cacheable is configable 195 def Reserved = "b0".U 196 197 def apply() = UInt(7.W) 198 199 def read(mode: UInt) = mode(0) 200 def write(mode: UInt) = mode(1) 201 def execute(mode: UInt) = mode(2) 202 def icache(mode: UInt) = mode(3) 203 def dcache(mode: UInt) = mode(4) 204 def speculate(mode: UInt) = mode(5) 205 def atomic(mode: UInt) = mode(6) 206 def configable_cache(mode: UInt) = mode(7) 207 208 def strToMode(s: String) = { 209 var result = 0.U(8.W) 210 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 211 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 212 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 213 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 214 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 215 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 216 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 217 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 218 result 219 } 220 } 221 222 223 object CSROpType { 224 def jmp = "b000".U 225 def wrt = "b001".U 226 def set = "b010".U 227 def clr = "b011".U 228 def wfi = "b100".U 229 def wrti = "b101".U 230 def seti = "b110".U 231 def clri = "b111".U 232 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 233 } 234 235 // jump 236 object JumpOpType { 237 def jal = "b00".U 238 def jalr = "b01".U 239 def auipc = "b10".U 240// def call = "b11_011".U 241// def ret = "b11_100".U 242 def jumpOpisJalr(op: UInt) = op(0) 243 def jumpOpisAuipc(op: UInt) = op(1) 244 } 245 246 object FenceOpType { 247 def fence = "b10000".U 248 def sfence = "b10001".U 249 def fencei = "b10010".U 250 def nofence= "b00000".U 251 } 252 253 object ALUOpType { 254 // shift optype 255 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 256 def sll = "b000_0001".U // sll: src1 << src2 257 258 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 259 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 260 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 261 262 def srl = "b000_0101".U // srl: src1 >> src2 263 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 264 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 265 266 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 267 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 268 269 // RV64 32bit optype 270 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 271 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 272 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 273 274 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 275 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 276 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 277 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 278 279 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 280 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 281 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 282 def rolw = "b001_1100".U 283 def rorw = "b001_1101".U 284 285 // ADD-op 286 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 287 def add = "b010_0001".U // add: src1 + src2 288 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 289 290 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 291 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 292 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 293 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 294 295 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 296 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 297 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 298 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 299 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 300 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 301 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 302 303 // SUB-op: src1 - src2 304 def sub = "b011_0000".U 305 def sltu = "b011_0001".U 306 def slt = "b011_0010".U 307 def maxu = "b011_0100".U 308 def minu = "b011_0101".U 309 def max = "b011_0110".U 310 def min = "b011_0111".U 311 312 // branch 313 def beq = "b111_0000".U 314 def bne = "b111_0010".U 315 def blt = "b111_1000".U 316 def bge = "b111_1010".U 317 def bltu = "b111_1100".U 318 def bgeu = "b111_1110".U 319 320 // misc optype 321 def and = "b100_0000".U 322 def andn = "b100_0001".U 323 def or = "b100_0010".U 324 def orn = "b100_0011".U 325 def xor = "b100_0100".U 326 def xnor = "b100_0101".U 327 def orcb = "b100_0110".U 328 329 def sextb = "b100_1000".U 330 def packh = "b100_1001".U 331 def sexth = "b100_1010".U 332 def packw = "b100_1011".U 333 334 def revb = "b101_0000".U 335 def rev8 = "b101_0001".U 336 def pack = "b101_0010".U 337 def orh48 = "b101_0011".U 338 339 def szewl1 = "b101_1000".U 340 def szewl2 = "b101_1001".U 341 def szewl3 = "b101_1010".U 342 def byte2 = "b101_1011".U 343 344 def andlsb = "b110_0000".U 345 def andzexth = "b110_0001".U 346 def orlsb = "b110_0010".U 347 def orzexth = "b110_0011".U 348 def xorlsb = "b110_0100".U 349 def xorzexth = "b110_0101".U 350 def orcblsb = "b110_0110".U 351 def orcbzexth = "b110_0111".U 352 def vsetvli1 = "b1000_0000".U 353 def vsetvli2 = "b1000_0100".U 354 def vsetvl1 = "b1000_0001".U 355 def vsetvl2 = "b1000_0101".U 356 def vsetivli1 = "b1000_0010".U 357 def vsetivli2 = "b1000_0110".U 358 359 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 360 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 361 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 362 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 363 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 364 def isVsetvl(func: UInt) = isVset(func) && func(0) 365 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 366 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 367 368 def apply() = UInt(FuOpTypeWidth.W) 369 } 370 371 object BRUOpType { 372 // branch 373 def beq = "b000_000".U 374 def bne = "b000_001".U 375 def blt = "b000_100".U 376 def bge = "b000_101".U 377 def bltu = "b001_000".U 378 def bgeu = "b001_001".U 379 380 def getBranchType(func: UInt) = func(3, 1) 381 def isBranchInvert(func: UInt) = func(0) 382 } 383 384 object MULOpType { 385 // mul 386 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 387 def mul = "b00000".U 388 def mulh = "b00001".U 389 def mulhsu = "b00010".U 390 def mulhu = "b00011".U 391 def mulw = "b00100".U 392 393 def mulw7 = "b01100".U 394 def isSign(op: UInt) = !op(1) 395 def isW(op: UInt) = op(2) 396 def isH(op: UInt) = op(1, 0) =/= 0.U 397 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 398 } 399 400 object DIVOpType { 401 // div 402 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 403 def div = "b10000".U 404 def divu = "b10010".U 405 def rem = "b10001".U 406 def remu = "b10011".U 407 408 def divw = "b10100".U 409 def divuw = "b10110".U 410 def remw = "b10101".U 411 def remuw = "b10111".U 412 413 def isSign(op: UInt) = !op(1) 414 def isW(op: UInt) = op(2) 415 def isH(op: UInt) = op(0) 416 } 417 418 object MDUOpType { 419 // mul 420 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 421 def mul = "b00000".U 422 def mulh = "b00001".U 423 def mulhsu = "b00010".U 424 def mulhu = "b00011".U 425 def mulw = "b00100".U 426 427 def mulw7 = "b01100".U 428 429 // div 430 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 431 def div = "b10000".U 432 def divu = "b10010".U 433 def rem = "b10001".U 434 def remu = "b10011".U 435 436 def divw = "b10100".U 437 def divuw = "b10110".U 438 def remw = "b10101".U 439 def remuw = "b10111".U 440 441 def isMul(op: UInt) = !op(4) 442 def isDiv(op: UInt) = op(4) 443 444 def isDivSign(op: UInt) = isDiv(op) && !op(1) 445 def isW(op: UInt) = op(2) 446 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 447 def getMulOp(op: UInt) = op(1, 0) 448 } 449 450 object LSUOpType { 451 // load pipeline 452 453 // normal load 454 // Note: bit(1, 0) are size, DO NOT CHANGE 455 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 456 def lb = "b0000".U 457 def lh = "b0001".U 458 def lw = "b0010".U 459 def ld = "b0011".U 460 def lbu = "b0100".U 461 def lhu = "b0101".U 462 def lwu = "b0110".U 463 464 // Zicbop software prefetch 465 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 466 def prefetch_i = "b1000".U // TODO 467 def prefetch_r = "b1001".U 468 def prefetch_w = "b1010".U 469 470 def isPrefetch(op: UInt): Bool = op(3) 471 472 // store pipeline 473 // normal store 474 // bit encoding: | store 00 | size(2bit) | 475 def sb = "b0000".U 476 def sh = "b0001".U 477 def sw = "b0010".U 478 def sd = "b0011".U 479 480 // l1 cache op 481 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 482 def cbo_zero = "b0111".U 483 484 // llc op 485 // bit encoding: | prefetch 11 | suboptype(2bit) | 486 def cbo_clean = "b1100".U 487 def cbo_flush = "b1101".U 488 def cbo_inval = "b1110".U 489 490 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 491 492 // atomics 493 // bit(1, 0) are size 494 // since atomics use a different fu type 495 // so we can safely reuse other load/store's encodings 496 // bit encoding: | optype(4bit) | size (2bit) | 497 def lr_w = "b000010".U 498 def sc_w = "b000110".U 499 def amoswap_w = "b001010".U 500 def amoadd_w = "b001110".U 501 def amoxor_w = "b010010".U 502 def amoand_w = "b010110".U 503 def amoor_w = "b011010".U 504 def amomin_w = "b011110".U 505 def amomax_w = "b100010".U 506 def amominu_w = "b100110".U 507 def amomaxu_w = "b101010".U 508 509 def lr_d = "b000011".U 510 def sc_d = "b000111".U 511 def amoswap_d = "b001011".U 512 def amoadd_d = "b001111".U 513 def amoxor_d = "b010011".U 514 def amoand_d = "b010111".U 515 def amoor_d = "b011011".U 516 def amomin_d = "b011111".U 517 def amomax_d = "b100011".U 518 def amominu_d = "b100111".U 519 def amomaxu_d = "b101011".U 520 521 def size(op: UInt) = op(1,0) 522 } 523 524 object BKUOpType { 525 526 def clmul = "b000000".U 527 def clmulh = "b000001".U 528 def clmulr = "b000010".U 529 def xpermn = "b000100".U 530 def xpermb = "b000101".U 531 532 def clz = "b001000".U 533 def clzw = "b001001".U 534 def ctz = "b001010".U 535 def ctzw = "b001011".U 536 def cpop = "b001100".U 537 def cpopw = "b001101".U 538 539 // 01xxxx is reserve 540 def aes64es = "b100000".U 541 def aes64esm = "b100001".U 542 def aes64ds = "b100010".U 543 def aes64dsm = "b100011".U 544 def aes64im = "b100100".U 545 def aes64ks1i = "b100101".U 546 def aes64ks2 = "b100110".U 547 548 // merge to two instruction sm4ks & sm4ed 549 def sm4ed0 = "b101000".U 550 def sm4ed1 = "b101001".U 551 def sm4ed2 = "b101010".U 552 def sm4ed3 = "b101011".U 553 def sm4ks0 = "b101100".U 554 def sm4ks1 = "b101101".U 555 def sm4ks2 = "b101110".U 556 def sm4ks3 = "b101111".U 557 558 def sha256sum0 = "b110000".U 559 def sha256sum1 = "b110001".U 560 def sha256sig0 = "b110010".U 561 def sha256sig1 = "b110011".U 562 def sha512sum0 = "b110100".U 563 def sha512sum1 = "b110101".U 564 def sha512sig0 = "b110110".U 565 def sha512sig1 = "b110111".U 566 567 def sm3p0 = "b111000".U 568 def sm3p1 = "b111001".U 569 } 570 571 object BTBtype { 572 def B = "b00".U // branch 573 def J = "b01".U // jump 574 def I = "b10".U // indirect 575 def R = "b11".U // return 576 577 def apply() = UInt(2.W) 578 } 579 580 object SelImm { 581 def IMM_X = "b0111".U 582 def IMM_S = "b0000".U 583 def IMM_SB = "b0001".U 584 def IMM_U = "b0010".U 585 def IMM_UJ = "b0011".U 586 def IMM_I = "b0100".U 587 def IMM_Z = "b0101".U 588 def INVALID_INSTR = "b0110".U 589 def IMM_B6 = "b1000".U 590 591 def IMM_OPIVIS = "b1001".U 592 def IMM_OPIVIU = "b1010".U 593 def IMM_VSETVLI = "b1100".U 594 def IMM_VSETIVLI = "b1101".U 595 596 def X = BitPat("b0000") 597 598 def apply() = UInt(4.W) 599 } 600 601 object ExceptionNO { 602 def instrAddrMisaligned = 0 603 def instrAccessFault = 1 604 def illegalInstr = 2 605 def breakPoint = 3 606 def loadAddrMisaligned = 4 607 def loadAccessFault = 5 608 def storeAddrMisaligned = 6 609 def storeAccessFault = 7 610 def ecallU = 8 611 def ecallS = 9 612 def ecallM = 11 613 def instrPageFault = 12 614 def loadPageFault = 13 615 // def singleStep = 14 616 def storePageFault = 15 617 def priorities = Seq( 618 breakPoint, // TODO: different BP has different priority 619 instrPageFault, 620 instrAccessFault, 621 illegalInstr, 622 instrAddrMisaligned, 623 ecallM, ecallS, ecallU, 624 storeAddrMisaligned, 625 loadAddrMisaligned, 626 storePageFault, 627 loadPageFault, 628 storeAccessFault, 629 loadAccessFault 630 ) 631 def all = priorities.distinct.sorted 632 def frontendSet = Seq( 633 instrAddrMisaligned, 634 instrAccessFault, 635 illegalInstr, 636 instrPageFault 637 ) 638 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 639 val new_vec = Wire(ExceptionVec()) 640 new_vec.foreach(_ := false.B) 641 select.foreach(i => new_vec(i) := vec(i)) 642 new_vec 643 } 644 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 645 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 646 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 647 partialSelect(vec, fuConfig.exceptionOut) 648// def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 649// partialSelect(vec, exuConfig.exceptionOut) 650// def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 651// partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 652 } 653 654// def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 655// def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 656// def aluGen(p: Parameters) = new Alu()(p) 657// def bkuGen(p: Parameters) = new Bku()(p) 658// def jmpGen(p: Parameters) = new Jump()(p) 659// def fenceGen(p: Parameters) = new Fence()(p) 660// def csrGen(p: Parameters) = new CSR()(p) 661// def i2fGen(p: Parameters) = new IntToFP()(p) 662// def fmacGen(p: Parameters) = new FMA()(p) 663// def f2iGen(p: Parameters) = new FPToInt()(p) 664// def f2fGen(p: Parameters) = new FPToFP()(p) 665// def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 666// def stdGen(p: Parameters) = new Std()(p) 667// def mouDataGen(p: Parameters) = new Std()(p) 668// def vipuGen(p: Parameters) = new VIPU()(p) 669// 670// def f2iSel(uop: MicroOp): Bool = { 671// uop.ctrl.rfWen 672// } 673// 674// def i2fSel(uop: MicroOp): Bool = { 675// uop.ctrl.fpu.fromInt 676// } 677// 678// def f2fSel(uop: MicroOp): Bool = { 679// val ctrl = uop.ctrl.fpu 680// ctrl.fpWen && !ctrl.div && !ctrl.sqrt 681// } 682// 683// def fdivSqrtSel(uop: MicroOp): Bool = { 684// val ctrl = uop.ctrl.fpu 685// ctrl.div || ctrl.sqrt 686// } 687// 688// val aluCfg = FuConfig( 689// name = "alu", 690// fuGen = aluGen, 691// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 692// fuType = FuType.alu, 693// numIntSrc = 2, 694// numFpSrc = 0, 695// writeIntRf = true, 696// writeFpRf = false, 697// hasRedirect = true, 698// ) 699// 700// val jmpCfg = FuConfig( 701// name = "jmp", 702// fuGen = jmpGen, 703// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 704// fuType = FuType.jmp, 705// numIntSrc = 1, 706// numFpSrc = 0, 707// writeIntRf = true, 708// writeFpRf = false, 709// hasRedirect = true, 710// ) 711// 712// val fenceCfg = FuConfig( 713// name = "fence", 714// fuGen = fenceGen, 715// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 716// FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 717// latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 718// flushPipe = true 719// ) 720// 721// val csrCfg = FuConfig( 722// name = "csr", 723// fuGen = csrGen, 724// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 725// fuType = FuType.csr, 726// numIntSrc = 1, 727// numFpSrc = 0, 728// writeIntRf = true, 729// writeFpRf = false, 730// exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 731// flushPipe = true 732// ) 733// 734// val i2fCfg = FuConfig( 735// name = "i2f", 736// fuGen = i2fGen, 737// fuSel = i2fSel, 738// FuType.i2f, 739// numIntSrc = 1, 740// numFpSrc = 0, 741// writeIntRf = false, 742// writeFpRf = true, 743// writeFflags = true, 744// latency = CertainLatency(2), 745// fastUopOut = true, fastImplemented = true 746// ) 747// 748// val divCfg = FuConfig( 749// name = "div", 750// fuGen = dividerGen, 751// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 752// FuType.div, 753// 2, 754// 0, 755// writeIntRf = true, 756// writeFpRf = false, 757// latency = UncertainLatency(), 758// fastUopOut = true, 759// fastImplemented = true, 760// hasInputBuffer = (true, 4, true) 761// ) 762// 763// val mulCfg = FuConfig( 764// name = "mul", 765// fuGen = multiplierGen, 766// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 767// FuType.mul, 768// 2, 769// 0, 770// writeIntRf = true, 771// writeFpRf = false, 772// latency = CertainLatency(2), 773// fastUopOut = true, 774// fastImplemented = true 775// ) 776// 777// val bkuCfg = FuConfig( 778// name = "bku", 779// fuGen = bkuGen, 780// fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 781// fuType = FuType.bku, 782// numIntSrc = 2, 783// numFpSrc = 0, 784// writeIntRf = true, 785// writeFpRf = false, 786// latency = CertainLatency(1), 787// fastUopOut = true, 788// fastImplemented = true 789// ) 790// 791// val fmacCfg = FuConfig( 792// name = "fmac", 793// fuGen = fmacGen, 794// fuSel = _ => true.B, 795// FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 796// latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 797// ) 798// 799// val f2iCfg = FuConfig( 800// name = "f2i", 801// fuGen = f2iGen, 802// fuSel = f2iSel, 803// FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 804// fastUopOut = true, fastImplemented = true 805// ) 806// 807// val f2fCfg = FuConfig( 808// name = "f2f", 809// fuGen = f2fGen, 810// fuSel = f2fSel, 811// FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 812// fastUopOut = true, fastImplemented = true 813// ) 814// 815// val fdivSqrtCfg = FuConfig( 816// name = "fdivSqrt", 817// fuGen = fdivSqrtGen, 818// fuSel = fdivSqrtSel, 819// FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 820// fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 821// ) 822// 823// val lduCfg = FuConfig( 824// "ldu", 825// null, // DontCare 826// (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 827// FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 828// latency = UncertainLatency(), 829// exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 830// flushPipe = true, 831// replayInst = true, 832// hasLoadError = true 833// ) 834// 835// val staCfg = FuConfig( 836// "sta", 837// null, 838// (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 839// FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 840// latency = UncertainLatency(), 841// exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 842// ) 843// 844// val stdCfg = FuConfig( 845// "std", 846// fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 847// writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 848// ) 849// 850// val mouCfg = FuConfig( 851// "mou", 852// null, 853// (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 854// FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 855// latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 856// ) 857// 858// val mouDataCfg = FuConfig( 859// "mou", 860// mouDataGen, 861// (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 862// FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 863// latency = UncertainLatency() 864// ) 865// 866// val vipuCfg = FuConfig( 867// name = "vipu", 868// fuGen = vipuGen, 869// fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 870// fuType = FuType.vipu, 871// numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 872// numVecSrc = 2, writeVecRf = true, 873// fastUopOut = true, // TODO: check 874// fastImplemented = true, //TODO: check 875// ) 876 877// val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 878// val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 879// val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 880// val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 881// val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 882// val FmiscExeUnitCfg = ExuConfig( 883// "FmiscExeUnit", 884// "Fp", 885// Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 886// Int.MaxValue, 1 887// ) 888// val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 889// val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 890// val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 891 892 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 893 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 894 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 895 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 896 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 897 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 898 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 899 900// val aluRSMod = new RSMod( 901// rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 902// rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 903// immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 904// ) 905// val fmaRSMod = new RSMod( 906// rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 907// rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 908// ) 909// val fmiscRSMod = new RSMod( 910// rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 911// rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 912// ) 913// val jumpRSMod = new RSMod( 914// rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 915// rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 916// immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 917// ) 918// val loadRSMod = new RSMod( 919// rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 920// rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 921// immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 922// ) 923// val mulRSMod = new RSMod( 924// rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 925// rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 926// immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 927// ) 928// val staRSMod = new RSMod( 929// rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 930// rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 931// ) 932// val stdRSMod = new RSMod( 933// rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 934// rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 935// ) 936} 937