1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isFp(srcType: UInt) = srcType(1) 46 def isVp(srcType: UInt) = srcType(2) 47 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 48 49 def apply() = UInt(3.W) 50 } 51 52 object SrcState { 53 def busy = "b0".U 54 def rdy = "b1".U 55 // def specRdy = "b10".U // speculative ready, for future use 56 def apply() = UInt(1.W) 57 } 58 59 // Todo: Use OH instead 60 object FuType { 61 def jmp = "b00000".U 62 def i2f = "b00001".U 63 def csr = "b00010".U 64 def alu = "b00110".U 65 def mul = "b00100".U 66 def div = "b00101".U 67 def fence = "b00011".U 68 def bku = "b00111".U 69 70 def fmac = "b01000".U 71 def fmisc = "b01011".U 72 def fDivSqrt = "b01010".U 73 74 def ldu = "b01100".U 75 def stu = "b01101".U 76 def mou = "b01111".U // for amo, lr, sc, fence 77 def vipu = "b10000".U 78 def vfpu = "b11000".U 79 def vldu = "b11100".U 80 def vstu = "b11101".U 81 def X = BitPat("b00000") 82 83 def num = 18 84 85 def apply() = UInt(log2Up(num).W) 86 87 def isIntExu(fuType: UInt) = !fuType(3) 88 def isJumpExu(fuType: UInt) = fuType === jmp 89 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 90 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 91 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 92 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 93 def isAMO(fuType: UInt) = fuType(1) 94 def isFence(fuType: UInt) = fuType === fence 95 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 96 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 97 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 98 99 100 def jmpCanAccept(fuType: UInt) = !fuType(2) 101 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 102 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 103 104 def fmacCanAccept(fuType: UInt) = !fuType(1) 105 def fmiscCanAccept(fuType: UInt) = fuType(1) 106 107 def loadCanAccept(fuType: UInt) = !fuType(0) 108 def storeCanAccept(fuType: UInt) = fuType(0) 109 110 def storeIsAMO(fuType: UInt) = fuType(1) 111 112 val functionNameMap = Map( 113 jmp.litValue() -> "jmp", 114 i2f.litValue() -> "int_to_float", 115 csr.litValue() -> "csr", 116 alu.litValue() -> "alu", 117 mul.litValue() -> "mul", 118 div.litValue() -> "div", 119 fence.litValue() -> "fence", 120 bku.litValue() -> "bku", 121 fmac.litValue() -> "fmac", 122 fmisc.litValue() -> "fmisc", 123 fDivSqrt.litValue() -> "fdiv_fsqrt", 124 ldu.litValue() -> "load", 125 stu.litValue() -> "store", 126 mou.litValue() -> "mou" 127 ) 128 } 129 130 def FuOpTypeWidth = 8 131 object FuOpType { 132 def apply() = UInt(FuOpTypeWidth.W) 133 def X = BitPat("b00000000") 134 } 135 136 // move VipuType and VfpuType into YunSuan/package.scala 137 // object VipuType { 138 // def dummy = 0.U(7.W) 139 // } 140 141 // object VfpuType { 142 // def dummy = 0.U(7.W) 143 // } 144 145 object VlduType { 146 def dummy = 0.U 147 } 148 149 object VstuType { 150 def dummy = 0.U 151 } 152 153 object CommitType { 154 def NORMAL = "b000".U // int/fp 155 def BRANCH = "b001".U // branch 156 def LOAD = "b010".U // load 157 def STORE = "b011".U // store 158 159 def apply() = UInt(3.W) 160 def isFused(commitType: UInt): Bool = commitType(2) 161 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 162 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 163 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 164 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 165 } 166 167 object RedirectLevel { 168 def flushAfter = "b0".U 169 def flush = "b1".U 170 171 def apply() = UInt(1.W) 172 // def isUnconditional(level: UInt) = level(1) 173 def flushItself(level: UInt) = level(0) 174 // def isException(level: UInt) = level(1) && level(0) 175 } 176 177 object ExceptionVec { 178 def apply() = Vec(16, Bool()) 179 } 180 181 object PMAMode { 182 def R = "b1".U << 0 //readable 183 def W = "b1".U << 1 //writeable 184 def X = "b1".U << 2 //executable 185 def I = "b1".U << 3 //cacheable: icache 186 def D = "b1".U << 4 //cacheable: dcache 187 def S = "b1".U << 5 //enable speculative access 188 def A = "b1".U << 6 //enable atomic operation, A imply R & W 189 def C = "b1".U << 7 //if it is cacheable is configable 190 def Reserved = "b0".U 191 192 def apply() = UInt(7.W) 193 194 def read(mode: UInt) = mode(0) 195 def write(mode: UInt) = mode(1) 196 def execute(mode: UInt) = mode(2) 197 def icache(mode: UInt) = mode(3) 198 def dcache(mode: UInt) = mode(4) 199 def speculate(mode: UInt) = mode(5) 200 def atomic(mode: UInt) = mode(6) 201 def configable_cache(mode: UInt) = mode(7) 202 203 def strToMode(s: String) = { 204 var result = 0.U(8.W) 205 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 206 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 207 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 208 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 209 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 210 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 211 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 212 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 213 result 214 } 215 } 216 217 218 object CSROpType { 219 def jmp = "b000".U 220 def wrt = "b001".U 221 def set = "b010".U 222 def clr = "b011".U 223 def wfi = "b100".U 224 def wrti = "b101".U 225 def seti = "b110".U 226 def clri = "b111".U 227 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 228 } 229 230 // jump 231 object JumpOpType { 232 def jal = "b00".U 233 def jalr = "b01".U 234 def auipc = "b10".U 235// def call = "b11_011".U 236// def ret = "b11_100".U 237 def jumpOpisJalr(op: UInt) = op(0) 238 def jumpOpisAuipc(op: UInt) = op(1) 239 } 240 241 object FenceOpType { 242 def fence = "b10000".U 243 def sfence = "b10001".U 244 def fencei = "b10010".U 245 def nofence= "b00000".U 246 } 247 248 object ALUOpType { 249 // shift optype 250 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 251 def sll = "b000_0001".U // sll: src1 << src2 252 253 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 254 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 255 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 256 257 def srl = "b000_0101".U // srl: src1 >> src2 258 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 259 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 260 261 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 262 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 263 264 // RV64 32bit optype 265 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 266 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 267 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 268 269 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 270 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 271 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 272 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 273 274 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 275 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 276 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 277 def rolw = "b001_1100".U 278 def rorw = "b001_1101".U 279 280 // ADD-op 281 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 282 def add = "b010_0001".U // add: src1 + src2 283 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 284 285 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 286 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 287 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 288 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 289 290 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 291 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 292 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 293 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 294 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 295 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 296 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 297 298 // SUB-op: src1 - src2 299 def sub = "b011_0000".U 300 def sltu = "b011_0001".U 301 def slt = "b011_0010".U 302 def maxu = "b011_0100".U 303 def minu = "b011_0101".U 304 def max = "b011_0110".U 305 def min = "b011_0111".U 306 307 // branch 308 def beq = "b111_0000".U 309 def bne = "b111_0010".U 310 def blt = "b111_1000".U 311 def bge = "b111_1010".U 312 def bltu = "b111_1100".U 313 def bgeu = "b111_1110".U 314 315 // misc optype 316 def and = "b100_0000".U 317 def andn = "b100_0001".U 318 def or = "b100_0010".U 319 def orn = "b100_0011".U 320 def xor = "b100_0100".U 321 def xnor = "b100_0101".U 322 def orcb = "b100_0110".U 323 324 def sextb = "b100_1000".U 325 def packh = "b100_1001".U 326 def sexth = "b100_1010".U 327 def packw = "b100_1011".U 328 329 def revb = "b101_0000".U 330 def rev8 = "b101_0001".U 331 def pack = "b101_0010".U 332 def orh48 = "b101_0011".U 333 334 def szewl1 = "b101_1000".U 335 def szewl2 = "b101_1001".U 336 def szewl3 = "b101_1010".U 337 def byte2 = "b101_1011".U 338 339 def andlsb = "b110_0000".U 340 def andzexth = "b110_0001".U 341 def orlsb = "b110_0010".U 342 def orzexth = "b110_0011".U 343 def xorlsb = "b110_0100".U 344 def xorzexth = "b110_0101".U 345 def orcblsb = "b110_0110".U 346 def orcbzexth = "b110_0111".U 347 def vsetvli = "b1000_0000".U 348 def vsetvl = "b1000_0001".U 349 def vsetivli = "b1000_0010".U 350 351 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 352 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 353 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 354 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 355 def isBranch(func: UInt) = func(6, 4) === "b111".U 356 def getBranchType(func: UInt) = func(3, 2) 357 def isBranchInvert(func: UInt) = func(1) 358 359 def apply() = UInt(FuOpTypeWidth.W) 360 } 361 362 object MDUOpType { 363 // mul 364 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 365 def mul = "b00000".U 366 def mulh = "b00001".U 367 def mulhsu = "b00010".U 368 def mulhu = "b00011".U 369 def mulw = "b00100".U 370 371 def mulw7 = "b01100".U 372 373 // div 374 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 375 def div = "b10000".U 376 def divu = "b10010".U 377 def rem = "b10001".U 378 def remu = "b10011".U 379 380 def divw = "b10100".U 381 def divuw = "b10110".U 382 def remw = "b10101".U 383 def remuw = "b10111".U 384 385 def isMul(op: UInt) = !op(4) 386 def isDiv(op: UInt) = op(4) 387 388 def isDivSign(op: UInt) = isDiv(op) && !op(1) 389 def isW(op: UInt) = op(2) 390 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 391 def getMulOp(op: UInt) = op(1, 0) 392 } 393 394 object LSUOpType { 395 // load pipeline 396 397 // normal load 398 // Note: bit(1, 0) are size, DO NOT CHANGE 399 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 400 def lb = "b0000".U 401 def lh = "b0001".U 402 def lw = "b0010".U 403 def ld = "b0011".U 404 def lbu = "b0100".U 405 def lhu = "b0101".U 406 def lwu = "b0110".U 407 408 // Zicbop software prefetch 409 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 410 def prefetch_i = "b1000".U // TODO 411 def prefetch_r = "b1001".U 412 def prefetch_w = "b1010".U 413 414 def isPrefetch(op: UInt): Bool = op(3) 415 416 // store pipeline 417 // normal store 418 // bit encoding: | store 00 | size(2bit) | 419 def sb = "b0000".U 420 def sh = "b0001".U 421 def sw = "b0010".U 422 def sd = "b0011".U 423 424 // l1 cache op 425 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 426 def cbo_zero = "b0111".U 427 428 // llc op 429 // bit encoding: | prefetch 11 | suboptype(2bit) | 430 def cbo_clean = "b1100".U 431 def cbo_flush = "b1101".U 432 def cbo_inval = "b1110".U 433 434 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 435 436 // atomics 437 // bit(1, 0) are size 438 // since atomics use a different fu type 439 // so we can safely reuse other load/store's encodings 440 // bit encoding: | optype(4bit) | size (2bit) | 441 def lr_w = "b000010".U 442 def sc_w = "b000110".U 443 def amoswap_w = "b001010".U 444 def amoadd_w = "b001110".U 445 def amoxor_w = "b010010".U 446 def amoand_w = "b010110".U 447 def amoor_w = "b011010".U 448 def amomin_w = "b011110".U 449 def amomax_w = "b100010".U 450 def amominu_w = "b100110".U 451 def amomaxu_w = "b101010".U 452 453 def lr_d = "b000011".U 454 def sc_d = "b000111".U 455 def amoswap_d = "b001011".U 456 def amoadd_d = "b001111".U 457 def amoxor_d = "b010011".U 458 def amoand_d = "b010111".U 459 def amoor_d = "b011011".U 460 def amomin_d = "b011111".U 461 def amomax_d = "b100011".U 462 def amominu_d = "b100111".U 463 def amomaxu_d = "b101011".U 464 465 def size(op: UInt) = op(1,0) 466 } 467 468 object BKUOpType { 469 470 def clmul = "b000000".U 471 def clmulh = "b000001".U 472 def clmulr = "b000010".U 473 def xpermn = "b000100".U 474 def xpermb = "b000101".U 475 476 def clz = "b001000".U 477 def clzw = "b001001".U 478 def ctz = "b001010".U 479 def ctzw = "b001011".U 480 def cpop = "b001100".U 481 def cpopw = "b001101".U 482 483 // 01xxxx is reserve 484 def aes64es = "b100000".U 485 def aes64esm = "b100001".U 486 def aes64ds = "b100010".U 487 def aes64dsm = "b100011".U 488 def aes64im = "b100100".U 489 def aes64ks1i = "b100101".U 490 def aes64ks2 = "b100110".U 491 492 // merge to two instruction sm4ks & sm4ed 493 def sm4ed0 = "b101000".U 494 def sm4ed1 = "b101001".U 495 def sm4ed2 = "b101010".U 496 def sm4ed3 = "b101011".U 497 def sm4ks0 = "b101100".U 498 def sm4ks1 = "b101101".U 499 def sm4ks2 = "b101110".U 500 def sm4ks3 = "b101111".U 501 502 def sha256sum0 = "b110000".U 503 def sha256sum1 = "b110001".U 504 def sha256sig0 = "b110010".U 505 def sha256sig1 = "b110011".U 506 def sha512sum0 = "b110100".U 507 def sha512sum1 = "b110101".U 508 def sha512sig0 = "b110110".U 509 def sha512sig1 = "b110111".U 510 511 def sm3p0 = "b111000".U 512 def sm3p1 = "b111001".U 513 } 514 515 object BTBtype { 516 def B = "b00".U // branch 517 def J = "b01".U // jump 518 def I = "b10".U // indirect 519 def R = "b11".U // return 520 521 def apply() = UInt(2.W) 522 } 523 524 object SelImm { 525 def IMM_X = "b0111".U 526 def IMM_S = "b0000".U 527 def IMM_SB = "b0001".U 528 def IMM_U = "b0010".U 529 def IMM_UJ = "b0011".U 530 def IMM_I = "b0100".U 531 def IMM_Z = "b0101".U 532 def INVALID_INSTR = "b0110".U 533 def IMM_B6 = "b1000".U 534 535 def IMM_OPIVIS = "b1001".U 536 def IMM_OPIVIU = "b1010".U 537 def IMM_VSETVLI = "b1100".U 538 def IMM_VSETIVLI = "b1101".U 539 540 def X = BitPat("b0000") 541 542 def apply() = UInt(4.W) 543 } 544 545 object ExceptionNO { 546 def instrAddrMisaligned = 0 547 def instrAccessFault = 1 548 def illegalInstr = 2 549 def breakPoint = 3 550 def loadAddrMisaligned = 4 551 def loadAccessFault = 5 552 def storeAddrMisaligned = 6 553 def storeAccessFault = 7 554 def ecallU = 8 555 def ecallS = 9 556 def ecallM = 11 557 def instrPageFault = 12 558 def loadPageFault = 13 559 // def singleStep = 14 560 def storePageFault = 15 561 def priorities = Seq( 562 breakPoint, // TODO: different BP has different priority 563 instrPageFault, 564 instrAccessFault, 565 illegalInstr, 566 instrAddrMisaligned, 567 ecallM, ecallS, ecallU, 568 storeAddrMisaligned, 569 loadAddrMisaligned, 570 storePageFault, 571 loadPageFault, 572 storeAccessFault, 573 loadAccessFault 574 ) 575 def all = priorities.distinct.sorted 576 def frontendSet = Seq( 577 instrAddrMisaligned, 578 instrAccessFault, 579 illegalInstr, 580 instrPageFault 581 ) 582 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 583 val new_vec = Wire(ExceptionVec()) 584 new_vec.foreach(_ := false.B) 585 select.foreach(i => new_vec(i) := vec(i)) 586 new_vec 587 } 588 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 589 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 590 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 591 partialSelect(vec, fuConfig.exceptionOut) 592 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 593 partialSelect(vec, exuConfig.exceptionOut) 594 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 595 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 596 } 597 598 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 599 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 600 def aluGen(p: Parameters) = new Alu()(p) 601 def bkuGen(p: Parameters) = new Bku()(p) 602 def jmpGen(p: Parameters) = new Jump()(p) 603 def fenceGen(p: Parameters) = new Fence()(p) 604 def csrGen(p: Parameters) = new CSR()(p) 605 def i2fGen(p: Parameters) = new IntToFP()(p) 606 def fmacGen(p: Parameters) = new FMA()(p) 607 def f2iGen(p: Parameters) = new FPToInt()(p) 608 def f2fGen(p: Parameters) = new FPToFP()(p) 609 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 610 def stdGen(p: Parameters) = new Std()(p) 611 def mouDataGen(p: Parameters) = new Std()(p) 612 def vipuGen(p: Parameters) = new VIPU()(p) 613 614 def f2iSel(uop: MicroOp): Bool = { 615 uop.ctrl.rfWen 616 } 617 618 def i2fSel(uop: MicroOp): Bool = { 619 uop.ctrl.fpu.fromInt 620 } 621 622 def f2fSel(uop: MicroOp): Bool = { 623 val ctrl = uop.ctrl.fpu 624 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 625 } 626 627 def fdivSqrtSel(uop: MicroOp): Bool = { 628 val ctrl = uop.ctrl.fpu 629 ctrl.div || ctrl.sqrt 630 } 631 632 val aluCfg = FuConfig( 633 name = "alu", 634 fuGen = aluGen, 635 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 636 fuType = FuType.alu, 637 numIntSrc = 2, 638 numFpSrc = 0, 639 writeIntRf = true, 640 writeFpRf = false, 641 hasRedirect = true, 642 ) 643 644 val jmpCfg = FuConfig( 645 name = "jmp", 646 fuGen = jmpGen, 647 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 648 fuType = FuType.jmp, 649 numIntSrc = 1, 650 numFpSrc = 0, 651 writeIntRf = true, 652 writeFpRf = false, 653 hasRedirect = true, 654 ) 655 656 val fenceCfg = FuConfig( 657 name = "fence", 658 fuGen = fenceGen, 659 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 660 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 661 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 662 flushPipe = true 663 ) 664 665 val csrCfg = FuConfig( 666 name = "csr", 667 fuGen = csrGen, 668 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 669 fuType = FuType.csr, 670 numIntSrc = 1, 671 numFpSrc = 0, 672 writeIntRf = true, 673 writeFpRf = false, 674 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 675 flushPipe = true 676 ) 677 678 val i2fCfg = FuConfig( 679 name = "i2f", 680 fuGen = i2fGen, 681 fuSel = i2fSel, 682 FuType.i2f, 683 numIntSrc = 1, 684 numFpSrc = 0, 685 writeIntRf = false, 686 writeFpRf = true, 687 writeFflags = true, 688 latency = CertainLatency(2), 689 fastUopOut = true, fastImplemented = true 690 ) 691 692 val divCfg = FuConfig( 693 name = "div", 694 fuGen = dividerGen, 695 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 696 FuType.div, 697 2, 698 0, 699 writeIntRf = true, 700 writeFpRf = false, 701 latency = UncertainLatency(), 702 fastUopOut = true, 703 fastImplemented = true, 704 hasInputBuffer = (true, 4, true) 705 ) 706 707 val mulCfg = FuConfig( 708 name = "mul", 709 fuGen = multiplierGen, 710 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 711 FuType.mul, 712 2, 713 0, 714 writeIntRf = true, 715 writeFpRf = false, 716 latency = CertainLatency(2), 717 fastUopOut = true, 718 fastImplemented = true 719 ) 720 721 val bkuCfg = FuConfig( 722 name = "bku", 723 fuGen = bkuGen, 724 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 725 fuType = FuType.bku, 726 numIntSrc = 2, 727 numFpSrc = 0, 728 writeIntRf = true, 729 writeFpRf = false, 730 latency = CertainLatency(1), 731 fastUopOut = true, 732 fastImplemented = true 733 ) 734 735 val fmacCfg = FuConfig( 736 name = "fmac", 737 fuGen = fmacGen, 738 fuSel = _ => true.B, 739 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 740 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 741 ) 742 743 val f2iCfg = FuConfig( 744 name = "f2i", 745 fuGen = f2iGen, 746 fuSel = f2iSel, 747 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 748 fastUopOut = true, fastImplemented = true 749 ) 750 751 val f2fCfg = FuConfig( 752 name = "f2f", 753 fuGen = f2fGen, 754 fuSel = f2fSel, 755 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 756 fastUopOut = true, fastImplemented = true 757 ) 758 759 val fdivSqrtCfg = FuConfig( 760 name = "fdivSqrt", 761 fuGen = fdivSqrtGen, 762 fuSel = fdivSqrtSel, 763 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 764 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 765 ) 766 767 val lduCfg = FuConfig( 768 "ldu", 769 null, // DontCare 770 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 771 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 772 latency = UncertainLatency(), 773 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 774 flushPipe = true, 775 replayInst = true, 776 hasLoadError = true 777 ) 778 779 val staCfg = FuConfig( 780 "sta", 781 null, 782 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 783 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 784 latency = UncertainLatency(), 785 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 786 ) 787 788 val stdCfg = FuConfig( 789 "std", 790 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 791 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 792 ) 793 794 val mouCfg = FuConfig( 795 "mou", 796 null, 797 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 798 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 799 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 800 ) 801 802 val mouDataCfg = FuConfig( 803 "mou", 804 mouDataGen, 805 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 806 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 807 latency = UncertainLatency() 808 ) 809 810 val vipuCfg = FuConfig( 811 name = "vipu", 812 fuGen = vipuGen, 813 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 814 fuType = FuType.vipu, 815 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 816 numVecSrc = 2, writeVecRf = true, 817 fastUopOut = true, // TODO: check 818 fastImplemented = true, //TODO: check 819 ) 820 821 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 822 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 823 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 824 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 825 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 826 val FmiscExeUnitCfg = ExuConfig( 827 "FmiscExeUnit", 828 "Fp", 829 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 830 Int.MaxValue, 1 831 ) 832 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 833 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 834 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 835 836 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 837 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 838 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 839 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 840 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 841 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 842 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 843 844 val aluRSMod = new RSMod( 845 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 846 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 847 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 848 ) 849 val fmaRSMod = new RSMod( 850 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 851 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 852 ) 853 val fmiscRSMod = new RSMod( 854 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 855 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 856 ) 857 val jumpRSMod = new RSMod( 858 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 859 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 860 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 861 ) 862 val loadRSMod = new RSMod( 863 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 864 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 865 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 866 ) 867 val mulRSMod = new RSMod( 868 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 869 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 870 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 871 ) 872 val staRSMod = new RSMod( 873 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 874 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 875 ) 876 val stdRSMod = new RSMod( 877 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 878 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 879 ) 880} 881