1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b???") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isFp(srcType: UInt) = srcType(1) 46 def isVp(srcType: UInt) = srcType(2) 47 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 48 49 def apply() = UInt(3.W) 50 } 51 52 object SrcState { 53 def busy = "b0".U 54 def rdy = "b1".U 55 // def specRdy = "b10".U // speculative ready, for future use 56 def apply() = UInt(1.W) 57 } 58 59 // Todo: Use OH instead 60 object FuType { 61 def jmp = "b0000".U 62 def i2f = "b0001".U 63 def csr = "b0010".U 64 def alu = "b0110".U 65 def mul = "b0100".U 66 def div = "b0101".U 67 def fence = "b0011".U 68 def bku = "b0111".U 69 70 def fmac = "b1000".U 71 def fmisc = "b1011".U 72 def fDivSqrt = "b1010".U 73 74 def ldu = "b1100".U 75 def stu = "b1101".U 76 def mou = "b1111".U // for amo, lr, sc, fence 77 def vipu = "b10000".U 78 def vfpu = "b11000".U 79 def vldu = "b11100".U 80 def vstu = "b11101".U 81 def X = BitPat("b????") 82 83 def num = 18 84 85 def apply() = UInt(log2Up(num).W) 86 87 def isIntExu(fuType: UInt) = !fuType(3) 88 def isJumpExu(fuType: UInt) = fuType === jmp 89 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 90 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 91 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 92 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 93 def isAMO(fuType: UInt) = fuType(1) 94 def isFence(fuType: UInt) = fuType === fence 95 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 96 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 97 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 98 99 100 def jmpCanAccept(fuType: UInt) = !fuType(2) 101 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 102 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 103 104 def fmacCanAccept(fuType: UInt) = !fuType(1) 105 def fmiscCanAccept(fuType: UInt) = fuType(1) 106 107 def loadCanAccept(fuType: UInt) = !fuType(0) 108 def storeCanAccept(fuType: UInt) = fuType(0) 109 110 def storeIsAMO(fuType: UInt) = fuType(1) 111 112 val functionNameMap = Map( 113 jmp.litValue() -> "jmp", 114 i2f.litValue() -> "int_to_float", 115 csr.litValue() -> "csr", 116 alu.litValue() -> "alu", 117 mul.litValue() -> "mul", 118 div.litValue() -> "div", 119 fence.litValue() -> "fence", 120 bku.litValue() -> "bku", 121 fmac.litValue() -> "fmac", 122 fmisc.litValue() -> "fmisc", 123 fDivSqrt.litValue() -> "fdiv_fsqrt", 124 ldu.litValue() -> "load", 125 stu.litValue() -> "store", 126 mou.litValue() -> "mou" 127 ) 128 } 129 130 object FuOpType { 131 def apply() = UInt(7.W) 132 def X = BitPat("b???????") 133 } 134 135 object VipuType { 136 def dummy = 0.U(7.W) 137 } 138 139 object VfpuType { 140 def dummy = 0.U(7.W) 141 } 142 143 object VlduType { 144 def dummy = 0.U(7.W) 145 } 146 147 object VstuType { 148 def dummy = 0.U(7.W) 149 } 150 151 object CommitType { 152 def NORMAL = "b000".U // int/fp 153 def BRANCH = "b001".U // branch 154 def LOAD = "b010".U // load 155 def STORE = "b011".U // store 156 157 def apply() = UInt(3.W) 158 def isFused(commitType: UInt): Bool = commitType(2) 159 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 160 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 161 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 162 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 163 } 164 165 object RedirectLevel { 166 def flushAfter = "b0".U 167 def flush = "b1".U 168 169 def apply() = UInt(1.W) 170 // def isUnconditional(level: UInt) = level(1) 171 def flushItself(level: UInt) = level(0) 172 // def isException(level: UInt) = level(1) && level(0) 173 } 174 175 object ExceptionVec { 176 def apply() = Vec(16, Bool()) 177 } 178 179 object PMAMode { 180 def R = "b1".U << 0 //readable 181 def W = "b1".U << 1 //writeable 182 def X = "b1".U << 2 //executable 183 def I = "b1".U << 3 //cacheable: icache 184 def D = "b1".U << 4 //cacheable: dcache 185 def S = "b1".U << 5 //enable speculative access 186 def A = "b1".U << 6 //enable atomic operation, A imply R & W 187 def C = "b1".U << 7 //if it is cacheable is configable 188 def Reserved = "b0".U 189 190 def apply() = UInt(7.W) 191 192 def read(mode: UInt) = mode(0) 193 def write(mode: UInt) = mode(1) 194 def execute(mode: UInt) = mode(2) 195 def icache(mode: UInt) = mode(3) 196 def dcache(mode: UInt) = mode(4) 197 def speculate(mode: UInt) = mode(5) 198 def atomic(mode: UInt) = mode(6) 199 def configable_cache(mode: UInt) = mode(7) 200 201 def strToMode(s: String) = { 202 var result = 0.U(8.W) 203 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 204 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 205 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 206 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 207 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 208 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 209 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 210 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 211 result 212 } 213 } 214 215 216 object CSROpType { 217 def jmp = "b000".U 218 def wrt = "b001".U 219 def set = "b010".U 220 def clr = "b011".U 221 def wfi = "b100".U 222 def wrti = "b101".U 223 def seti = "b110".U 224 def clri = "b111".U 225 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 226 } 227 228 // jump 229 object JumpOpType { 230 def jal = "b00".U 231 def jalr = "b01".U 232 def auipc = "b10".U 233// def call = "b11_011".U 234// def ret = "b11_100".U 235 def jumpOpisJalr(op: UInt) = op(0) 236 def jumpOpisAuipc(op: UInt) = op(1) 237 } 238 239 object FenceOpType { 240 def fence = "b10000".U 241 def sfence = "b10001".U 242 def fencei = "b10010".U 243 def nofence= "b00000".U 244 } 245 246 object ALUOpType { 247 // shift optype 248 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 249 def sll = "b000_0001".U // sll: src1 << src2 250 251 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 252 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 253 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 254 255 def srl = "b000_0101".U // srl: src1 >> src2 256 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 257 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 258 259 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 260 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 261 262 // RV64 32bit optype 263 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 264 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 265 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 266 267 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 268 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 269 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 270 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 271 272 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 273 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 274 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 275 def rolw = "b001_1100".U 276 def rorw = "b001_1101".U 277 278 // ADD-op 279 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 280 def add = "b010_0001".U // add: src1 + src2 281 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 282 283 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 284 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 285 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 286 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 287 288 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 289 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 290 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 291 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 292 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 293 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 294 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 295 296 // SUB-op: src1 - src2 297 def sub = "b011_0000".U 298 def sltu = "b011_0001".U 299 def slt = "b011_0010".U 300 def maxu = "b011_0100".U 301 def minu = "b011_0101".U 302 def max = "b011_0110".U 303 def min = "b011_0111".U 304 305 // branch 306 def beq = "b111_0000".U 307 def bne = "b111_0010".U 308 def blt = "b111_1000".U 309 def bge = "b111_1010".U 310 def bltu = "b111_1100".U 311 def bgeu = "b111_1110".U 312 313 // misc optype 314 def and = "b100_0000".U 315 def andn = "b100_0001".U 316 def or = "b100_0010".U 317 def orn = "b100_0011".U 318 def xor = "b100_0100".U 319 def xnor = "b100_0101".U 320 def orcb = "b100_0110".U 321 322 def sextb = "b100_1000".U 323 def packh = "b100_1001".U 324 def sexth = "b100_1010".U 325 def packw = "b100_1011".U 326 327 def revb = "b101_0000".U 328 def rev8 = "b101_0001".U 329 def pack = "b101_0010".U 330 def orh48 = "b101_0011".U 331 332 def szewl1 = "b101_1000".U 333 def szewl2 = "b101_1001".U 334 def szewl3 = "b101_1010".U 335 def byte2 = "b101_1011".U 336 337 def andlsb = "b110_0000".U 338 def andzexth = "b110_0001".U 339 def orlsb = "b110_0010".U 340 def orzexth = "b110_0011".U 341 def xorlsb = "b110_0100".U 342 def xorzexth = "b110_0101".U 343 def orcblsb = "b110_0110".U 344 def orcbzexth = "b110_0111".U 345 346 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 347 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 348 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 349 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 350 def isBranch(func: UInt) = func(6, 4) === "b111".U 351 def getBranchType(func: UInt) = func(3, 2) 352 def isBranchInvert(func: UInt) = func(1) 353 354 def apply() = UInt(7.W) 355 } 356 357 object MDUOpType { 358 // mul 359 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 360 def mul = "b00000".U 361 def mulh = "b00001".U 362 def mulhsu = "b00010".U 363 def mulhu = "b00011".U 364 def mulw = "b00100".U 365 366 def mulw7 = "b01100".U 367 368 // div 369 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 370 def div = "b10000".U 371 def divu = "b10010".U 372 def rem = "b10001".U 373 def remu = "b10011".U 374 375 def divw = "b10100".U 376 def divuw = "b10110".U 377 def remw = "b10101".U 378 def remuw = "b10111".U 379 380 def isMul(op: UInt) = !op(4) 381 def isDiv(op: UInt) = op(4) 382 383 def isDivSign(op: UInt) = isDiv(op) && !op(1) 384 def isW(op: UInt) = op(2) 385 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 386 def getMulOp(op: UInt) = op(1, 0) 387 } 388 389 object LSUOpType { 390 // load pipeline 391 392 // normal load 393 // Note: bit(1, 0) are size, DO NOT CHANGE 394 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 395 def lb = "b0000".U 396 def lh = "b0001".U 397 def lw = "b0010".U 398 def ld = "b0011".U 399 def lbu = "b0100".U 400 def lhu = "b0101".U 401 def lwu = "b0110".U 402 403 // Zicbop software prefetch 404 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 405 def prefetch_i = "b1000".U // TODO 406 def prefetch_r = "b1001".U 407 def prefetch_w = "b1010".U 408 409 def isPrefetch(op: UInt): Bool = op(3) 410 411 // store pipeline 412 // normal store 413 // bit encoding: | store 00 | size(2bit) | 414 def sb = "b0000".U 415 def sh = "b0001".U 416 def sw = "b0010".U 417 def sd = "b0011".U 418 419 // l1 cache op 420 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 421 def cbo_zero = "b0111".U 422 423 // llc op 424 // bit encoding: | prefetch 11 | suboptype(2bit) | 425 def cbo_clean = "b1100".U 426 def cbo_flush = "b1101".U 427 def cbo_inval = "b1110".U 428 429 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 430 431 // atomics 432 // bit(1, 0) are size 433 // since atomics use a different fu type 434 // so we can safely reuse other load/store's encodings 435 // bit encoding: | optype(4bit) | size (2bit) | 436 def lr_w = "b000010".U 437 def sc_w = "b000110".U 438 def amoswap_w = "b001010".U 439 def amoadd_w = "b001110".U 440 def amoxor_w = "b010010".U 441 def amoand_w = "b010110".U 442 def amoor_w = "b011010".U 443 def amomin_w = "b011110".U 444 def amomax_w = "b100010".U 445 def amominu_w = "b100110".U 446 def amomaxu_w = "b101010".U 447 448 def lr_d = "b000011".U 449 def sc_d = "b000111".U 450 def amoswap_d = "b001011".U 451 def amoadd_d = "b001111".U 452 def amoxor_d = "b010011".U 453 def amoand_d = "b010111".U 454 def amoor_d = "b011011".U 455 def amomin_d = "b011111".U 456 def amomax_d = "b100011".U 457 def amominu_d = "b100111".U 458 def amomaxu_d = "b101011".U 459 460 def size(op: UInt) = op(1,0) 461 } 462 463 object BKUOpType { 464 465 def clmul = "b000000".U 466 def clmulh = "b000001".U 467 def clmulr = "b000010".U 468 def xpermn = "b000100".U 469 def xpermb = "b000101".U 470 471 def clz = "b001000".U 472 def clzw = "b001001".U 473 def ctz = "b001010".U 474 def ctzw = "b001011".U 475 def cpop = "b001100".U 476 def cpopw = "b001101".U 477 478 // 01xxxx is reserve 479 def aes64es = "b100000".U 480 def aes64esm = "b100001".U 481 def aes64ds = "b100010".U 482 def aes64dsm = "b100011".U 483 def aes64im = "b100100".U 484 def aes64ks1i = "b100101".U 485 def aes64ks2 = "b100110".U 486 487 // merge to two instruction sm4ks & sm4ed 488 def sm4ed0 = "b101000".U 489 def sm4ed1 = "b101001".U 490 def sm4ed2 = "b101010".U 491 def sm4ed3 = "b101011".U 492 def sm4ks0 = "b101100".U 493 def sm4ks1 = "b101101".U 494 def sm4ks2 = "b101110".U 495 def sm4ks3 = "b101111".U 496 497 def sha256sum0 = "b110000".U 498 def sha256sum1 = "b110001".U 499 def sha256sig0 = "b110010".U 500 def sha256sig1 = "b110011".U 501 def sha512sum0 = "b110100".U 502 def sha512sum1 = "b110101".U 503 def sha512sig0 = "b110110".U 504 def sha512sig1 = "b110111".U 505 506 def sm3p0 = "b111000".U 507 def sm3p1 = "b111001".U 508 } 509 510 object BTBtype { 511 def B = "b00".U // branch 512 def J = "b01".U // jump 513 def I = "b10".U // indirect 514 def R = "b11".U // return 515 516 def apply() = UInt(2.W) 517 } 518 519 object SelImm { 520 def IMM_X = "b0111".U 521 def IMM_S = "b0000".U 522 def IMM_SB = "b0001".U 523 def IMM_U = "b0010".U 524 def IMM_UJ = "b0011".U 525 def IMM_I = "b0100".U 526 def IMM_Z = "b0101".U 527 def INVALID_INSTR = "b0110".U 528 def IMM_B6 = "b1000".U 529 530 def X = BitPat("b????") 531 532 def apply() = UInt(4.W) 533 } 534 535 object ExceptionNO { 536 def instrAddrMisaligned = 0 537 def instrAccessFault = 1 538 def illegalInstr = 2 539 def breakPoint = 3 540 def loadAddrMisaligned = 4 541 def loadAccessFault = 5 542 def storeAddrMisaligned = 6 543 def storeAccessFault = 7 544 def ecallU = 8 545 def ecallS = 9 546 def ecallM = 11 547 def instrPageFault = 12 548 def loadPageFault = 13 549 // def singleStep = 14 550 def storePageFault = 15 551 def priorities = Seq( 552 breakPoint, // TODO: different BP has different priority 553 instrPageFault, 554 instrAccessFault, 555 illegalInstr, 556 instrAddrMisaligned, 557 ecallM, ecallS, ecallU, 558 storeAddrMisaligned, 559 loadAddrMisaligned, 560 storePageFault, 561 loadPageFault, 562 storeAccessFault, 563 loadAccessFault 564 ) 565 def all = priorities.distinct.sorted 566 def frontendSet = Seq( 567 instrAddrMisaligned, 568 instrAccessFault, 569 illegalInstr, 570 instrPageFault 571 ) 572 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 573 val new_vec = Wire(ExceptionVec()) 574 new_vec.foreach(_ := false.B) 575 select.foreach(i => new_vec(i) := vec(i)) 576 new_vec 577 } 578 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 579 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 580 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 581 partialSelect(vec, fuConfig.exceptionOut) 582 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 583 partialSelect(vec, exuConfig.exceptionOut) 584 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 585 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 586 } 587 588 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 589 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 590 def aluGen(p: Parameters) = new Alu()(p) 591 def bkuGen(p: Parameters) = new Bku()(p) 592 def jmpGen(p: Parameters) = new Jump()(p) 593 def fenceGen(p: Parameters) = new Fence()(p) 594 def csrGen(p: Parameters) = new CSR()(p) 595 def i2fGen(p: Parameters) = new IntToFP()(p) 596 def fmacGen(p: Parameters) = new FMA()(p) 597 def f2iGen(p: Parameters) = new FPToInt()(p) 598 def f2fGen(p: Parameters) = new FPToFP()(p) 599 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 600 def stdGen(p: Parameters) = new Std()(p) 601 def mouDataGen(p: Parameters) = new Std()(p) 602 def vipuGen(p: Parameters) = new VIPU()(p) 603 604 def f2iSel(uop: MicroOp): Bool = { 605 uop.ctrl.rfWen 606 } 607 608 def i2fSel(uop: MicroOp): Bool = { 609 uop.ctrl.fpu.fromInt 610 } 611 612 def f2fSel(uop: MicroOp): Bool = { 613 val ctrl = uop.ctrl.fpu 614 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 615 } 616 617 def fdivSqrtSel(uop: MicroOp): Bool = { 618 val ctrl = uop.ctrl.fpu 619 ctrl.div || ctrl.sqrt 620 } 621 622 val aluCfg = FuConfig( 623 name = "alu", 624 fuGen = aluGen, 625 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 626 fuType = FuType.alu, 627 numIntSrc = 2, 628 numFpSrc = 0, 629 writeIntRf = true, 630 writeFpRf = false, 631 hasRedirect = true, 632 ) 633 634 val jmpCfg = FuConfig( 635 name = "jmp", 636 fuGen = jmpGen, 637 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 638 fuType = FuType.jmp, 639 numIntSrc = 1, 640 numFpSrc = 0, 641 writeIntRf = true, 642 writeFpRf = false, 643 hasRedirect = true, 644 ) 645 646 val fenceCfg = FuConfig( 647 name = "fence", 648 fuGen = fenceGen, 649 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 650 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 651 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 652 flushPipe = true 653 ) 654 655 val csrCfg = FuConfig( 656 name = "csr", 657 fuGen = csrGen, 658 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 659 fuType = FuType.csr, 660 numIntSrc = 1, 661 numFpSrc = 0, 662 writeIntRf = true, 663 writeFpRf = false, 664 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 665 flushPipe = true 666 ) 667 668 val i2fCfg = FuConfig( 669 name = "i2f", 670 fuGen = i2fGen, 671 fuSel = i2fSel, 672 FuType.i2f, 673 numIntSrc = 1, 674 numFpSrc = 0, 675 writeIntRf = false, 676 writeFpRf = true, 677 writeFflags = true, 678 latency = CertainLatency(2), 679 fastUopOut = true, fastImplemented = true 680 ) 681 682 val divCfg = FuConfig( 683 name = "div", 684 fuGen = dividerGen, 685 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 686 FuType.div, 687 2, 688 0, 689 writeIntRf = true, 690 writeFpRf = false, 691 latency = UncertainLatency(), 692 fastUopOut = true, 693 fastImplemented = true, 694 hasInputBuffer = (true, 4, true) 695 ) 696 697 val mulCfg = FuConfig( 698 name = "mul", 699 fuGen = multiplierGen, 700 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 701 FuType.mul, 702 2, 703 0, 704 writeIntRf = true, 705 writeFpRf = false, 706 latency = CertainLatency(2), 707 fastUopOut = true, 708 fastImplemented = true 709 ) 710 711 val bkuCfg = FuConfig( 712 name = "bku", 713 fuGen = bkuGen, 714 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 715 fuType = FuType.bku, 716 numIntSrc = 2, 717 numFpSrc = 0, 718 writeIntRf = true, 719 writeFpRf = false, 720 latency = CertainLatency(1), 721 fastUopOut = true, 722 fastImplemented = true 723 ) 724 725 val fmacCfg = FuConfig( 726 name = "fmac", 727 fuGen = fmacGen, 728 fuSel = _ => true.B, 729 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 730 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 731 ) 732 733 val f2iCfg = FuConfig( 734 name = "f2i", 735 fuGen = f2iGen, 736 fuSel = f2iSel, 737 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 738 fastUopOut = true, fastImplemented = true 739 ) 740 741 val f2fCfg = FuConfig( 742 name = "f2f", 743 fuGen = f2fGen, 744 fuSel = f2fSel, 745 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 746 fastUopOut = true, fastImplemented = true 747 ) 748 749 val fdivSqrtCfg = FuConfig( 750 name = "fdivSqrt", 751 fuGen = fdivSqrtGen, 752 fuSel = fdivSqrtSel, 753 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 754 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 755 ) 756 757 val lduCfg = FuConfig( 758 "ldu", 759 null, // DontCare 760 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 761 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 762 latency = UncertainLatency(), 763 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 764 flushPipe = true, 765 replayInst = true, 766 hasLoadError = true 767 ) 768 769 val staCfg = FuConfig( 770 "sta", 771 null, 772 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 773 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 774 latency = UncertainLatency(), 775 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 776 ) 777 778 val stdCfg = FuConfig( 779 "std", 780 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 781 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 782 ) 783 784 val mouCfg = FuConfig( 785 "mou", 786 null, 787 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 788 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 789 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 790 ) 791 792 val mouDataCfg = FuConfig( 793 "mou", 794 mouDataGen, 795 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 796 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 797 latency = UncertainLatency() 798 ) 799 800 val vipuCfg = FuConfig( 801 name = "vipu", 802 fuGen = vipuGen, 803 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 804 fuType = FuType.vipu, 805 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 806 numVecSrc = 2, writeVecRf = true, 807 fastUopOut = true, // TODO: check 808 fastImplemented = true, //TODO: check 809 ) 810 811 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 812 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 813 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 814 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 815 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 816 val FmiscExeUnitCfg = ExuConfig( 817 "FmiscExeUnit", 818 "Fp", 819 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 820 Int.MaxValue, 1 821 ) 822 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 823 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 824 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 825 826 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 827 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 828 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 829 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 830 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 831 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 832 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 833 834 val aluRSMod = new RSMod( 835 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 836 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 837 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 838 ) 839 val fmaRSMod = new RSMod( 840 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 841 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 842 ) 843 val fmiscRSMod = new RSMod( 844 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 845 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 846 ) 847 val jumpRSMod = new RSMod( 848 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 849 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 850 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 851 ) 852 val loadRSMod = new RSMod( 853 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 854 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 855 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 856 ) 857 val mulRSMod = new RSMod( 858 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 859 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 860 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 861 ) 862 val staRSMod = new RSMod( 863 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 864 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 865 ) 866 val stdRSMod = new RSMod( 867 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 868 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 869 ) 870} 871