1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.tile.XLen 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType===fp 40 def isPcImm(srcType: UInt) = srcType(0) 41 def isRegFp(srcType: UInt) = !srcType(0) 42 43 def apply() = UInt(2.W) 44 } 45 46 object SrcState { 47 def busy = "b0".U 48 def rdy = "b1".U 49 // def specRdy = "b10".U // speculative ready, for future use 50 def apply() = UInt(1.W) 51 } 52 53 object FuType { 54 def jmp = "b0000".U 55 def i2f = "b0001".U 56 def csr = "b0010".U 57 def alu = "b0110".U 58 def mul = "b0100".U 59 def div = "b0101".U 60 def fence = "b0011".U 61 def bmu = "b0111".U 62 63 def fmac = "b1000".U 64 def fmisc = "b1011".U 65 def fDivSqrt = "b1010".U 66 67 def ldu = "b1100".U 68 def stu = "b1101".U 69 def mou = "b1111".U // for amo, lr, sc, fence 70 71 def num = 14 72 73 def apply() = UInt(log2Up(num).W) 74 75 def isIntExu(fuType: UInt) = !fuType(3) 76 def isJumpExu(fuType: UInt) = fuType === jmp 77 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 78 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 79 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 80 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 81 def isAMO(fuType: UInt) = fuType(1) 82 83 def jmpCanAccept(fuType: UInt) = !fuType(2) 84 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 85 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 86 87 def fmacCanAccept(fuType: UInt) = !fuType(1) 88 def fmiscCanAccept(fuType: UInt) = fuType(1) 89 90 def loadCanAccept(fuType: UInt) = !fuType(0) 91 def storeCanAccept(fuType: UInt) = fuType(0) 92 93 def storeIsAMO(fuType: UInt) = fuType(1) 94 95 val functionNameMap = Map( 96 jmp.litValue() -> "jmp", 97 i2f.litValue() -> "int to float", 98 csr.litValue() -> "csr", 99 alu.litValue() -> "alu", 100 mul.litValue() -> "mul", 101 div.litValue() -> "div", 102 fence.litValue() -> "fence", 103 fmac.litValue() -> "fmac", 104 fmisc.litValue() -> "fmisc", 105 fDivSqrt.litValue() -> "fdiv/fsqrt", 106 ldu.litValue() -> "load", 107 stu.litValue() -> "store" 108 ) 109 110 } 111 112 object FuOpType { 113 def apply() = UInt(8.W) 114 } 115 116 object CommitType { 117 def NORMAL = "b00".U // int/fp 118 def BRANCH = "b01".U // branch 119 def LOAD = "b10".U // load 120 def STORE = "b11".U // store 121 122 def apply() = UInt(2.W) 123 def isLoadStore(commitType: UInt) = commitType(1) 124 def lsInstIsStore(commitType: UInt) = commitType(0) 125 def isStore(commitType: UInt) = isLoadStore(commitType) && lsInstIsStore(commitType) 126 def isBranch(commitType: UInt) = commitType(0) && !commitType(1) 127 } 128 129 object RedirectLevel { 130 def flushAfter = "b0".U 131 def flush = "b1".U 132 133 def apply() = UInt(1.W) 134 // def isUnconditional(level: UInt) = level(1) 135 def flushItself(level: UInt) = level(0) 136 // def isException(level: UInt) = level(1) && level(0) 137 } 138 139 object ExceptionVec { 140 def apply() = Vec(16, Bool()) 141 } 142 143 object PMAMode { 144 def R = "b1".U << 0 //readable 145 def W = "b1".U << 1 //writeable 146 def X = "b1".U << 2 //executable 147 def I = "b1".U << 3 //cacheable: icache 148 def D = "b1".U << 4 //cacheable: dcache 149 def S = "b1".U << 5 //enable speculative access 150 def A = "b1".U << 6 //enable atomic operation, A imply R & W 151 def C = "b1".U << 7 //if it is cacheable is configable 152 def Reserved = "b0".U 153 154 def apply() = UInt(7.W) 155 156 def read(mode: UInt) = mode(0) 157 def write(mode: UInt) = mode(1) 158 def execute(mode: UInt) = mode(2) 159 def icache(mode: UInt) = mode(3) 160 def dcache(mode: UInt) = mode(4) 161 def speculate(mode: UInt) = mode(5) 162 def atomic(mode: UInt) = mode(6) 163 def configable_cache(mode: UInt) = mode(7) 164 165 def strToMode(s: String) = { 166 var result = 0.U(8.W) 167 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 168 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 169 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 170 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 171 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 172 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 173 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 174 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 175 result 176 } 177 } 178 179 180 object CSROpType { 181 def jmp = "b000".U 182 def wrt = "b001".U 183 def set = "b010".U 184 def clr = "b011".U 185 def wrti = "b101".U 186 def seti = "b110".U 187 def clri = "b111".U 188 } 189 190 // jump 191 object JumpOpType { 192 def jal = "b00".U 193 def jalr = "b01".U 194 def auipc = "b10".U 195// def call = "b11_011".U 196// def ret = "b11_100".U 197 def jumpOpisJalr(op: UInt) = op(0) 198 def jumpOpisAuipc(op: UInt) = op(1) 199 } 200 201 object FenceOpType { 202 def fence = "b10000".U 203 def sfence = "b10001".U 204 def fencei = "b10010".U 205 } 206 207 object ALUOpType { 208 // misc & branch optype 209 def and = "b0_00_00_000".U 210 def andn = "b0_00_00_001".U 211 def or = "b0_00_00_010".U 212 def orn = "b0_00_00_011".U 213 def xor = "b0_00_00_100".U 214 def xnor = "b0_00_00_101".U 215 216 def sext_b = "b0_00_01_000".U 217 def sext_h = "b0_00_01_001".U 218 def zext_h = "b0_00_01_010".U 219 def orc_b = "b0_00_01_100".U 220 def rev8 = "b0_00_01_101".U 221 222 def beq = "b0_00_10_000".U 223 def bne = "b0_00_10_001".U 224 def blt = "b0_00_10_100".U 225 def bge = "b0_00_10_101".U 226 def bltu = "b0_00_10_110".U 227 def bgeu = "b0_00_10_111".U 228 229 def slt = "b0_00_11_000".U 230 def sltu = "b0_00_11_010".U 231 def max = "b0_00_11_100".U 232 def min = "b0_00_11_101".U 233 def maxu = "b0_00_11_110".U 234 def minu = "b0_00_11_111".U 235 236 // add & sub optype 237 def add = "b0_01_00_000".U 238 def add_uw = "b0_01_00_001".U 239 def sh1add = "b0_01_00_010".U 240 def sh1add_uw = "b0_01_00_011".U 241 def sh2add = "b0_01_00_100".U 242 def sh2add_uw = "b0_01_00_101".U 243 def sh3add = "b0_01_00_110".U 244 def sh3add_uw = "b0_01_00_111".U 245 246 def sub = "b0_01_01_000".U 247 248 // shift optype 249 def sll = "b0_10_00_000".U 250 def slli_uw = "b0_10_00_001".U 251 def bclr = "b0_10_00_100".U 252 def binv = "b0_10_00_101".U 253 def bset = "b0_10_00_110".U 254 def bext = "b0_10_00_111".U 255 256 def srl = "b0_10_01_010".U 257 def sra = "b0_10_01_011".U 258 259 def rol = "b0_10_10_000".U 260 261 def ror = "b0_10_11_000".U 262 263 // count optype 264 def clz = "b0_11_00_000".U 265 def ctz = "b0_11_00_001".U 266 def cpop = "b0_11_00_010".U 267 268 // RV64 32bit optype 269 def addw = "b1_01_00_000".U 270 def subw = "b1_01_01_000".U 271 def sllw = "b1_10_00_000".U 272 def srlw = "b1_10_01_010".U 273 def sraw = "b1_10_01_011".U 274 def rolw = "b1_10_10_000".U 275 def rorw = "b1_10_11_000".U 276 def clzw = "b1_11_00_000".U 277 def ctzw = "b1_11_00_001".U 278 def cpopw = "b1_11_00_010".U 279 280 def isWordOp(func: UInt) = func(7) 281 def isBranch(func: UInt) = func(6, 3) === "b0010".U 282 def getBranchType(func: UInt) = func(2, 1) 283 def isBranchInvert(func: UInt) = func(0) 284 285 def apply() = UInt(8.W) 286 } 287 288 object MDUOpType { 289 // mul 290 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 291 def mul = "b00000".U 292 def mulh = "b00001".U 293 def mulhsu = "b00010".U 294 def mulhu = "b00011".U 295 def mulw = "b00100".U 296 297 // div 298 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 299 def div = "b01000".U 300 def divu = "b01010".U 301 def rem = "b01001".U 302 def remu = "b01011".U 303 304 def divw = "b01100".U 305 def divuw = "b01110".U 306 def remw = "b01101".U 307 def remuw = "b01111".U 308 309 // fence 310 // bit encoding: | type (2bit) | padding(1bit)(zero) | opcode(2bit) | 311 def fence = "b10000".U 312 def sfence = "b10001".U 313 def fencei = "b10010".U 314 315 // the highest bits are for instruction types 316 def typeMSB = 4 317 def typeLSB = 3 318 319 def MulType = "b00".U 320 def DivType = "b01".U 321 def FenceType = "b10".U 322 323 def isMul(op: UInt) = op(typeMSB, typeLSB) === MulType 324 def isDiv(op: UInt) = op(typeMSB, typeLSB) === DivType 325 def isFence(op: UInt) = op(typeMSB, typeLSB) === FenceType 326 327 def isDivSign(op: UInt) = isDiv(op) && !op(1) 328 def isW(op: UInt) = op(2) 329 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1,0)=/=0.U) 330 def getMulOp(op: UInt) = op(1,0) 331 } 332 333 object LSUOpType { 334 // normal load/store 335 // bit(1, 0) are size 336 def lb = "b000000".U 337 def lh = "b000001".U 338 def lw = "b000010".U 339 def ld = "b000011".U 340 def lbu = "b000100".U 341 def lhu = "b000101".U 342 def lwu = "b000110".U 343 def sb = "b001000".U 344 def sh = "b001001".U 345 def sw = "b001010".U 346 def sd = "b001011".U 347 348 def isLoad(op: UInt): Bool = !op(3) 349 def isStore(op: UInt): Bool = op(3) 350 351 // atomics 352 // bit(1, 0) are size 353 // since atomics use a different fu type 354 // so we can safely reuse other load/store's encodings 355 def lr_w = "b000010".U 356 def sc_w = "b000110".U 357 def amoswap_w = "b001010".U 358 def amoadd_w = "b001110".U 359 def amoxor_w = "b010010".U 360 def amoand_w = "b010110".U 361 def amoor_w = "b011010".U 362 def amomin_w = "b011110".U 363 def amomax_w = "b100010".U 364 def amominu_w = "b100110".U 365 def amomaxu_w = "b101010".U 366 367 def lr_d = "b000011".U 368 def sc_d = "b000111".U 369 def amoswap_d = "b001011".U 370 def amoadd_d = "b001111".U 371 def amoxor_d = "b010011".U 372 def amoand_d = "b010111".U 373 def amoor_d = "b011011".U 374 def amomin_d = "b011111".U 375 def amomax_d = "b100011".U 376 def amominu_d = "b100111".U 377 def amomaxu_d = "b101011".U 378 } 379 380 object BMUOpType { 381 382 def clmul = "b0000".U 383 def clmulh = "b0010".U 384 def clmulr = "b0100".U 385 386 def clz = "b1000".U 387 def clzw = "b1001".U 388 def ctz = "b1010".U 389 def ctzw = "b1011".U 390 def cpop = "b1100".U 391 def cpopw = "b1101".U 392 } 393 394 object BTBtype { 395 def B = "b00".U // branch 396 def J = "b01".U // jump 397 def I = "b10".U // indirect 398 def R = "b11".U // return 399 400 def apply() = UInt(2.W) 401 } 402 403 object SelImm { 404 def IMM_X = "b0111".U 405 def IMM_S = "b0000".U 406 def IMM_SB = "b0001".U 407 def IMM_U = "b0010".U 408 def IMM_UJ = "b0011".U 409 def IMM_I = "b0100".U 410 def IMM_Z = "b0101".U 411 def INVALID_INSTR = "b0110".U 412 def IMM_B6 = "b1000".U 413 414 def apply() = UInt(4.W) 415 } 416 417 def dividerGen(p: Parameters) = new SRT4Divider(p(XLen))(p) 418 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1, Seq(0, 2))(p) 419 def aluGen(p: Parameters) = new Alu()(p) 420 def bmuGen(p: Parameters) = new Bmu()(p) 421 def jmpGen(p: Parameters) = new Jump()(p) 422 def fenceGen(p: Parameters) = new Fence()(p) 423 def csrGen(p: Parameters) = new CSR()(p) 424 def i2fGen(p: Parameters) = new IntToFP()(p) 425 def fmacGen(p: Parameters) = new FMA()(p) 426 def f2iGen(p: Parameters) = new FPToInt()(p) 427 def f2fGen(p: Parameters) = new FPToFP()(p) 428 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 429 def stdGen(p: Parameters) = new Std()(p) 430 431 def f2iSel(x: FunctionUnit): Bool = { 432 x.io.in.bits.uop.ctrl.rfWen 433 } 434 435 def i2fSel(x: FunctionUnit): Bool = { 436 x.io.in.bits.uop.ctrl.fpu.fromInt 437 } 438 439 def f2fSel(x: FunctionUnit): Bool = { 440 val ctrl = x.io.in.bits.uop.ctrl.fpu 441 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 442 } 443 444 def fdivSqrtSel(x: FunctionUnit): Bool = { 445 val ctrl = x.io.in.bits.uop.ctrl.fpu 446 ctrl.div || ctrl.sqrt 447 } 448 449 val aluCfg = FuConfig( 450 fuGen = aluGen, 451 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.alu, 452 fuType = FuType.alu, 453 numIntSrc = 2, 454 numFpSrc = 0, 455 writeIntRf = true, 456 writeFpRf = false, 457 hasRedirect = true, 458 ) 459 460 val jmpCfg = FuConfig( 461 fuGen = jmpGen, 462 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.jmp, 463 fuType = FuType.jmp, 464 numIntSrc = 1, 465 numFpSrc = 0, 466 writeIntRf = true, 467 writeFpRf = false, 468 hasRedirect = true, 469 ) 470 471 val fenceCfg = FuConfig( 472 fuGen = fenceGen, 473 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.fence, 474 FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 475 UncertainLatency() // TODO: need rewrite latency structure, not just this value 476 ) 477 478 val csrCfg = FuConfig( 479 fuGen = csrGen, 480 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.csr, 481 fuType = FuType.csr, 482 numIntSrc = 1, 483 numFpSrc = 0, 484 writeIntRf = true, 485 writeFpRf = false, 486 hasRedirect = false 487 ) 488 489 val i2fCfg = FuConfig( 490 fuGen = i2fGen, 491 fuSel = i2fSel, 492 FuType.i2f, 493 numIntSrc = 1, 494 numFpSrc = 0, 495 writeIntRf = false, 496 writeFpRf = true, 497 hasRedirect = false, 498 UncertainLatency() 499 ) 500 501 val divCfg = FuConfig( 502 fuGen = dividerGen, 503 fuSel = (x: FunctionUnit) => MDUOpType.isDiv(x.io.in.bits.uop.ctrl.fuOpType), 504 FuType.div, 505 2, 506 0, 507 writeIntRf = true, 508 writeFpRf = false, 509 hasRedirect = false, 510 UncertainLatency() 511 ) 512 513 val mulCfg = FuConfig( 514 fuGen = multiplierGen, 515 fuSel = (x: FunctionUnit) => MDUOpType.isMul(x.io.in.bits.uop.ctrl.fuOpType), 516 FuType.mul, 517 2, 518 0, 519 writeIntRf = true, 520 writeFpRf = false, 521 hasRedirect = false, 522 CertainLatency(2) 523 ) 524 525 val bmuCfg = FuConfig( 526 fuGen = bmuGen, 527 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.bmu, 528 fuType = FuType.bmu, 529 numIntSrc = 2, 530 numFpSrc = 0, 531 writeIntRf = true, 532 writeFpRf = false, 533 hasRedirect = false, 534 CertainLatency(1) 535 ) 536 537 val fmacCfg = FuConfig( 538 fuGen = fmacGen, 539 fuSel = _ => true.B, 540 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(4) 541 ) 542 543 val f2iCfg = FuConfig( 544 fuGen = f2iGen, 545 fuSel = f2iSel, 546 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2) 547 ) 548 549 val f2fCfg = FuConfig( 550 fuGen = f2fGen, 551 fuSel = f2fSel, 552 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2) 553 ) 554 555 val fdivSqrtCfg = FuConfig( 556 fuGen = fdivSqrtGen, 557 fuSel = fdivSqrtSel, 558 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency() 559 ) 560 561 val lduCfg = FuConfig( 562 null, // DontCare 563 null, 564 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 565 UncertainLatency() 566 ) 567 568 val staCfg = FuConfig( 569 null, 570 null, 571 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 572 UncertainLatency() 573 ) 574 575 val stdCfg = FuConfig( 576 fuGen = stdGen, fuSel = _ => true.B, FuType.stu, 1, 1, 577 writeIntRf = false, writeFpRf = false, hasRedirect = false, UncertainLatency() 578 ) 579 580 val mouCfg = FuConfig( 581 null, 582 null, 583 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 584 UncertainLatency() 585 ) 586 587 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 588 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 589 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 590 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bmuCfg), 1, Int.MaxValue) 591 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 592 val FmiscExeUnitCfg = ExuConfig( 593 "FmiscExeUnit", 594 "Fp", 595 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 596 Int.MaxValue, 1 597 ) 598 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0) 599 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 600 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 601}