1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b???") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isFp(srcType: UInt) = srcType(1) 46 def isVp(srcType: UInt) = srcType(2) 47 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 48 49 def apply() = UInt(3.W) 50 } 51 52 object SrcState { 53 def busy = "b0".U 54 def rdy = "b1".U 55 // def specRdy = "b10".U // speculative ready, for future use 56 def apply() = UInt(1.W) 57 } 58 59 // Todo: Use OH instead 60 object FuType { 61 def jmp = "b0000".U 62 def i2f = "b0001".U 63 def csr = "b0010".U 64 def alu = "b0110".U 65 def mul = "b0100".U 66 def div = "b0101".U 67 def fence = "b0011".U 68 def bku = "b0111".U 69 70 def fmac = "b1000".U 71 def fmisc = "b1011".U 72 def fDivSqrt = "b1010".U 73 74 def ldu = "b1100".U 75 def stu = "b1101".U 76 def mou = "b1111".U // for amo, lr, sc, fence 77 def vipu = "b10000".U 78 def vfpu = "b11000".U 79 def vldu = "b11100".U 80 def vstu = "b11101".U 81 def X = BitPat("b????") 82 83 def num = 18 84 85 def apply() = UInt(log2Up(num).W) 86 87 def isIntExu(fuType: UInt) = !fuType(3) 88 def isJumpExu(fuType: UInt) = fuType === jmp 89 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 90 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 91 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 92 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 93 def isAMO(fuType: UInt) = fuType(1) 94 def isFence(fuType: UInt) = fuType === fence 95 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 96 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 97 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 98 99 100 def jmpCanAccept(fuType: UInt) = !fuType(2) 101 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 102 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 103 104 def fmacCanAccept(fuType: UInt) = !fuType(1) 105 def fmiscCanAccept(fuType: UInt) = fuType(1) 106 107 def loadCanAccept(fuType: UInt) = !fuType(0) 108 def storeCanAccept(fuType: UInt) = fuType(0) 109 110 def storeIsAMO(fuType: UInt) = fuType(1) 111 112 val functionNameMap = Map( 113 jmp.litValue() -> "jmp", 114 i2f.litValue() -> "int_to_float", 115 csr.litValue() -> "csr", 116 alu.litValue() -> "alu", 117 mul.litValue() -> "mul", 118 div.litValue() -> "div", 119 fence.litValue() -> "fence", 120 bku.litValue() -> "bku", 121 fmac.litValue() -> "fmac", 122 fmisc.litValue() -> "fmisc", 123 fDivSqrt.litValue() -> "fdiv_fsqrt", 124 ldu.litValue() -> "load", 125 stu.litValue() -> "store", 126 mou.litValue() -> "mou" 127 ) 128 } 129 130 object FuOpType { 131 def apply() = UInt(7.W) 132 def X = BitPat("b???????") 133 } 134 135 // move VipuType and VfpuType into YunSuan/package.scala 136 // object VipuType { 137 // def dummy = 0.U(7.W) 138 // } 139 140 // object VfpuType { 141 // def dummy = 0.U(7.W) 142 // } 143 144 object VlduType { 145 def dummy = 0.U(7.W) 146 } 147 148 object VstuType { 149 def dummy = 0.U(7.W) 150 } 151 152 object CommitType { 153 def NORMAL = "b000".U // int/fp 154 def BRANCH = "b001".U // branch 155 def LOAD = "b010".U // load 156 def STORE = "b011".U // store 157 158 def apply() = UInt(3.W) 159 def isFused(commitType: UInt): Bool = commitType(2) 160 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 161 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 162 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 163 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 164 } 165 166 object RedirectLevel { 167 def flushAfter = "b0".U 168 def flush = "b1".U 169 170 def apply() = UInt(1.W) 171 // def isUnconditional(level: UInt) = level(1) 172 def flushItself(level: UInt) = level(0) 173 // def isException(level: UInt) = level(1) && level(0) 174 } 175 176 object ExceptionVec { 177 def apply() = Vec(16, Bool()) 178 } 179 180 object PMAMode { 181 def R = "b1".U << 0 //readable 182 def W = "b1".U << 1 //writeable 183 def X = "b1".U << 2 //executable 184 def I = "b1".U << 3 //cacheable: icache 185 def D = "b1".U << 4 //cacheable: dcache 186 def S = "b1".U << 5 //enable speculative access 187 def A = "b1".U << 6 //enable atomic operation, A imply R & W 188 def C = "b1".U << 7 //if it is cacheable is configable 189 def Reserved = "b0".U 190 191 def apply() = UInt(7.W) 192 193 def read(mode: UInt) = mode(0) 194 def write(mode: UInt) = mode(1) 195 def execute(mode: UInt) = mode(2) 196 def icache(mode: UInt) = mode(3) 197 def dcache(mode: UInt) = mode(4) 198 def speculate(mode: UInt) = mode(5) 199 def atomic(mode: UInt) = mode(6) 200 def configable_cache(mode: UInt) = mode(7) 201 202 def strToMode(s: String) = { 203 var result = 0.U(8.W) 204 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 205 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 206 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 207 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 208 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 209 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 210 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 211 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 212 result 213 } 214 } 215 216 217 object CSROpType { 218 def jmp = "b000".U 219 def wrt = "b001".U 220 def set = "b010".U 221 def clr = "b011".U 222 def wfi = "b100".U 223 def wrti = "b101".U 224 def seti = "b110".U 225 def clri = "b111".U 226 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 227 } 228 229 // jump 230 object JumpOpType { 231 def jal = "b00".U 232 def jalr = "b01".U 233 def auipc = "b10".U 234// def call = "b11_011".U 235// def ret = "b11_100".U 236 def jumpOpisJalr(op: UInt) = op(0) 237 def jumpOpisAuipc(op: UInt) = op(1) 238 } 239 240 object FenceOpType { 241 def fence = "b10000".U 242 def sfence = "b10001".U 243 def fencei = "b10010".U 244 def nofence= "b00000".U 245 } 246 247 object ALUOpType { 248 // shift optype 249 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 250 def sll = "b000_0001".U // sll: src1 << src2 251 252 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 253 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 254 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 255 256 def srl = "b000_0101".U // srl: src1 >> src2 257 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 258 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 259 260 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 261 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 262 263 // RV64 32bit optype 264 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 265 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 266 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 267 268 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 269 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 270 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 271 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 272 273 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 274 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 275 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 276 def rolw = "b001_1100".U 277 def rorw = "b001_1101".U 278 279 // ADD-op 280 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 281 def add = "b010_0001".U // add: src1 + src2 282 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 283 284 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 285 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 286 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 287 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 288 289 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 290 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 291 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 292 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 293 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 294 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 295 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 296 297 // SUB-op: src1 - src2 298 def sub = "b011_0000".U 299 def sltu = "b011_0001".U 300 def slt = "b011_0010".U 301 def maxu = "b011_0100".U 302 def minu = "b011_0101".U 303 def max = "b011_0110".U 304 def min = "b011_0111".U 305 306 // branch 307 def beq = "b111_0000".U 308 def bne = "b111_0010".U 309 def blt = "b111_1000".U 310 def bge = "b111_1010".U 311 def bltu = "b111_1100".U 312 def bgeu = "b111_1110".U 313 314 // misc optype 315 def and = "b100_0000".U 316 def andn = "b100_0001".U 317 def or = "b100_0010".U 318 def orn = "b100_0011".U 319 def xor = "b100_0100".U 320 def xnor = "b100_0101".U 321 def orcb = "b100_0110".U 322 323 def sextb = "b100_1000".U 324 def packh = "b100_1001".U 325 def sexth = "b100_1010".U 326 def packw = "b100_1011".U 327 328 def revb = "b101_0000".U 329 def rev8 = "b101_0001".U 330 def pack = "b101_0010".U 331 def orh48 = "b101_0011".U 332 333 def szewl1 = "b101_1000".U 334 def szewl2 = "b101_1001".U 335 def szewl3 = "b101_1010".U 336 def byte2 = "b101_1011".U 337 338 def andlsb = "b110_0000".U 339 def andzexth = "b110_0001".U 340 def orlsb = "b110_0010".U 341 def orzexth = "b110_0011".U 342 def xorlsb = "b110_0100".U 343 def xorzexth = "b110_0101".U 344 def orcblsb = "b110_0110".U 345 def orcbzexth = "b110_0111".U 346 347 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 348 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 349 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 350 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 351 def isBranch(func: UInt) = func(6, 4) === "b111".U 352 def getBranchType(func: UInt) = func(3, 2) 353 def isBranchInvert(func: UInt) = func(1) 354 355 def apply() = UInt(7.W) 356 } 357 358 object MDUOpType { 359 // mul 360 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 361 def mul = "b00000".U 362 def mulh = "b00001".U 363 def mulhsu = "b00010".U 364 def mulhu = "b00011".U 365 def mulw = "b00100".U 366 367 def mulw7 = "b01100".U 368 369 // div 370 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 371 def div = "b10000".U 372 def divu = "b10010".U 373 def rem = "b10001".U 374 def remu = "b10011".U 375 376 def divw = "b10100".U 377 def divuw = "b10110".U 378 def remw = "b10101".U 379 def remuw = "b10111".U 380 381 def isMul(op: UInt) = !op(4) 382 def isDiv(op: UInt) = op(4) 383 384 def isDivSign(op: UInt) = isDiv(op) && !op(1) 385 def isW(op: UInt) = op(2) 386 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 387 def getMulOp(op: UInt) = op(1, 0) 388 } 389 390 object LSUOpType { 391 // load pipeline 392 393 // normal load 394 // Note: bit(1, 0) are size, DO NOT CHANGE 395 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 396 def lb = "b0000".U 397 def lh = "b0001".U 398 def lw = "b0010".U 399 def ld = "b0011".U 400 def lbu = "b0100".U 401 def lhu = "b0101".U 402 def lwu = "b0110".U 403 404 // Zicbop software prefetch 405 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 406 def prefetch_i = "b1000".U // TODO 407 def prefetch_r = "b1001".U 408 def prefetch_w = "b1010".U 409 410 def isPrefetch(op: UInt): Bool = op(3) 411 412 // store pipeline 413 // normal store 414 // bit encoding: | store 00 | size(2bit) | 415 def sb = "b0000".U 416 def sh = "b0001".U 417 def sw = "b0010".U 418 def sd = "b0011".U 419 420 // l1 cache op 421 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 422 def cbo_zero = "b0111".U 423 424 // llc op 425 // bit encoding: | prefetch 11 | suboptype(2bit) | 426 def cbo_clean = "b1100".U 427 def cbo_flush = "b1101".U 428 def cbo_inval = "b1110".U 429 430 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 431 432 // atomics 433 // bit(1, 0) are size 434 // since atomics use a different fu type 435 // so we can safely reuse other load/store's encodings 436 // bit encoding: | optype(4bit) | size (2bit) | 437 def lr_w = "b000010".U 438 def sc_w = "b000110".U 439 def amoswap_w = "b001010".U 440 def amoadd_w = "b001110".U 441 def amoxor_w = "b010010".U 442 def amoand_w = "b010110".U 443 def amoor_w = "b011010".U 444 def amomin_w = "b011110".U 445 def amomax_w = "b100010".U 446 def amominu_w = "b100110".U 447 def amomaxu_w = "b101010".U 448 449 def lr_d = "b000011".U 450 def sc_d = "b000111".U 451 def amoswap_d = "b001011".U 452 def amoadd_d = "b001111".U 453 def amoxor_d = "b010011".U 454 def amoand_d = "b010111".U 455 def amoor_d = "b011011".U 456 def amomin_d = "b011111".U 457 def amomax_d = "b100011".U 458 def amominu_d = "b100111".U 459 def amomaxu_d = "b101011".U 460 461 def size(op: UInt) = op(1,0) 462 } 463 464 object BKUOpType { 465 466 def clmul = "b000000".U 467 def clmulh = "b000001".U 468 def clmulr = "b000010".U 469 def xpermn = "b000100".U 470 def xpermb = "b000101".U 471 472 def clz = "b001000".U 473 def clzw = "b001001".U 474 def ctz = "b001010".U 475 def ctzw = "b001011".U 476 def cpop = "b001100".U 477 def cpopw = "b001101".U 478 479 // 01xxxx is reserve 480 def aes64es = "b100000".U 481 def aes64esm = "b100001".U 482 def aes64ds = "b100010".U 483 def aes64dsm = "b100011".U 484 def aes64im = "b100100".U 485 def aes64ks1i = "b100101".U 486 def aes64ks2 = "b100110".U 487 488 // merge to two instruction sm4ks & sm4ed 489 def sm4ed0 = "b101000".U 490 def sm4ed1 = "b101001".U 491 def sm4ed2 = "b101010".U 492 def sm4ed3 = "b101011".U 493 def sm4ks0 = "b101100".U 494 def sm4ks1 = "b101101".U 495 def sm4ks2 = "b101110".U 496 def sm4ks3 = "b101111".U 497 498 def sha256sum0 = "b110000".U 499 def sha256sum1 = "b110001".U 500 def sha256sig0 = "b110010".U 501 def sha256sig1 = "b110011".U 502 def sha512sum0 = "b110100".U 503 def sha512sum1 = "b110101".U 504 def sha512sig0 = "b110110".U 505 def sha512sig1 = "b110111".U 506 507 def sm3p0 = "b111000".U 508 def sm3p1 = "b111001".U 509 } 510 511 object BTBtype { 512 def B = "b00".U // branch 513 def J = "b01".U // jump 514 def I = "b10".U // indirect 515 def R = "b11".U // return 516 517 def apply() = UInt(2.W) 518 } 519 520 object SelImm { 521 def IMM_X = "b0111".U 522 def IMM_S = "b0000".U 523 def IMM_SB = "b0001".U 524 def IMM_U = "b0010".U 525 def IMM_UJ = "b0011".U 526 def IMM_I = "b0100".U 527 def IMM_Z = "b0101".U 528 def INVALID_INSTR = "b0110".U 529 def IMM_B6 = "b1000".U 530 531 def IMM_OPIVIS = "b1001".U 532 def IMM_OPIVIU = "b1010".U 533 534 535 def X = BitPat("b????") 536 537 def apply() = UInt(4.W) 538 } 539 540 object ExceptionNO { 541 def instrAddrMisaligned = 0 542 def instrAccessFault = 1 543 def illegalInstr = 2 544 def breakPoint = 3 545 def loadAddrMisaligned = 4 546 def loadAccessFault = 5 547 def storeAddrMisaligned = 6 548 def storeAccessFault = 7 549 def ecallU = 8 550 def ecallS = 9 551 def ecallM = 11 552 def instrPageFault = 12 553 def loadPageFault = 13 554 // def singleStep = 14 555 def storePageFault = 15 556 def priorities = Seq( 557 breakPoint, // TODO: different BP has different priority 558 instrPageFault, 559 instrAccessFault, 560 illegalInstr, 561 instrAddrMisaligned, 562 ecallM, ecallS, ecallU, 563 storeAddrMisaligned, 564 loadAddrMisaligned, 565 storePageFault, 566 loadPageFault, 567 storeAccessFault, 568 loadAccessFault 569 ) 570 def all = priorities.distinct.sorted 571 def frontendSet = Seq( 572 instrAddrMisaligned, 573 instrAccessFault, 574 illegalInstr, 575 instrPageFault 576 ) 577 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 578 val new_vec = Wire(ExceptionVec()) 579 new_vec.foreach(_ := false.B) 580 select.foreach(i => new_vec(i) := vec(i)) 581 new_vec 582 } 583 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 584 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 585 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 586 partialSelect(vec, fuConfig.exceptionOut) 587 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 588 partialSelect(vec, exuConfig.exceptionOut) 589 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 590 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 591 } 592 593 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 594 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 595 def aluGen(p: Parameters) = new Alu()(p) 596 def bkuGen(p: Parameters) = new Bku()(p) 597 def jmpGen(p: Parameters) = new Jump()(p) 598 def fenceGen(p: Parameters) = new Fence()(p) 599 def csrGen(p: Parameters) = new CSR()(p) 600 def i2fGen(p: Parameters) = new IntToFP()(p) 601 def fmacGen(p: Parameters) = new FMA()(p) 602 def f2iGen(p: Parameters) = new FPToInt()(p) 603 def f2fGen(p: Parameters) = new FPToFP()(p) 604 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 605 def stdGen(p: Parameters) = new Std()(p) 606 def mouDataGen(p: Parameters) = new Std()(p) 607 def vipuGen(p: Parameters) = new VIPU()(p) 608 609 def f2iSel(uop: MicroOp): Bool = { 610 uop.ctrl.rfWen 611 } 612 613 def i2fSel(uop: MicroOp): Bool = { 614 uop.ctrl.fpu.fromInt 615 } 616 617 def f2fSel(uop: MicroOp): Bool = { 618 val ctrl = uop.ctrl.fpu 619 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 620 } 621 622 def fdivSqrtSel(uop: MicroOp): Bool = { 623 val ctrl = uop.ctrl.fpu 624 ctrl.div || ctrl.sqrt 625 } 626 627 val aluCfg = FuConfig( 628 name = "alu", 629 fuGen = aluGen, 630 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 631 fuType = FuType.alu, 632 numIntSrc = 2, 633 numFpSrc = 0, 634 writeIntRf = true, 635 writeFpRf = false, 636 hasRedirect = true, 637 ) 638 639 val jmpCfg = FuConfig( 640 name = "jmp", 641 fuGen = jmpGen, 642 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 643 fuType = FuType.jmp, 644 numIntSrc = 1, 645 numFpSrc = 0, 646 writeIntRf = true, 647 writeFpRf = false, 648 hasRedirect = true, 649 ) 650 651 val fenceCfg = FuConfig( 652 name = "fence", 653 fuGen = fenceGen, 654 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 655 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 656 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 657 flushPipe = true 658 ) 659 660 val csrCfg = FuConfig( 661 name = "csr", 662 fuGen = csrGen, 663 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 664 fuType = FuType.csr, 665 numIntSrc = 1, 666 numFpSrc = 0, 667 writeIntRf = true, 668 writeFpRf = false, 669 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 670 flushPipe = true 671 ) 672 673 val i2fCfg = FuConfig( 674 name = "i2f", 675 fuGen = i2fGen, 676 fuSel = i2fSel, 677 FuType.i2f, 678 numIntSrc = 1, 679 numFpSrc = 0, 680 writeIntRf = false, 681 writeFpRf = true, 682 writeFflags = true, 683 latency = CertainLatency(2), 684 fastUopOut = true, fastImplemented = true 685 ) 686 687 val divCfg = FuConfig( 688 name = "div", 689 fuGen = dividerGen, 690 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 691 FuType.div, 692 2, 693 0, 694 writeIntRf = true, 695 writeFpRf = false, 696 latency = UncertainLatency(), 697 fastUopOut = true, 698 fastImplemented = true, 699 hasInputBuffer = (true, 4, true) 700 ) 701 702 val mulCfg = FuConfig( 703 name = "mul", 704 fuGen = multiplierGen, 705 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 706 FuType.mul, 707 2, 708 0, 709 writeIntRf = true, 710 writeFpRf = false, 711 latency = CertainLatency(2), 712 fastUopOut = true, 713 fastImplemented = true 714 ) 715 716 val bkuCfg = FuConfig( 717 name = "bku", 718 fuGen = bkuGen, 719 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 720 fuType = FuType.bku, 721 numIntSrc = 2, 722 numFpSrc = 0, 723 writeIntRf = true, 724 writeFpRf = false, 725 latency = CertainLatency(1), 726 fastUopOut = true, 727 fastImplemented = true 728 ) 729 730 val fmacCfg = FuConfig( 731 name = "fmac", 732 fuGen = fmacGen, 733 fuSel = _ => true.B, 734 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 735 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 736 ) 737 738 val f2iCfg = FuConfig( 739 name = "f2i", 740 fuGen = f2iGen, 741 fuSel = f2iSel, 742 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 743 fastUopOut = true, fastImplemented = true 744 ) 745 746 val f2fCfg = FuConfig( 747 name = "f2f", 748 fuGen = f2fGen, 749 fuSel = f2fSel, 750 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 751 fastUopOut = true, fastImplemented = true 752 ) 753 754 val fdivSqrtCfg = FuConfig( 755 name = "fdivSqrt", 756 fuGen = fdivSqrtGen, 757 fuSel = fdivSqrtSel, 758 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 759 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 760 ) 761 762 val lduCfg = FuConfig( 763 "ldu", 764 null, // DontCare 765 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 766 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 767 latency = UncertainLatency(), 768 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 769 flushPipe = true, 770 replayInst = true, 771 hasLoadError = true 772 ) 773 774 val staCfg = FuConfig( 775 "sta", 776 null, 777 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 778 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 779 latency = UncertainLatency(), 780 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 781 ) 782 783 val stdCfg = FuConfig( 784 "std", 785 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 786 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 787 ) 788 789 val mouCfg = FuConfig( 790 "mou", 791 null, 792 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 793 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 794 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 795 ) 796 797 val mouDataCfg = FuConfig( 798 "mou", 799 mouDataGen, 800 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 801 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 802 latency = UncertainLatency() 803 ) 804 805 val vipuCfg = FuConfig( 806 name = "vipu", 807 fuGen = vipuGen, 808 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 809 fuType = FuType.vipu, 810 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 811 numVecSrc = 2, writeVecRf = true, 812 fastUopOut = true, // TODO: check 813 fastImplemented = true, //TODO: check 814 ) 815 816 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 817 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 818 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 819 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 820 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 821 val FmiscExeUnitCfg = ExuConfig( 822 "FmiscExeUnit", 823 "Fp", 824 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 825 Int.MaxValue, 1 826 ) 827 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 828 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 829 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 830 831 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 832 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 833 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 834 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 835 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 836 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 837 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 838 839 val aluRSMod = new RSMod( 840 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 841 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 842 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 843 ) 844 val fmaRSMod = new RSMod( 845 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 846 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 847 ) 848 val fmiscRSMod = new RSMod( 849 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 850 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 851 ) 852 val jumpRSMod = new RSMod( 853 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 854 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 855 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 856 ) 857 val loadRSMod = new RSMod( 858 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 859 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 860 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 861 ) 862 val mulRSMod = new RSMod( 863 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 864 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 865 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 866 ) 867 val staRSMod = new RSMod( 868 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 869 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 870 ) 871 val stdRSMod = new RSMod( 872 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 873 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 874 ) 875} 876