1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27import xiangshan.backend.decode.{Imm, ImmUnion} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 def no = "b000".U // this src read no reg but cannot be Any value 37 38 // alias 39 def reg = this.xp 40 def DC = imm // Don't Care 41 def X = BitPat("b000") 42 43 def isPc(srcType: UInt) = srcType===pc 44 def isImm(srcType: UInt) = srcType===imm 45 def isReg(srcType: UInt) = srcType(0) 46 def isXp(srcType: UInt) = srcType(0) 47 def isFp(srcType: UInt) = srcType(1) 48 def isVp(srcType: UInt) = srcType(2) 49 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 50 def isNotReg(srcType: UInt): Bool = !srcType.orR 51 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 61 def isReady(state: UInt): Bool = state === this.rdy 62 def isBusy(state: UInt): Bool = state === this.busy 63 } 64 65 def FuOpTypeWidth = 9 66 object FuOpType { 67 def apply() = UInt(FuOpTypeWidth.W) 68 def X = BitPat("b0_0000_0000") 69 def FMVXF = BitPat("b1_1000_0000") //for fmv_x_d & fmv_x_w 70 } 71 72 object VlduType { 73 // bit encoding: | vector or scala (2bit) || mop (2bit) | lumop(5bit) | 74 // only unit-stride use lumop 75 // mop [1:0] 76 // 0 0 : unit-stride 77 // 0 1 : indexed-unordered 78 // 1 0 : strided 79 // 1 1 : indexed-ordered 80 // lumop[4:0] 81 // 0 0 0 0 0 : unit-stride load 82 // 0 1 0 0 0 : unit-stride, whole register load 83 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 84 // 1 0 0 0 0 : unit-stride fault-only-first 85 def vle = "b01_00_00000".U 86 def vlr = "b01_00_01000".U // whole 87 def vlm = "b01_00_01011".U // mask 88 def vleff = "b01_00_10000".U 89 def vluxe = "b01_01_00000".U // index 90 def vlse = "b01_10_00000".U // strided 91 def vloxe = "b01_11_00000".U // index 92 93 def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U 94 def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U 95 def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U 96 def isIndexed(fuOpType: UInt): Bool = fuOpType(5) 97 def isVecLd (fuOpType: UInt): Bool = fuOpType(8, 7) === "b01".U 98 } 99 100 object VstuType { 101 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 102 // only unit-stride use sumop 103 // mop [1:0] 104 // 0 0 : unit-stride 105 // 0 1 : indexed-unordered 106 // 1 0 : strided 107 // 1 1 : indexed-ordered 108 // sumop[4:0] 109 // 0 0 0 0 0 : unit-stride load 110 // 0 1 0 0 0 : unit-stride, whole register load 111 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 112 def vse = "b10_00_00000".U 113 def vsr = "b10_00_01000".U // whole 114 def vsm = "b10_00_01011".U // mask 115 def vsuxe = "b10_01_00000".U // index 116 def vsse = "b10_10_00000".U // strided 117 def vsoxe = "b10_11_00000".U // index 118 119 def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U 120 def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U 121 def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U 122 def isIndexed(fuOpType: UInt): Bool = fuOpType(5) 123 def isVecSt (fuOpType: UInt): Bool = fuOpType(8, 7) === "b10".U 124 } 125 126 object IF2VectorType { 127 // use last 2 bits for vsew 128 def iDup2Vec = "b1_00".U 129 def fDup2Vec = "b1_00".U 130 def immDup2Vec = "b1_10".U 131 def i2Vec = "b0_00".U 132 def f2Vec = "b0_01".U 133 def imm2Vec = "b0_10".U 134 def needDup(bits: UInt): Bool = bits(2) 135 def isImm(bits: UInt): Bool = bits(1) 136 def isFmv(bits: UInt): Bool = bits(0) 137 def FMX_D_X = "b0_01_11".U 138 def FMX_W_X = "b0_01_10".U 139 } 140 141 object CommitType { 142 def NORMAL = "b000".U // int/fp 143 def BRANCH = "b001".U // branch 144 def LOAD = "b010".U // load 145 def STORE = "b011".U // store 146 147 def apply() = UInt(3.W) 148 def isFused(commitType: UInt): Bool = commitType(2) 149 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 150 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 151 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 152 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 153 } 154 155 object RedirectLevel { 156 def flushAfter = "b0".U 157 def flush = "b1".U 158 159 def apply() = UInt(1.W) 160 // def isUnconditional(level: UInt) = level(1) 161 def flushItself(level: UInt) = level(0) 162 // def isException(level: UInt) = level(1) && level(0) 163 } 164 165 object ExceptionVec { 166 val ExceptionVecSize = 16 167 def apply() = Vec(ExceptionVecSize, Bool()) 168 } 169 170 object PMAMode { 171 def R = "b1".U << 0 //readable 172 def W = "b1".U << 1 //writeable 173 def X = "b1".U << 2 //executable 174 def I = "b1".U << 3 //cacheable: icache 175 def D = "b1".U << 4 //cacheable: dcache 176 def S = "b1".U << 5 //enable speculative access 177 def A = "b1".U << 6 //enable atomic operation, A imply R & W 178 def C = "b1".U << 7 //if it is cacheable is configable 179 def Reserved = "b0".U 180 181 def apply() = UInt(7.W) 182 183 def read(mode: UInt) = mode(0) 184 def write(mode: UInt) = mode(1) 185 def execute(mode: UInt) = mode(2) 186 def icache(mode: UInt) = mode(3) 187 def dcache(mode: UInt) = mode(4) 188 def speculate(mode: UInt) = mode(5) 189 def atomic(mode: UInt) = mode(6) 190 def configable_cache(mode: UInt) = mode(7) 191 192 def strToMode(s: String) = { 193 var result = 0.U(8.W) 194 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 195 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 196 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 197 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 198 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 199 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 200 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 201 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 202 result 203 } 204 } 205 206 207 object CSROpType { 208 def jmp = "b000".U 209 def wrt = "b001".U 210 def set = "b010".U 211 def clr = "b011".U 212 def wfi = "b100".U 213 def wrti = "b101".U 214 def seti = "b110".U 215 def clri = "b111".U 216 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 217 } 218 219 // jump 220 object JumpOpType { 221 def jal = "b00".U 222 def jalr = "b01".U 223 def auipc = "b10".U 224// def call = "b11_011".U 225// def ret = "b11_100".U 226 def jumpOpisJalr(op: UInt) = op(0) 227 def jumpOpisAuipc(op: UInt) = op(1) 228 } 229 230 object FenceOpType { 231 def fence = "b10000".U 232 def sfence = "b10001".U 233 def fencei = "b10010".U 234 def nofence= "b00000".U 235 } 236 237 object ALUOpType { 238 // shift optype 239 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 240 def sll = "b000_0001".U // sll: src1 << src2 241 242 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 243 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 244 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 245 246 def srl = "b000_0101".U // srl: src1 >> src2 247 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 248 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 249 250 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 251 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 252 253 // RV64 32bit optype 254 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 255 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 256 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 257 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 258 259 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 260 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 261 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 262 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 263 264 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 265 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 266 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 267 def rolw = "b001_1100".U 268 def rorw = "b001_1101".U 269 270 // ADD-op 271 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 272 def add = "b010_0001".U // add: src1 + src2 273 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 274 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 275 276 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 277 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 278 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 279 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 280 281 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 282 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 283 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 284 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 285 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 286 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 287 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 288 289 // SUB-op: src1 - src2 290 def sub = "b011_0000".U 291 def sltu = "b011_0001".U 292 def slt = "b011_0010".U 293 def maxu = "b011_0100".U 294 def minu = "b011_0101".U 295 def max = "b011_0110".U 296 def min = "b011_0111".U 297 298 // branch 299 def beq = "b111_0000".U 300 def bne = "b111_0010".U 301 def blt = "b111_1000".U 302 def bge = "b111_1010".U 303 def bltu = "b111_1100".U 304 def bgeu = "b111_1110".U 305 306 // misc optype 307 def and = "b100_0000".U 308 def andn = "b100_0001".U 309 def or = "b100_0010".U 310 def orn = "b100_0011".U 311 def xor = "b100_0100".U 312 def xnor = "b100_0101".U 313 def orcb = "b100_0110".U 314 315 def sextb = "b100_1000".U 316 def packh = "b100_1001".U 317 def sexth = "b100_1010".U 318 def packw = "b100_1011".U 319 320 def revb = "b101_0000".U 321 def rev8 = "b101_0001".U 322 def pack = "b101_0010".U 323 def orh48 = "b101_0011".U 324 325 def szewl1 = "b101_1000".U 326 def szewl2 = "b101_1001".U 327 def szewl3 = "b101_1010".U 328 def byte2 = "b101_1011".U 329 330 def andlsb = "b110_0000".U 331 def andzexth = "b110_0001".U 332 def orlsb = "b110_0010".U 333 def orzexth = "b110_0011".U 334 def xorlsb = "b110_0100".U 335 def xorzexth = "b110_0101".U 336 def orcblsb = "b110_0110".U 337 def orcbzexth = "b110_0111".U 338 339 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 340 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 341 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 342 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 343 344 def apply() = UInt(FuOpTypeWidth.W) 345 } 346 347 object VSETOpType { 348 val setVlmaxBit = 0 349 val keepVlBit = 1 350 // destTypeBit == 0: write vl to rd 351 // destTypeBit == 1: write vconfig 352 val destTypeBit = 5 353 354 // vsetvli's uop 355 // rs1!=x0, normal 356 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 357 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 358 def uvsetvcfg_xi = "b1010_0000".U 359 def uvsetrd_xi = "b1000_0000".U 360 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 361 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 362 // uop1: w(rd) | vlmax, vtypei -> x[rd] 363 def uvsetvcfg_vlmax_i = "b1010_0001".U 364 def uvsetrd_vlmax_i = "b1000_0001".U 365 // rs1==x0, rd==x0, keep vl, set vtype 366 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 367 def uvsetvcfg_keep_v = "b1010_0010".U 368 369 // vsetvl's uop 370 // rs1!=x0, normal 371 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 372 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 373 def uvsetvcfg_xx = "b0110_0000".U 374 def uvsetrd_xx = "b0100_0000".U 375 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 376 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 377 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 378 def uvsetvcfg_vlmax_x = "b0110_0001".U 379 def uvsetrd_vlmax_x = "b0100_0001".U 380 // rs1==x0, rd==x0, keep vl, set vtype 381 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 382 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 383 def uvmv_v_x = "b0110_0010".U 384 def uvsetvcfg_vv = "b0111_0010".U 385 386 // vsetivli's uop 387 // uop0: w(vconfig) | vli, vtypei -> vconfig 388 // uop1: w(rd) | vli, vtypei -> x[rd] 389 def uvsetvcfg_ii = "b0010_0000".U 390 def uvsetrd_ii = "b0000_0000".U 391 392 def isVsetvl (func: UInt) = func(6) 393 def isVsetvli (func: UInt) = func(7) 394 def isVsetivli(func: UInt) = func(7, 6) === 0.U 395 def isNormal (func: UInt) = func(1, 0) === 0.U 396 def isSetVlmax(func: UInt) = func(setVlmaxBit) 397 def isKeepVl (func: UInt) = func(keepVlBit) 398 // RG: region 399 def writeIntRG(func: UInt) = !func(5) 400 def writeVecRG(func: UInt) = func(5) 401 def readIntRG (func: UInt) = !func(4) 402 def readVecRG (func: UInt) = func(4) 403 // modify fuOpType 404 def keepVl(func: UInt) = func | (1 << keepVlBit).U 405 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 406 } 407 408 object BRUOpType { 409 // branch 410 def beq = "b000_000".U 411 def bne = "b000_001".U 412 def blt = "b000_100".U 413 def bge = "b000_101".U 414 def bltu = "b001_000".U 415 def bgeu = "b001_001".U 416 417 def getBranchType(func: UInt) = func(3, 1) 418 def isBranchInvert(func: UInt) = func(0) 419 } 420 421 object MULOpType { 422 // mul 423 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 424 def mul = "b00000".U 425 def mulh = "b00001".U 426 def mulhsu = "b00010".U 427 def mulhu = "b00011".U 428 def mulw = "b00100".U 429 430 def mulw7 = "b01100".U 431 def isSign(op: UInt) = !op(1) 432 def isW(op: UInt) = op(2) 433 def isH(op: UInt) = op(1, 0) =/= 0.U 434 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 435 } 436 437 object DIVOpType { 438 // div 439 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 440 def div = "b10000".U 441 def divu = "b10010".U 442 def rem = "b10001".U 443 def remu = "b10011".U 444 445 def divw = "b10100".U 446 def divuw = "b10110".U 447 def remw = "b10101".U 448 def remuw = "b10111".U 449 450 def isSign(op: UInt) = !op(1) 451 def isW(op: UInt) = op(2) 452 def isH(op: UInt) = op(0) 453 } 454 455 object MDUOpType { 456 // mul 457 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 458 def mul = "b00000".U 459 def mulh = "b00001".U 460 def mulhsu = "b00010".U 461 def mulhu = "b00011".U 462 def mulw = "b00100".U 463 464 def mulw7 = "b01100".U 465 466 // div 467 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 468 def div = "b10000".U 469 def divu = "b10010".U 470 def rem = "b10001".U 471 def remu = "b10011".U 472 473 def divw = "b10100".U 474 def divuw = "b10110".U 475 def remw = "b10101".U 476 def remuw = "b10111".U 477 478 def isMul(op: UInt) = !op(4) 479 def isDiv(op: UInt) = op(4) 480 481 def isDivSign(op: UInt) = isDiv(op) && !op(1) 482 def isW(op: UInt) = op(2) 483 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 484 def getMulOp(op: UInt) = op(1, 0) 485 } 486 487 object LSUOpType { 488 // load pipeline 489 490 // normal load 491 // Note: bit(1, 0) are size, DO NOT CHANGE 492 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 493 def lb = "b0000".U 494 def lh = "b0001".U 495 def lw = "b0010".U 496 def ld = "b0011".U 497 def lbu = "b0100".U 498 def lhu = "b0101".U 499 def lwu = "b0110".U 500 501 // Zicbop software prefetch 502 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 503 def prefetch_i = "b1000".U // TODO 504 def prefetch_r = "b1001".U 505 def prefetch_w = "b1010".U 506 507 def isPrefetch(op: UInt): Bool = op(3) 508 509 // store pipeline 510 // normal store 511 // bit encoding: | store 00 | size(2bit) | 512 def sb = "b0000".U 513 def sh = "b0001".U 514 def sw = "b0010".U 515 def sd = "b0011".U 516 517 // l1 cache op 518 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 519 def cbo_zero = "b0111".U 520 521 // llc op 522 // bit encoding: | prefetch 11 | suboptype(2bit) | 523 def cbo_clean = "b1100".U 524 def cbo_flush = "b1101".U 525 def cbo_inval = "b1110".U 526 527 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 528 529 // atomics 530 // bit(1, 0) are size 531 // since atomics use a different fu type 532 // so we can safely reuse other load/store's encodings 533 // bit encoding: | optype(4bit) | size (2bit) | 534 def lr_w = "b000010".U 535 def sc_w = "b000110".U 536 def amoswap_w = "b001010".U 537 def amoadd_w = "b001110".U 538 def amoxor_w = "b010010".U 539 def amoand_w = "b010110".U 540 def amoor_w = "b011010".U 541 def amomin_w = "b011110".U 542 def amomax_w = "b100010".U 543 def amominu_w = "b100110".U 544 def amomaxu_w = "b101010".U 545 546 def lr_d = "b000011".U 547 def sc_d = "b000111".U 548 def amoswap_d = "b001011".U 549 def amoadd_d = "b001111".U 550 def amoxor_d = "b010011".U 551 def amoand_d = "b010111".U 552 def amoor_d = "b011011".U 553 def amomin_d = "b011111".U 554 def amomax_d = "b100011".U 555 def amominu_d = "b100111".U 556 def amomaxu_d = "b101011".U 557 558 def size(op: UInt) = op(1,0) 559 560 def getVecLSMop(fuOpType: UInt): UInt = fuOpType(6, 5) 561 562 def isVecLd(fuOpType: UInt): Bool = fuOpType(8, 7) === "b01".U 563 def isVecSt(fuOpType: UInt): Bool = fuOpType(8, 7) === "b10".U 564 def isVecLS(fuOpType: UInt): Bool = fuOpType(8, 7).orR 565 566 def isUStride(fuOpType: UInt): Bool = fuOpType(6, 0) === "b00_00000".U 567 def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U 568 def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U 569 def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U 570 def isIndexed(fuOpType: UInt): Bool = fuOpType(5) 571 } 572 573 object BKUOpType { 574 575 def clmul = "b000000".U 576 def clmulh = "b000001".U 577 def clmulr = "b000010".U 578 def xpermn = "b000100".U 579 def xpermb = "b000101".U 580 581 def clz = "b001000".U 582 def clzw = "b001001".U 583 def ctz = "b001010".U 584 def ctzw = "b001011".U 585 def cpop = "b001100".U 586 def cpopw = "b001101".U 587 588 // 01xxxx is reserve 589 def aes64es = "b100000".U 590 def aes64esm = "b100001".U 591 def aes64ds = "b100010".U 592 def aes64dsm = "b100011".U 593 def aes64im = "b100100".U 594 def aes64ks1i = "b100101".U 595 def aes64ks2 = "b100110".U 596 597 // merge to two instruction sm4ks & sm4ed 598 def sm4ed0 = "b101000".U 599 def sm4ed1 = "b101001".U 600 def sm4ed2 = "b101010".U 601 def sm4ed3 = "b101011".U 602 def sm4ks0 = "b101100".U 603 def sm4ks1 = "b101101".U 604 def sm4ks2 = "b101110".U 605 def sm4ks3 = "b101111".U 606 607 def sha256sum0 = "b110000".U 608 def sha256sum1 = "b110001".U 609 def sha256sig0 = "b110010".U 610 def sha256sig1 = "b110011".U 611 def sha512sum0 = "b110100".U 612 def sha512sum1 = "b110101".U 613 def sha512sig0 = "b110110".U 614 def sha512sig1 = "b110111".U 615 616 def sm3p0 = "b111000".U 617 def sm3p1 = "b111001".U 618 } 619 620 object BTBtype { 621 def B = "b00".U // branch 622 def J = "b01".U // jump 623 def I = "b10".U // indirect 624 def R = "b11".U // return 625 626 def apply() = UInt(2.W) 627 } 628 629 object SelImm { 630 def IMM_X = "b0111".U 631 def IMM_S = "b1110".U 632 def IMM_SB = "b0001".U 633 def IMM_U = "b0010".U 634 def IMM_UJ = "b0011".U 635 def IMM_I = "b0100".U 636 def IMM_Z = "b0101".U 637 def INVALID_INSTR = "b0110".U 638 def IMM_B6 = "b1000".U 639 640 def IMM_OPIVIS = "b1001".U 641 def IMM_OPIVIU = "b1010".U 642 def IMM_VSETVLI = "b1100".U 643 def IMM_VSETIVLI = "b1101".U 644 def IMM_LUI32 = "b1011".U 645 def IMM_VRORVI = "b1111".U 646 647 def X = BitPat("b0000") 648 649 def apply() = UInt(4.W) 650 651 def mkString(immType: UInt) : String = { 652 val strMap = Map( 653 IMM_S.litValue -> "S", 654 IMM_SB.litValue -> "SB", 655 IMM_U.litValue -> "U", 656 IMM_UJ.litValue -> "UJ", 657 IMM_I.litValue -> "I", 658 IMM_Z.litValue -> "Z", 659 IMM_B6.litValue -> "B6", 660 IMM_OPIVIS.litValue -> "VIS", 661 IMM_OPIVIU.litValue -> "VIU", 662 IMM_VSETVLI.litValue -> "VSETVLI", 663 IMM_VSETIVLI.litValue -> "VSETIVLI", 664 IMM_LUI32.litValue -> "LUI32", 665 IMM_VRORVI.litValue -> "VRORVI", 666 INVALID_INSTR.litValue -> "INVALID", 667 ) 668 strMap(immType.litValue) 669 } 670 671 def getImmUnion(immType: UInt) : Imm = { 672 val iuMap = Map( 673 IMM_S.litValue -> ImmUnion.S, 674 IMM_SB.litValue -> ImmUnion.B, 675 IMM_U.litValue -> ImmUnion.U, 676 IMM_UJ.litValue -> ImmUnion.J, 677 IMM_I.litValue -> ImmUnion.I, 678 IMM_Z.litValue -> ImmUnion.Z, 679 IMM_B6.litValue -> ImmUnion.B6, 680 IMM_OPIVIS.litValue -> ImmUnion.OPIVIS, 681 IMM_OPIVIU.litValue -> ImmUnion.OPIVIU, 682 IMM_VSETVLI.litValue -> ImmUnion.VSETVLI, 683 IMM_VSETIVLI.litValue -> ImmUnion.VSETIVLI, 684 IMM_LUI32.litValue -> ImmUnion.LUI32, 685 IMM_VRORVI.litValue -> ImmUnion.VRORVI, 686 ) 687 iuMap(immType.litValue) 688 } 689 } 690 691 object UopSplitType { 692 def SCA_SIM = "b000000".U // 693 def VSET = "b010001".U // dirty: vset 694 def VEC_VVV = "b010010".U // VEC_VVV 695 def VEC_VXV = "b010011".U // VEC_VXV 696 def VEC_0XV = "b010100".U // VEC_0XV 697 def VEC_VVW = "b010101".U // VEC_VVW 698 def VEC_WVW = "b010110".U // VEC_WVW 699 def VEC_VXW = "b010111".U // VEC_VXW 700 def VEC_WXW = "b011000".U // VEC_WXW 701 def VEC_WVV = "b011001".U // VEC_WVV 702 def VEC_WXV = "b011010".U // VEC_WXV 703 def VEC_EXT2 = "b011011".U // VF2 0 -> V 704 def VEC_EXT4 = "b011100".U // VF4 0 -> V 705 def VEC_EXT8 = "b011101".U // VF8 0 -> V 706 def VEC_VVM = "b011110".U // VEC_VVM 707 def VEC_VXM = "b011111".U // VEC_VXM 708 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 709 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 710 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 711 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 712 def VEC_VRED = "b100100".U // VEC_VRED 713 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 714 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 715 def VEC_M0X = "b101001".U // VEC_M0X 0MV 716 def VEC_MVV = "b101010".U // VEC_MVV VMV 717 def VEC_M0X_VFIRST = "b101011".U // 718 def VEC_VWW = "b101100".U // 719 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 720 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 721 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 722 def VEC_COMPRESS = "b110000".U // vcompress.vm 723 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 724 def VEC_S_LDST = "b110010".U // vector strided load/store 725 def VEC_I_LDST = "b110011".U // vector indexed load/store 726 def VEC_VFV = "b111000".U // VEC_VFV 727 def VEC_VFW = "b111001".U // VEC_VFW 728 def VEC_WFW = "b111010".U // VEC_WVW 729 def VEC_VFM = "b111011".U // VEC_VFM 730 def VEC_VFRED = "b111100".U // VEC_VFRED 731 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 732 def VEC_M0M = "b000000".U // VEC_M0M 733 def VEC_MMM = "b000000".U // VEC_MMM 734 def VEC_MVNR = "b000100".U // vmvnr 735 def dummy = "b111111".U 736 737 def X = BitPat("b000000") 738 739 def apply() = UInt(6.W) 740 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 741 } 742 743 object ExceptionNO { 744 def instrAddrMisaligned = 0 745 def instrAccessFault = 1 746 def illegalInstr = 2 747 def breakPoint = 3 748 def loadAddrMisaligned = 4 749 def loadAccessFault = 5 750 def storeAddrMisaligned = 6 751 def storeAccessFault = 7 752 def ecallU = 8 753 def ecallS = 9 754 def ecallM = 11 755 def instrPageFault = 12 756 def loadPageFault = 13 757 // def singleStep = 14 758 def storePageFault = 15 759 def priorities = Seq( 760 breakPoint, // TODO: different BP has different priority 761 instrPageFault, 762 instrAccessFault, 763 illegalInstr, 764 instrAddrMisaligned, 765 ecallM, ecallS, ecallU, 766 storeAddrMisaligned, 767 loadAddrMisaligned, 768 storePageFault, 769 loadPageFault, 770 storeAccessFault, 771 loadAccessFault 772 ) 773 def all = priorities.distinct.sorted 774 def frontendSet = Seq( 775 instrAddrMisaligned, 776 instrAccessFault, 777 illegalInstr, 778 instrPageFault 779 ) 780 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 781 val new_vec = Wire(ExceptionVec()) 782 new_vec.foreach(_ := false.B) 783 select.foreach(i => new_vec(i) := vec(i)) 784 new_vec 785 } 786 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 787 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 788 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 789 partialSelect(vec, fuConfig.exceptionOut) 790 } 791 792 object TopDownCounters extends Enumeration { 793 val NoStall = Value("NoStall") // Base 794 // frontend 795 val OverrideBubble = Value("OverrideBubble") 796 val FtqUpdateBubble = Value("FtqUpdateBubble") 797 // val ControlRedirectBubble = Value("ControlRedirectBubble") 798 val TAGEMissBubble = Value("TAGEMissBubble") 799 val SCMissBubble = Value("SCMissBubble") 800 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 801 val RASMissBubble = Value("RASMissBubble") 802 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 803 val OtherRedirectBubble = Value("OtherRedirectBubble") 804 val FtqFullStall = Value("FtqFullStall") 805 806 val ICacheMissBubble = Value("ICacheMissBubble") 807 val ITLBMissBubble = Value("ITLBMissBubble") 808 val BTBMissBubble = Value("BTBMissBubble") 809 val FetchFragBubble = Value("FetchFragBubble") 810 811 // backend 812 // long inst stall at rob head 813 val DivStall = Value("DivStall") // int div, float div/sqrt 814 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 815 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 816 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 817 // freelist full 818 val IntFlStall = Value("IntFlStall") 819 val FpFlStall = Value("FpFlStall") 820 // dispatch queue full 821 val IntDqStall = Value("IntDqStall") 822 val FpDqStall = Value("FpDqStall") 823 val LsDqStall = Value("LsDqStall") 824 825 // memblock 826 val LoadTLBStall = Value("LoadTLBStall") 827 val LoadL1Stall = Value("LoadL1Stall") 828 val LoadL2Stall = Value("LoadL2Stall") 829 val LoadL3Stall = Value("LoadL3Stall") 830 val LoadMemStall = Value("LoadMemStall") 831 val StoreStall = Value("StoreStall") // include store tlb miss 832 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 833 834 // xs replay (different to gem5) 835 val LoadVioReplayStall = Value("LoadVioReplayStall") 836 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 837 838 // bad speculation 839 val ControlRecoveryStall = Value("ControlRecoveryStall") 840 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 841 val OtherRecoveryStall = Value("OtherRecoveryStall") 842 843 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 844 845 val OtherCoreStall = Value("OtherCoreStall") 846 847 val NumStallReasons = Value("NumStallReasons") 848 } 849} 850