1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.backend.fu._ 22import xiangshan.backend.fu.fpu._ 23import xiangshan.backend.exu._ 24import xiangshan.backend.{AmoData, Std} 25 26package object xiangshan { 27 object SrcType { 28 def reg = "b00".U 29 def pc = "b01".U 30 def imm = "b01".U 31 def fp = "b10".U 32 33 def DC = imm // Don't Care 34 35 def isReg(srcType: UInt) = srcType===reg 36 def isPc(srcType: UInt) = srcType===pc 37 def isImm(srcType: UInt) = srcType===imm 38 def isFp(srcType: UInt) = srcType(1) 39 def isPcOrImm(srcType: UInt) = srcType(0) 40 def isRegOrFp(srcType: UInt) = !srcType(0) 41 def regIsFp(srcType: UInt) = srcType(1) 42 43 def apply() = UInt(2.W) 44 } 45 46 object SrcState { 47 def busy = "b0".U 48 def rdy = "b1".U 49 // def specRdy = "b10".U // speculative ready, for future use 50 def apply() = UInt(1.W) 51 } 52 53 object FuType { 54 def jmp = "b0000".U 55 def i2f = "b0001".U 56 def csr = "b0010".U 57 def alu = "b0110".U 58 def mul = "b0100".U 59 def div = "b0101".U 60 def fence = "b0011".U 61 def bmu = "b0111".U 62 63 def fmac = "b1000".U 64 def fmisc = "b1011".U 65 def fDivSqrt = "b1010".U 66 67 def ldu = "b1100".U 68 def stu = "b1101".U 69 def mou = "b1111".U // for amo, lr, sc, fence 70 71 def num = 14 72 73 def apply() = UInt(log2Up(num).W) 74 75 def isIntExu(fuType: UInt) = !fuType(3) 76 def isJumpExu(fuType: UInt) = fuType === jmp 77 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 78 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 79 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 80 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 81 def isAMO(fuType: UInt) = fuType(1) 82 83 def jmpCanAccept(fuType: UInt) = !fuType(2) 84 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 85 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 86 87 def fmacCanAccept(fuType: UInt) = !fuType(1) 88 def fmiscCanAccept(fuType: UInt) = fuType(1) 89 90 def loadCanAccept(fuType: UInt) = !fuType(0) 91 def storeCanAccept(fuType: UInt) = fuType(0) 92 93 def storeIsAMO(fuType: UInt) = fuType(1) 94 95 val functionNameMap = Map( 96 jmp.litValue() -> "jmp", 97 i2f.litValue() -> "int_to_float", 98 csr.litValue() -> "csr", 99 alu.litValue() -> "alu", 100 mul.litValue() -> "mul", 101 div.litValue() -> "div", 102 fence.litValue() -> "fence", 103 bmu.litValue() -> "bmu", 104 fmac.litValue() -> "fmac", 105 fmisc.litValue() -> "fmisc", 106 fDivSqrt.litValue() -> "fdiv/fsqrt", 107 ldu.litValue() -> "load", 108 stu.litValue() -> "store", 109 mou.litValue() -> "mou" 110 ) 111 } 112 113 object FuOpType { 114 def apply() = UInt(7.W) 115 } 116 117 object CommitType { 118 def NORMAL = "b00".U // int/fp 119 def BRANCH = "b01".U // branch 120 def LOAD = "b10".U // load 121 def STORE = "b11".U // store 122 123 def apply() = UInt(2.W) 124 def isLoadStore(commitType: UInt) = commitType(1) 125 def lsInstIsStore(commitType: UInt) = commitType(0) 126 def isStore(commitType: UInt) = isLoadStore(commitType) && lsInstIsStore(commitType) 127 def isBranch(commitType: UInt) = commitType(0) && !commitType(1) 128 } 129 130 object RedirectLevel { 131 def flushAfter = "b0".U 132 def flush = "b1".U 133 134 def apply() = UInt(1.W) 135 // def isUnconditional(level: UInt) = level(1) 136 def flushItself(level: UInt) = level(0) 137 // def isException(level: UInt) = level(1) && level(0) 138 } 139 140 object ExceptionVec { 141 def apply() = Vec(16, Bool()) 142 } 143 144 object PMAMode { 145 def R = "b1".U << 0 //readable 146 def W = "b1".U << 1 //writeable 147 def X = "b1".U << 2 //executable 148 def I = "b1".U << 3 //cacheable: icache 149 def D = "b1".U << 4 //cacheable: dcache 150 def S = "b1".U << 5 //enable speculative access 151 def A = "b1".U << 6 //enable atomic operation, A imply R & W 152 def C = "b1".U << 7 //if it is cacheable is configable 153 def Reserved = "b0".U 154 155 def apply() = UInt(7.W) 156 157 def read(mode: UInt) = mode(0) 158 def write(mode: UInt) = mode(1) 159 def execute(mode: UInt) = mode(2) 160 def icache(mode: UInt) = mode(3) 161 def dcache(mode: UInt) = mode(4) 162 def speculate(mode: UInt) = mode(5) 163 def atomic(mode: UInt) = mode(6) 164 def configable_cache(mode: UInt) = mode(7) 165 166 def strToMode(s: String) = { 167 var result = 0.U(8.W) 168 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 169 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 170 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 171 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 172 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 173 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 174 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 175 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 176 result 177 } 178 } 179 180 181 object CSROpType { 182 def jmp = "b000".U 183 def wrt = "b001".U 184 def set = "b010".U 185 def clr = "b011".U 186 def wrti = "b101".U 187 def seti = "b110".U 188 def clri = "b111".U 189 } 190 191 // jump 192 object JumpOpType { 193 def jal = "b00".U 194 def jalr = "b01".U 195 def auipc = "b10".U 196// def call = "b11_011".U 197// def ret = "b11_100".U 198 def jumpOpisJalr(op: UInt) = op(0) 199 def jumpOpisAuipc(op: UInt) = op(1) 200 } 201 202 object FenceOpType { 203 def fence = "b10000".U 204 def sfence = "b10001".U 205 def fencei = "b10010".U 206 } 207 208 object ALUOpType { 209 // shift optype 210 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 211 def sll = "b000_0001".U // sll: src1 << src2 212 213 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 214 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 215 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 216 217 def srl = "b000_0101".U // srl: src1 >> src2 218 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 219 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 220 221 def rol = "b000_1000".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 222 def ror = "b000_1001".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 223 224 // RV64 32bit optype 225 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 226 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 227 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 228 229 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 230 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 231 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 232 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 233 234 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 235 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 236 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 237 def rolw = "b001_1100".U 238 def rorw = "b001_1101".U 239 240 // ADD-op 241 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 242 def add = "b010_0001".U // add: src1 + src2 243 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 244 245 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 246 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 247 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 248 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 249 250 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 251 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 252 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 253 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 254 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 255 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 256 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 257 258 // SUB-op: src1 - src2 259 def sub = "b011_0000".U 260 def sltu = "b011_0001".U 261 def slt = "b011_0010".U 262 def maxu = "b011_0100".U 263 def minu = "b011_0101".U 264 def max = "b011_0110".U 265 def min = "b011_0111".U 266 267 // branch 268 def beq = "b111_0000".U 269 def bne = "b111_0010".U 270 def blt = "b111_1000".U 271 def bge = "b111_1010".U 272 def bltu = "b111_1100".U 273 def bgeu = "b111_1110".U 274 275 // misc optype 276 def and = "b100_0000".U 277 def andn = "b100_0001".U 278 def or = "b100_0010".U 279 def orn = "b100_0011".U 280 def xor = "b100_0100".U 281 def xnor = "b100_0101".U 282 def orcb = "b100_0110".U 283 284 def sextb = "b100_1000".U 285 def packh = "b100_1001".U 286 def sexth = "b100_1010".U 287 def packw = "b100_1011".U 288 289 def revb = "b101_0000".U 290 def rev8 = "b101_0001".U 291 def pack = "b101_0010".U 292 def orh48 = "b101_0011".U 293 294 def szewl1 = "b101_1000".U 295 def szewl2 = "b101_1001".U 296 def szewl3 = "b101_1010".U 297 def byte2 = "b101_1011".U 298 299 def andlsb = "b110_0000".U 300 def andzexth = "b110_0001".U 301 def orlsb = "b110_0010".U 302 def orzexth = "b110_0011".U 303 def xorlsb = "b110_0100".U 304 def xorzexth = "b110_0101".U 305 def orcblsb = "b110_0110".U 306 def orcbzexth = "b110_0111".U 307 308 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 309 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 310 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 311 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 312 def isBranch(func: UInt) = func(6, 4) === "b111".U 313 def getBranchType(func: UInt) = func(3, 2) 314 def isBranchInvert(func: UInt) = func(1) 315 316 def apply() = UInt(7.W) 317 } 318 319 object MDUOpType { 320 // mul 321 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 322 def mul = "b00000".U 323 def mulh = "b00001".U 324 def mulhsu = "b00010".U 325 def mulhu = "b00011".U 326 def mulw = "b00100".U 327 328 def mulw7 = "b01100".U 329 330 // div 331 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 332 def div = "b10000".U 333 def divu = "b10010".U 334 def rem = "b10001".U 335 def remu = "b10011".U 336 337 def divw = "b10100".U 338 def divuw = "b10110".U 339 def remw = "b10101".U 340 def remuw = "b10111".U 341 342 def isMul(op: UInt) = !op(4) 343 def isDiv(op: UInt) = op(4) 344 345 def isDivSign(op: UInt) = isDiv(op) && !op(1) 346 def isW(op: UInt) = op(2) 347 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 348 def getMulOp(op: UInt) = op(1, 0) 349 } 350 351 object LSUOpType { 352 // normal load/store 353 // bit(1, 0) are size 354 def lb = "b000000".U 355 def lh = "b000001".U 356 def lw = "b000010".U 357 def ld = "b000011".U 358 def lbu = "b000100".U 359 def lhu = "b000101".U 360 def lwu = "b000110".U 361 def sb = "b001000".U 362 def sh = "b001001".U 363 def sw = "b001010".U 364 def sd = "b001011".U 365 366 def isLoad(op: UInt): Bool = !op(3) 367 def isStore(op: UInt): Bool = op(3) 368 369 // atomics 370 // bit(1, 0) are size 371 // since atomics use a different fu type 372 // so we can safely reuse other load/store's encodings 373 def lr_w = "b000010".U 374 def sc_w = "b000110".U 375 def amoswap_w = "b001010".U 376 def amoadd_w = "b001110".U 377 def amoxor_w = "b010010".U 378 def amoand_w = "b010110".U 379 def amoor_w = "b011010".U 380 def amomin_w = "b011110".U 381 def amomax_w = "b100010".U 382 def amominu_w = "b100110".U 383 def amomaxu_w = "b101010".U 384 385 def lr_d = "b000011".U 386 def sc_d = "b000111".U 387 def amoswap_d = "b001011".U 388 def amoadd_d = "b001111".U 389 def amoxor_d = "b010011".U 390 def amoand_d = "b010111".U 391 def amoor_d = "b011011".U 392 def amomin_d = "b011111".U 393 def amomax_d = "b100011".U 394 def amominu_d = "b100111".U 395 def amomaxu_d = "b101011".U 396 } 397 398 object BMUOpType { 399 400 def clmul = "b00000".U 401 def clmulh = "b00010".U 402 def clmulr = "b00100".U 403 404 def clz = "b01000".U 405 def clzw = "b01001".U 406 def ctz = "b01010".U 407 def ctzw = "b01011".U 408 def cpop = "b01100".U 409 def cpopw = "b01101".U 410 411 // TODO: move to alu 412 def xpermn = "b10000".U 413 def xpermb = "b10001".U 414 } 415 416 object BTBtype { 417 def B = "b00".U // branch 418 def J = "b01".U // jump 419 def I = "b10".U // indirect 420 def R = "b11".U // return 421 422 def apply() = UInt(2.W) 423 } 424 425 object SelImm { 426 def IMM_X = "b0111".U 427 def IMM_S = "b0000".U 428 def IMM_SB = "b0001".U 429 def IMM_U = "b0010".U 430 def IMM_UJ = "b0011".U 431 def IMM_I = "b0100".U 432 def IMM_Z = "b0101".U 433 def INVALID_INSTR = "b0110".U 434 def IMM_B6 = "b1000".U 435 436 def apply() = UInt(4.W) 437 } 438 439 def dividerGen(p: Parameters) = new SRT16Divider(p(XLen))(p) 440 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 441 def aluGen(p: Parameters) = new Alu()(p) 442 def bmuGen(p: Parameters) = new Bmu()(p) 443 def jmpGen(p: Parameters) = new Jump()(p) 444 def fenceGen(p: Parameters) = new Fence()(p) 445 def csrGen(p: Parameters) = new CSR()(p) 446 def i2fGen(p: Parameters) = new IntToFP()(p) 447 def fmacGen(p: Parameters) = new FMA()(p) 448 def f2iGen(p: Parameters) = new FPToInt()(p) 449 def f2fGen(p: Parameters) = new FPToFP()(p) 450 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 451 def stdGen(p: Parameters) = new Std()(p) 452 def mouDataGen(p: Parameters) = new AmoData()(p) 453 454 def f2iSel(uop: MicroOp): Bool = { 455 uop.ctrl.rfWen 456 } 457 458 def i2fSel(uop: MicroOp): Bool = { 459 uop.ctrl.fpu.fromInt 460 } 461 462 def f2fSel(uop: MicroOp): Bool = { 463 val ctrl = uop.ctrl.fpu 464 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 465 } 466 467 def fdivSqrtSel(uop: MicroOp): Bool = { 468 val ctrl = uop.ctrl.fpu 469 ctrl.div || ctrl.sqrt 470 } 471 472 val aluCfg = FuConfig( 473 name = "alu", 474 fuGen = aluGen, 475 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 476 fuType = FuType.alu, 477 numIntSrc = 2, 478 numFpSrc = 0, 479 writeIntRf = true, 480 writeFpRf = false, 481 hasRedirect = true, 482 ) 483 484 val jmpCfg = FuConfig( 485 name = "jmp", 486 fuGen = jmpGen, 487 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 488 fuType = FuType.jmp, 489 numIntSrc = 1, 490 numFpSrc = 0, 491 writeIntRf = true, 492 writeFpRf = false, 493 hasRedirect = true, 494 ) 495 496 val fenceCfg = FuConfig( 497 name = "fence", 498 fuGen = fenceGen, 499 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 500 FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 501 latency = UncertainLatency(), // TODO: need rewrite latency structure, not just this value, 502 hasExceptionOut = true 503 ) 504 505 val csrCfg = FuConfig( 506 name = "csr", 507 fuGen = csrGen, 508 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 509 fuType = FuType.csr, 510 numIntSrc = 1, 511 numFpSrc = 0, 512 writeIntRf = true, 513 writeFpRf = false, 514 hasRedirect = false, 515 hasExceptionOut = true 516 ) 517 518 val i2fCfg = FuConfig( 519 name = "i2f", 520 fuGen = i2fGen, 521 fuSel = i2fSel, 522 FuType.i2f, 523 numIntSrc = 1, 524 numFpSrc = 0, 525 writeIntRf = false, 526 writeFpRf = true, 527 hasRedirect = false, 528 latency = CertainLatency(2), 529 fastUopOut = true, fastImplemented = true 530 ) 531 532 val divCfg = FuConfig( 533 name = "div", 534 fuGen = dividerGen, 535 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 536 FuType.div, 537 2, 538 0, 539 writeIntRf = true, 540 writeFpRf = false, 541 hasRedirect = false, 542 latency = UncertainLatency(), 543 fastUopOut = true, 544 fastImplemented = false 545 ) 546 547 val mulCfg = FuConfig( 548 name = "mul", 549 fuGen = multiplierGen, 550 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 551 FuType.mul, 552 2, 553 0, 554 writeIntRf = true, 555 writeFpRf = false, 556 hasRedirect = false, 557 latency = CertainLatency(2), 558 fastUopOut = true, 559 fastImplemented = true 560 ) 561 562 val bmuCfg = FuConfig( 563 name = "bmu", 564 fuGen = bmuGen, 565 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bmu, 566 fuType = FuType.bmu, 567 numIntSrc = 2, 568 numFpSrc = 0, 569 writeIntRf = true, 570 writeFpRf = false, 571 hasRedirect = false, 572 latency = CertainLatency(1), 573 fastUopOut = true, 574 fastImplemented = true 575 ) 576 577 val fmacCfg = FuConfig( 578 name = "fmac", 579 fuGen = fmacGen, 580 fuSel = _ => true.B, 581 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, 582 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 583 ) 584 585 val f2iCfg = FuConfig( 586 name = "f2i", 587 fuGen = f2iGen, 588 fuSel = f2iSel, 589 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2), 590 fastUopOut = true, fastImplemented = true 591 ) 592 593 val f2fCfg = FuConfig( 594 name = "f2f", 595 fuGen = f2fGen, 596 fuSel = f2fSel, 597 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2), 598 fastUopOut = true, fastImplemented = true 599 ) 600 601 val fdivSqrtCfg = FuConfig( 602 name = "fdivSqrt", 603 fuGen = fdivSqrtGen, 604 fuSel = fdivSqrtSel, 605 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency(), 606 fastUopOut = true, fastImplemented = false, hasInputBuffer = true 607 ) 608 609 val lduCfg = FuConfig( 610 "ldu", 611 null, // DontCare 612 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 613 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 614 latency = UncertainLatency(), hasExceptionOut = true 615 ) 616 617 val staCfg = FuConfig( 618 "sta", 619 null, 620 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 621 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 622 latency = UncertainLatency(), hasExceptionOut = true 623 ) 624 625 val stdCfg = FuConfig( 626 "std", 627 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 628 writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = CertainLatency(1) 629 ) 630 631 val mouCfg = FuConfig( 632 "mou", 633 null, 634 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 635 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 636 latency = UncertainLatency(), hasExceptionOut = true 637 ) 638 639 val mouDataCfg = FuConfig( 640 "mou", 641 mouDataGen, 642 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 643 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 644 latency = UncertainLatency(), hasExceptionOut = true 645 ) 646 647 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 648 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 649 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 650 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bmuCfg), 1, Int.MaxValue) 651 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 652 val FmiscExeUnitCfg = ExuConfig( 653 "FmiscExeUnit", 654 "Fp", 655 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 656 Int.MaxValue, 1 657 ) 658 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 659 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 660 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 661} 662