1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.fu.vector._ 26import xiangshan.backend.exu._ 27import xiangshan.backend.{Std, ScheLaneConfig} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isFp(srcType: UInt) = srcType(1) 46 def isVp(srcType: UInt) = srcType(2) 47 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 48 49 def apply() = UInt(3.W) 50 } 51 52 object SrcState { 53 def busy = "b0".U 54 def rdy = "b1".U 55 // def specRdy = "b10".U // speculative ready, for future use 56 def apply() = UInt(1.W) 57 } 58 59 // Todo: Use OH instead 60 object FuType { 61 def jmp = "b00000".U 62 def i2f = "b00001".U 63 def csr = "b00010".U 64 def alu = "b00110".U 65 def mul = "b00100".U 66 def div = "b00101".U 67 def fence = "b00011".U 68 def bku = "b00111".U 69 70 def fmac = "b01000".U 71 def fmisc = "b01011".U 72 def fDivSqrt = "b01010".U 73 74 def ldu = "b01100".U 75 def stu = "b01101".U 76 def mou = "b01111".U // for amo, lr, sc, fence 77 def vipu = "b10000".U 78 def vfpu = "b11000".U 79 def vldu = "b11100".U 80 def vstu = "b11101".U 81 def X = BitPat("b00000") 82 83 def num = 18 84 85 def apply() = UInt(log2Up(num).W) 86 87 // TODO: Optimize FuTpye and its method 88 // FIXME: Vector FuType coding is not ready 89 def isVecExu(fuType: UInt) = fuType(4) 90 def isIntExu(fuType: UInt) = !isVecExu(fuType) && !fuType(3) 91 def isJumpExu(fuType: UInt) = fuType === jmp 92 def isFpExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b10".U) 93 def isMemExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b11".U) 94 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 95 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 96 def isAMO(fuType: UInt) = fuType(1) 97 def isFence(fuType: UInt) = fuType === fence 98 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 99 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 100 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 101 def isVpu(fuType: UInt) = fuType(4) 102 103 def jmpCanAccept(fuType: UInt) = !fuType(2) 104 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 105 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 106 107 def fmacCanAccept(fuType: UInt) = !fuType(1) 108 def fmiscCanAccept(fuType: UInt) = fuType(1) 109 110 def loadCanAccept(fuType: UInt) = !fuType(0) 111 def storeCanAccept(fuType: UInt) = fuType(0) 112 113 def storeIsAMO(fuType: UInt) = fuType(1) 114 115 val functionNameMap = Map( 116 jmp.litValue() -> "jmp", 117 i2f.litValue() -> "int_to_float", 118 csr.litValue() -> "csr", 119 alu.litValue() -> "alu", 120 mul.litValue() -> "mul", 121 div.litValue() -> "div", 122 fence.litValue() -> "fence", 123 bku.litValue() -> "bku", 124 fmac.litValue() -> "fmac", 125 fmisc.litValue() -> "fmisc", 126 fDivSqrt.litValue() -> "fdiv_fsqrt", 127 ldu.litValue() -> "load", 128 stu.litValue() -> "store", 129 mou.litValue() -> "mou" 130 ) 131 } 132 133 def FuOpTypeWidth = 8 134 object FuOpType { 135 def apply() = UInt(FuOpTypeWidth.W) 136 def X = BitPat("b00000000") 137 } 138 139 // move VipuType and VfpuType into YunSuan/package.scala 140 // object VipuType { 141 // def dummy = 0.U(7.W) 142 // } 143 144 // object VfpuType { 145 // def dummy = 0.U(7.W) 146 // } 147 148 object VlduType { 149 def dummy = 0.U 150 } 151 152 object VstuType { 153 def dummy = 0.U 154 } 155 156 object CommitType { 157 def NORMAL = "b000".U // int/fp 158 def BRANCH = "b001".U // branch 159 def LOAD = "b010".U // load 160 def STORE = "b011".U // store 161 162 def apply() = UInt(3.W) 163 def isFused(commitType: UInt): Bool = commitType(2) 164 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 165 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 166 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 167 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 168 } 169 170 object RedirectLevel { 171 def flushAfter = "b0".U 172 def flush = "b1".U 173 174 def apply() = UInt(1.W) 175 // def isUnconditional(level: UInt) = level(1) 176 def flushItself(level: UInt) = level(0) 177 // def isException(level: UInt) = level(1) && level(0) 178 } 179 180 object ExceptionVec { 181 def apply() = Vec(16, Bool()) 182 } 183 184 object PMAMode { 185 def R = "b1".U << 0 //readable 186 def W = "b1".U << 1 //writeable 187 def X = "b1".U << 2 //executable 188 def I = "b1".U << 3 //cacheable: icache 189 def D = "b1".U << 4 //cacheable: dcache 190 def S = "b1".U << 5 //enable speculative access 191 def A = "b1".U << 6 //enable atomic operation, A imply R & W 192 def C = "b1".U << 7 //if it is cacheable is configable 193 def Reserved = "b0".U 194 195 def apply() = UInt(7.W) 196 197 def read(mode: UInt) = mode(0) 198 def write(mode: UInt) = mode(1) 199 def execute(mode: UInt) = mode(2) 200 def icache(mode: UInt) = mode(3) 201 def dcache(mode: UInt) = mode(4) 202 def speculate(mode: UInt) = mode(5) 203 def atomic(mode: UInt) = mode(6) 204 def configable_cache(mode: UInt) = mode(7) 205 206 def strToMode(s: String) = { 207 var result = 0.U(8.W) 208 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 209 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 210 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 211 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 212 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 213 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 214 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 215 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 216 result 217 } 218 } 219 220 221 object CSROpType { 222 def jmp = "b000".U 223 def wrt = "b001".U 224 def set = "b010".U 225 def clr = "b011".U 226 def wfi = "b100".U 227 def wrti = "b101".U 228 def seti = "b110".U 229 def clri = "b111".U 230 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 231 } 232 233 // jump 234 object JumpOpType { 235 def jal = "b00".U 236 def jalr = "b01".U 237 def auipc = "b10".U 238// def call = "b11_011".U 239// def ret = "b11_100".U 240 def jumpOpisJalr(op: UInt) = op(0) 241 def jumpOpisAuipc(op: UInt) = op(1) 242 } 243 244 object FenceOpType { 245 def fence = "b10000".U 246 def sfence = "b10001".U 247 def fencei = "b10010".U 248 def nofence= "b00000".U 249 } 250 251 object ALUOpType { 252 // shift optype 253 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 254 def sll = "b000_0001".U // sll: src1 << src2 255 256 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 257 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 258 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 259 260 def srl = "b000_0101".U // srl: src1 >> src2 261 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 262 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 263 264 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 265 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 266 267 // RV64 32bit optype 268 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 269 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 270 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 271 272 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 273 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 274 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 275 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 276 277 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 278 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 279 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 280 def rolw = "b001_1100".U 281 def rorw = "b001_1101".U 282 283 // ADD-op 284 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 285 def add = "b010_0001".U // add: src1 + src2 286 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 287 288 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 289 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 290 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 291 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 292 293 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 294 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 295 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 296 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 297 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 298 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 299 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 300 301 // SUB-op: src1 - src2 302 def sub = "b011_0000".U 303 def sltu = "b011_0001".U 304 def slt = "b011_0010".U 305 def maxu = "b011_0100".U 306 def minu = "b011_0101".U 307 def max = "b011_0110".U 308 def min = "b011_0111".U 309 310 // branch 311 def beq = "b111_0000".U 312 def bne = "b111_0010".U 313 def blt = "b111_1000".U 314 def bge = "b111_1010".U 315 def bltu = "b111_1100".U 316 def bgeu = "b111_1110".U 317 318 // misc optype 319 def and = "b100_0000".U 320 def andn = "b100_0001".U 321 def or = "b100_0010".U 322 def orn = "b100_0011".U 323 def xor = "b100_0100".U 324 def xnor = "b100_0101".U 325 def orcb = "b100_0110".U 326 327 def sextb = "b100_1000".U 328 def packh = "b100_1001".U 329 def sexth = "b100_1010".U 330 def packw = "b100_1011".U 331 332 def revb = "b101_0000".U 333 def rev8 = "b101_0001".U 334 def pack = "b101_0010".U 335 def orh48 = "b101_0011".U 336 337 def szewl1 = "b101_1000".U 338 def szewl2 = "b101_1001".U 339 def szewl3 = "b101_1010".U 340 def byte2 = "b101_1011".U 341 342 def andlsb = "b110_0000".U 343 def andzexth = "b110_0001".U 344 def orlsb = "b110_0010".U 345 def orzexth = "b110_0011".U 346 def xorlsb = "b110_0100".U 347 def xorzexth = "b110_0101".U 348 def orcblsb = "b110_0110".U 349 def orcbzexth = "b110_0111".U 350 def vsetvli1 = "b1000_0000".U 351 def vsetvli2 = "b1000_0100".U 352 def vsetvl1 = "b1000_0001".U 353 def vsetvl2 = "b1000_0101".U 354 def vsetivli1 = "b1000_0010".U 355 def vsetivli2 = "b1000_0110".U 356 357 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 358 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 359 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 360 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 361 def isBranch(func: UInt) = func(6, 4) === "b111".U 362 def getBranchType(func: UInt) = func(3, 2) 363 def isBranchInvert(func: UInt) = func(1) 364 def isVset(func: UInt) = func(7, 3) === "b1000_0".U 365 def isVsetvl(func: UInt) = isVset(func) && func(0) 366 def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 367 def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 368 369 def apply() = UInt(FuOpTypeWidth.W) 370 } 371 372 object MDUOpType { 373 // mul 374 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 375 def mul = "b00000".U 376 def mulh = "b00001".U 377 def mulhsu = "b00010".U 378 def mulhu = "b00011".U 379 def mulw = "b00100".U 380 381 def mulw7 = "b01100".U 382 383 // div 384 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 385 def div = "b10000".U 386 def divu = "b10010".U 387 def rem = "b10001".U 388 def remu = "b10011".U 389 390 def divw = "b10100".U 391 def divuw = "b10110".U 392 def remw = "b10101".U 393 def remuw = "b10111".U 394 395 def isMul(op: UInt) = !op(4) 396 def isDiv(op: UInt) = op(4) 397 398 def isDivSign(op: UInt) = isDiv(op) && !op(1) 399 def isW(op: UInt) = op(2) 400 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 401 def getMulOp(op: UInt) = op(1, 0) 402 } 403 404 object LSUOpType { 405 // load pipeline 406 407 // normal load 408 // Note: bit(1, 0) are size, DO NOT CHANGE 409 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 410 def lb = "b0000".U 411 def lh = "b0001".U 412 def lw = "b0010".U 413 def ld = "b0011".U 414 def lbu = "b0100".U 415 def lhu = "b0101".U 416 def lwu = "b0110".U 417 418 // Zicbop software prefetch 419 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 420 def prefetch_i = "b1000".U // TODO 421 def prefetch_r = "b1001".U 422 def prefetch_w = "b1010".U 423 424 def isPrefetch(op: UInt): Bool = op(3) 425 426 // store pipeline 427 // normal store 428 // bit encoding: | store 00 | size(2bit) | 429 def sb = "b0000".U 430 def sh = "b0001".U 431 def sw = "b0010".U 432 def sd = "b0011".U 433 434 // l1 cache op 435 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 436 def cbo_zero = "b0111".U 437 438 // llc op 439 // bit encoding: | prefetch 11 | suboptype(2bit) | 440 def cbo_clean = "b1100".U 441 def cbo_flush = "b1101".U 442 def cbo_inval = "b1110".U 443 444 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 445 446 // atomics 447 // bit(1, 0) are size 448 // since atomics use a different fu type 449 // so we can safely reuse other load/store's encodings 450 // bit encoding: | optype(4bit) | size (2bit) | 451 def lr_w = "b000010".U 452 def sc_w = "b000110".U 453 def amoswap_w = "b001010".U 454 def amoadd_w = "b001110".U 455 def amoxor_w = "b010010".U 456 def amoand_w = "b010110".U 457 def amoor_w = "b011010".U 458 def amomin_w = "b011110".U 459 def amomax_w = "b100010".U 460 def amominu_w = "b100110".U 461 def amomaxu_w = "b101010".U 462 463 def lr_d = "b000011".U 464 def sc_d = "b000111".U 465 def amoswap_d = "b001011".U 466 def amoadd_d = "b001111".U 467 def amoxor_d = "b010011".U 468 def amoand_d = "b010111".U 469 def amoor_d = "b011011".U 470 def amomin_d = "b011111".U 471 def amomax_d = "b100011".U 472 def amominu_d = "b100111".U 473 def amomaxu_d = "b101011".U 474 475 def size(op: UInt) = op(1,0) 476 } 477 478 object BKUOpType { 479 480 def clmul = "b000000".U 481 def clmulh = "b000001".U 482 def clmulr = "b000010".U 483 def xpermn = "b000100".U 484 def xpermb = "b000101".U 485 486 def clz = "b001000".U 487 def clzw = "b001001".U 488 def ctz = "b001010".U 489 def ctzw = "b001011".U 490 def cpop = "b001100".U 491 def cpopw = "b001101".U 492 493 // 01xxxx is reserve 494 def aes64es = "b100000".U 495 def aes64esm = "b100001".U 496 def aes64ds = "b100010".U 497 def aes64dsm = "b100011".U 498 def aes64im = "b100100".U 499 def aes64ks1i = "b100101".U 500 def aes64ks2 = "b100110".U 501 502 // merge to two instruction sm4ks & sm4ed 503 def sm4ed0 = "b101000".U 504 def sm4ed1 = "b101001".U 505 def sm4ed2 = "b101010".U 506 def sm4ed3 = "b101011".U 507 def sm4ks0 = "b101100".U 508 def sm4ks1 = "b101101".U 509 def sm4ks2 = "b101110".U 510 def sm4ks3 = "b101111".U 511 512 def sha256sum0 = "b110000".U 513 def sha256sum1 = "b110001".U 514 def sha256sig0 = "b110010".U 515 def sha256sig1 = "b110011".U 516 def sha512sum0 = "b110100".U 517 def sha512sum1 = "b110101".U 518 def sha512sig0 = "b110110".U 519 def sha512sig1 = "b110111".U 520 521 def sm3p0 = "b111000".U 522 def sm3p1 = "b111001".U 523 } 524 525 object BTBtype { 526 def B = "b00".U // branch 527 def J = "b01".U // jump 528 def I = "b10".U // indirect 529 def R = "b11".U // return 530 531 def apply() = UInt(2.W) 532 } 533 534 object SelImm { 535 def IMM_X = "b0111".U 536 def IMM_S = "b0000".U 537 def IMM_SB = "b0001".U 538 def IMM_U = "b0010".U 539 def IMM_UJ = "b0011".U 540 def IMM_I = "b0100".U 541 def IMM_Z = "b0101".U 542 def INVALID_INSTR = "b0110".U 543 def IMM_B6 = "b1000".U 544 545 def IMM_OPIVIS = "b1001".U 546 def IMM_OPIVIU = "b1010".U 547 def IMM_VSETVLI = "b1100".U 548 def IMM_VSETIVLI = "b1101".U 549 550 def X = BitPat("b0000") 551 552 def apply() = UInt(4.W) 553 } 554 555 object ExceptionNO { 556 def instrAddrMisaligned = 0 557 def instrAccessFault = 1 558 def illegalInstr = 2 559 def breakPoint = 3 560 def loadAddrMisaligned = 4 561 def loadAccessFault = 5 562 def storeAddrMisaligned = 6 563 def storeAccessFault = 7 564 def ecallU = 8 565 def ecallS = 9 566 def ecallM = 11 567 def instrPageFault = 12 568 def loadPageFault = 13 569 // def singleStep = 14 570 def storePageFault = 15 571 def priorities = Seq( 572 breakPoint, // TODO: different BP has different priority 573 instrPageFault, 574 instrAccessFault, 575 illegalInstr, 576 instrAddrMisaligned, 577 ecallM, ecallS, ecallU, 578 storeAddrMisaligned, 579 loadAddrMisaligned, 580 storePageFault, 581 loadPageFault, 582 storeAccessFault, 583 loadAccessFault 584 ) 585 def all = priorities.distinct.sorted 586 def frontendSet = Seq( 587 instrAddrMisaligned, 588 instrAccessFault, 589 illegalInstr, 590 instrPageFault 591 ) 592 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 593 val new_vec = Wire(ExceptionVec()) 594 new_vec.foreach(_ := false.B) 595 select.foreach(i => new_vec(i) := vec(i)) 596 new_vec 597 } 598 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 599 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 600 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 601 partialSelect(vec, fuConfig.exceptionOut) 602 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 603 partialSelect(vec, exuConfig.exceptionOut) 604 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 605 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 606 } 607 608 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 609 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 610 def aluGen(p: Parameters) = new Alu()(p) 611 def bkuGen(p: Parameters) = new Bku()(p) 612 def jmpGen(p: Parameters) = new Jump()(p) 613 def fenceGen(p: Parameters) = new Fence()(p) 614 def csrGen(p: Parameters) = new CSR()(p) 615 def i2fGen(p: Parameters) = new IntToFP()(p) 616 def fmacGen(p: Parameters) = new FMA()(p) 617 def f2iGen(p: Parameters) = new FPToInt()(p) 618 def f2fGen(p: Parameters) = new FPToFP()(p) 619 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 620 def stdGen(p: Parameters) = new Std()(p) 621 def mouDataGen(p: Parameters) = new Std()(p) 622 def vipuGen(p: Parameters) = new VIPU()(p) 623 624 def f2iSel(uop: MicroOp): Bool = { 625 uop.ctrl.rfWen 626 } 627 628 def i2fSel(uop: MicroOp): Bool = { 629 uop.ctrl.fpu.fromInt 630 } 631 632 def f2fSel(uop: MicroOp): Bool = { 633 val ctrl = uop.ctrl.fpu 634 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 635 } 636 637 def fdivSqrtSel(uop: MicroOp): Bool = { 638 val ctrl = uop.ctrl.fpu 639 ctrl.div || ctrl.sqrt 640 } 641 642 val aluCfg = FuConfig( 643 name = "alu", 644 fuGen = aluGen, 645 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 646 fuType = FuType.alu, 647 numIntSrc = 2, 648 numFpSrc = 0, 649 writeIntRf = true, 650 writeFpRf = false, 651 hasRedirect = true, 652 ) 653 654 val jmpCfg = FuConfig( 655 name = "jmp", 656 fuGen = jmpGen, 657 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 658 fuType = FuType.jmp, 659 numIntSrc = 1, 660 numFpSrc = 0, 661 writeIntRf = true, 662 writeFpRf = false, 663 hasRedirect = true, 664 ) 665 666 val fenceCfg = FuConfig( 667 name = "fence", 668 fuGen = fenceGen, 669 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 670 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 671 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 672 flushPipe = true 673 ) 674 675 val csrCfg = FuConfig( 676 name = "csr", 677 fuGen = csrGen, 678 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 679 fuType = FuType.csr, 680 numIntSrc = 1, 681 numFpSrc = 0, 682 writeIntRf = true, 683 writeFpRf = false, 684 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 685 flushPipe = true 686 ) 687 688 val i2fCfg = FuConfig( 689 name = "i2f", 690 fuGen = i2fGen, 691 fuSel = i2fSel, 692 FuType.i2f, 693 numIntSrc = 1, 694 numFpSrc = 0, 695 writeIntRf = false, 696 writeFpRf = true, 697 writeFflags = true, 698 latency = CertainLatency(2), 699 fastUopOut = true, fastImplemented = true 700 ) 701 702 val divCfg = FuConfig( 703 name = "div", 704 fuGen = dividerGen, 705 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 706 FuType.div, 707 2, 708 0, 709 writeIntRf = true, 710 writeFpRf = false, 711 latency = UncertainLatency(), 712 fastUopOut = true, 713 fastImplemented = true, 714 hasInputBuffer = (true, 4, true) 715 ) 716 717 val mulCfg = FuConfig( 718 name = "mul", 719 fuGen = multiplierGen, 720 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 721 FuType.mul, 722 2, 723 0, 724 writeIntRf = true, 725 writeFpRf = false, 726 latency = CertainLatency(2), 727 fastUopOut = true, 728 fastImplemented = true 729 ) 730 731 val bkuCfg = FuConfig( 732 name = "bku", 733 fuGen = bkuGen, 734 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 735 fuType = FuType.bku, 736 numIntSrc = 2, 737 numFpSrc = 0, 738 writeIntRf = true, 739 writeFpRf = false, 740 latency = CertainLatency(1), 741 fastUopOut = true, 742 fastImplemented = true 743 ) 744 745 val fmacCfg = FuConfig( 746 name = "fmac", 747 fuGen = fmacGen, 748 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fmac, 749 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 750 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 751 ) 752 753 val f2iCfg = FuConfig( 754 name = "f2i", 755 fuGen = f2iGen, 756 fuSel = f2iSel, 757 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 758 fastUopOut = true, fastImplemented = true 759 ) 760 761 val f2fCfg = FuConfig( 762 name = "f2f", 763 fuGen = f2fGen, 764 fuSel = f2fSel, 765 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 766 fastUopOut = true, fastImplemented = true 767 ) 768 769 val fdivSqrtCfg = FuConfig( 770 name = "fdivSqrt", 771 fuGen = fdivSqrtGen, 772 fuSel = fdivSqrtSel, 773 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 774 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 775 ) 776 777 val lduCfg = FuConfig( 778 "ldu", 779 null, // DontCare 780 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 781 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 782 latency = UncertainLatency(), 783 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 784 flushPipe = true, 785 replayInst = true, 786 hasLoadError = true 787 ) 788 789 val staCfg = FuConfig( 790 "sta", 791 null, 792 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 793 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 794 latency = UncertainLatency(), 795 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 796 ) 797 798 val stdCfg = FuConfig( 799 "std", 800 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 801 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 802 ) 803 804 val mouCfg = FuConfig( 805 "mou", 806 null, 807 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 808 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 809 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 810 ) 811 812 val mouDataCfg = FuConfig( 813 "mou", 814 mouDataGen, 815 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 816 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 817 latency = UncertainLatency() 818 ) 819 820 val vipuCfg = FuConfig( 821 name = "vipu", 822 fuGen = vipuGen, 823 fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 824 fuType = FuType.vipu, 825 numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 826 numVecSrc = 2, writeVecRf = true, 827 fastUopOut = false, // TODO: check 828 fastImplemented = true, //TODO: check 829 ) 830 831 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 832 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 833 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 834 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 835 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0) 836 val FmiscExeUnitCfg = ExuConfig( 837 "FmiscExeUnit", 838 "Fp", 839 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 840 Int.MaxValue, 1 841 ) 842 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 843 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 844 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 845 846 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 847 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 848 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 849 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 850 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 851 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 852 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 853 854 val aluRSMod = new RSMod( 855 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 856 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 857 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 858 ) 859 val fmaRSMod = new RSMod( 860 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 861 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 862 ) 863 val fmiscRSMod = new RSMod( 864 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 865 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 866 ) 867 val jumpRSMod = new RSMod( 868 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 869 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 870 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 871 ) 872 val loadRSMod = new RSMod( 873 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 874 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 875 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 876 ) 877 val mulRSMod = new RSMod( 878 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 879 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 880 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 881 ) 882 val staRSMod = new RSMod( 883 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 884 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 885 ) 886 val stdRSMod = new RSMod( 887 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 888 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 889 ) 890} 891