1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.tile.XLen 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType===fp 40 def isPcOrImm(srcType: UInt) = srcType(0) 41 def isRegOrFp(srcType: UInt) = !srcType(1) 42 def regIsFp(srcType: UInt) = srcType(1) 43 44 def apply() = UInt(2.W) 45 } 46 47 object SrcState { 48 def busy = "b0".U 49 def rdy = "b1".U 50 // def specRdy = "b10".U // speculative ready, for future use 51 def apply() = UInt(1.W) 52 } 53 54 object FuType { 55 def jmp = "b0000".U 56 def i2f = "b0001".U 57 def csr = "b0010".U 58 def alu = "b0110".U 59 def mul = "b0100".U 60 def div = "b0101".U 61 def fence = "b0011".U 62 def bmu = "b0111".U 63 64 def fmac = "b1000".U 65 def fmisc = "b1011".U 66 def fDivSqrt = "b1010".U 67 68 def ldu = "b1100".U 69 def stu = "b1101".U 70 def mou = "b1111".U // for amo, lr, sc, fence 71 72 def num = 14 73 74 def apply() = UInt(log2Up(num).W) 75 76 def isIntExu(fuType: UInt) = !fuType(3) 77 def isJumpExu(fuType: UInt) = fuType === jmp 78 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 79 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 80 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 81 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 82 def isAMO(fuType: UInt) = fuType(1) 83 84 def jmpCanAccept(fuType: UInt) = !fuType(2) 85 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 86 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 87 88 def fmacCanAccept(fuType: UInt) = !fuType(1) 89 def fmiscCanAccept(fuType: UInt) = fuType(1) 90 91 def loadCanAccept(fuType: UInt) = !fuType(0) 92 def storeCanAccept(fuType: UInt) = fuType(0) 93 94 def storeIsAMO(fuType: UInt) = fuType(1) 95 96 val functionNameMap = Map( 97 jmp.litValue() -> "jmp", 98 i2f.litValue() -> "int_to_float", 99 csr.litValue() -> "csr", 100 alu.litValue() -> "alu", 101 mul.litValue() -> "mul", 102 div.litValue() -> "div", 103 fence.litValue() -> "fence", 104 bmu.litValue() -> "bmu", 105 fmac.litValue() -> "fmac", 106 fmisc.litValue() -> "fmisc", 107 fDivSqrt.litValue() -> "fdiv/fsqrt", 108 ldu.litValue() -> "load", 109 stu.litValue() -> "store", 110 mou.litValue() -> "mou" 111 ) 112 } 113 114 object FuOpType { 115 def apply() = UInt(8.W) 116 } 117 118 object CommitType { 119 def NORMAL = "b00".U // int/fp 120 def BRANCH = "b01".U // branch 121 def LOAD = "b10".U // load 122 def STORE = "b11".U // store 123 124 def apply() = UInt(2.W) 125 def isLoadStore(commitType: UInt) = commitType(1) 126 def lsInstIsStore(commitType: UInt) = commitType(0) 127 def isStore(commitType: UInt) = isLoadStore(commitType) && lsInstIsStore(commitType) 128 def isBranch(commitType: UInt) = commitType(0) && !commitType(1) 129 } 130 131 object RedirectLevel { 132 def flushAfter = "b0".U 133 def flush = "b1".U 134 135 def apply() = UInt(1.W) 136 // def isUnconditional(level: UInt) = level(1) 137 def flushItself(level: UInt) = level(0) 138 // def isException(level: UInt) = level(1) && level(0) 139 } 140 141 object ExceptionVec { 142 def apply() = Vec(16, Bool()) 143 } 144 145 object PMAMode { 146 def R = "b1".U << 0 //readable 147 def W = "b1".U << 1 //writeable 148 def X = "b1".U << 2 //executable 149 def I = "b1".U << 3 //cacheable: icache 150 def D = "b1".U << 4 //cacheable: dcache 151 def S = "b1".U << 5 //enable speculative access 152 def A = "b1".U << 6 //enable atomic operation, A imply R & W 153 def C = "b1".U << 7 //if it is cacheable is configable 154 def Reserved = "b0".U 155 156 def apply() = UInt(7.W) 157 158 def read(mode: UInt) = mode(0) 159 def write(mode: UInt) = mode(1) 160 def execute(mode: UInt) = mode(2) 161 def icache(mode: UInt) = mode(3) 162 def dcache(mode: UInt) = mode(4) 163 def speculate(mode: UInt) = mode(5) 164 def atomic(mode: UInt) = mode(6) 165 def configable_cache(mode: UInt) = mode(7) 166 167 def strToMode(s: String) = { 168 var result = 0.U(8.W) 169 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 170 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 171 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 172 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 173 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 174 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 175 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 176 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 177 result 178 } 179 } 180 181 182 object CSROpType { 183 def jmp = "b000".U 184 def wrt = "b001".U 185 def set = "b010".U 186 def clr = "b011".U 187 def wrti = "b101".U 188 def seti = "b110".U 189 def clri = "b111".U 190 } 191 192 // jump 193 object JumpOpType { 194 def jal = "b00".U 195 def jalr = "b01".U 196 def auipc = "b10".U 197// def call = "b11_011".U 198// def ret = "b11_100".U 199 def jumpOpisJalr(op: UInt) = op(0) 200 def jumpOpisAuipc(op: UInt) = op(1) 201 } 202 203 object FenceOpType { 204 def fence = "b10000".U 205 def sfence = "b10001".U 206 def fencei = "b10010".U 207 } 208 209 object ALUOpType { 210 // misc & branch optype 211 def and = "b0_00_00_000".U 212 def andn = "b0_00_00_001".U 213 def or = "b0_00_00_010".U 214 def orn = "b0_00_00_011".U 215 def xor = "b0_00_00_100".U 216 def xnor = "b0_00_00_101".U 217 def orh48 = "b0_00_00_110".U 218 def orc_b = "b0_00_00_111".U 219 220 def andlsb = "b0_00_11_000".U 221 def andnlsb = "b0_00_11_001".U 222 def orlsb = "b0_00_11_010".U 223 def ornlsb = "b0_00_11_011".U 224 def xorlsb = "b0_00_11_100".U 225 def xnorlsb = "b0_00_11_101".U 226 227 def sext_b = "b0_00_01_000".U 228 def sext_h = "b0_00_01_001".U 229 // def zext_h = "b0_00_01_010".U // packw 230 def rev8 = "b0_00_01_011".U 231 // TOOD: optimize it 232 def szewl1 = "b0_00_01_100".U 233 def szewl2 = "b0_00_01_101".U 234 def szewl3 = "b0_00_01_110".U 235 def byte2 = "b0_00_01_111".U 236 237 def beq = "b0_00_10_000".U 238 def bne = "b0_00_10_001".U 239 def blt = "b0_00_10_100".U 240 def bge = "b0_00_10_101".U 241 def bltu = "b0_00_10_110".U 242 def bgeu = "b0_00_10_111".U 243 244 // add & sub optype 245 def add_uw = "b0_01_00_000".U 246 def add = "b0_01_00_001".U 247 248 def oddadd = "b0_01_11_001".U 249 250 def sh1add_uw = "b0_01_10_000".U 251 def sh1add = "b0_01_10_001".U 252 def sh2add_uw = "b0_01_10_010".U 253 def sh2add = "b0_01_10_011".U 254 def sh3add_uw = "b0_01_10_100".U 255 def sh3add = "b0_01_10_101".U 256 def sh4add = "b0_01_10_111".U 257 258 def sr29add = "b0_01_01_001".U 259 def sr30add = "b0_01_01_011".U 260 def sr31add = "b0_01_01_101".U 261 def sr32add = "b0_01_01_111".U 262 263 // shift optype 264 def slli_uw = "b0_10_00_000".U 265 def sll = "b0_10_00_001".U 266 def bclr = "b0_10_00_100".U 267 def bset = "b0_10_00_101".U 268 def binv = "b0_10_00_110".U 269 270 def srl = "b0_10_01_001".U 271 def bext = "b0_10_01_010".U 272 def sra = "b0_10_01_100".U 273 274 def rol = "b0_10_10_000".U 275 276 def ror = "b0_10_11_000".U 277 278 def sub = "b0_11_00_000".U 279 def sltu = "b0_11_00_001".U 280 def slt = "b0_11_00_010".U 281 def maxu = "b0_11_00_100".U 282 def minu = "b0_11_00_101".U 283 def max = "b0_11_00_110".U 284 def min = "b0_11_00_111".U 285 286 // RV64 32bit optype 287 def addw = "b1_01_00_001".U 288 def addwbyte = "b1_01_00_011".U 289 def addwbit = "b1_01_00_101".U 290 def oddaddw = "b1_01_11_001".U 291 def subw = "b1_11_00_000".U 292 def sllw = "b1_10_00_000".U 293 def srlw = "b1_10_01_001".U 294 def sraw = "b1_10_01_100".U 295 def rolw = "b1_10_10_000".U 296 def rorw = "b1_10_11_000".U 297 298 def isWordOp(func: UInt) = func(7) 299 def isAddw(func: UInt) = func(7, 5) === "b101".U 300 def isLogic(func: UInt) = func(7, 3) === "b00000".U 301 def logicToLSB(func: UInt) = Cat(func(7, 5), "b11".U(2.W), func(2, 0)) 302 def isBranch(func: UInt) = func(6, 3) === "b0010".U 303 def getBranchType(func: UInt) = func(2, 1) 304 def isBranchInvert(func: UInt) = func(0) 305 def isAddOddBit(func: UInt) = func(4, 3) === "b11".U(2.W) 306 def isShAdd(func: UInt) = func(4, 3) === "b10".U(2.W) 307 def isSrAdd(func: UInt) = func(4, 3) === "b01".U(2.W) 308 309 def apply() = UInt(8.W) 310 } 311 312 object MDUOpType { 313 // mul 314 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 315 def mul = "b00000".U 316 def mulh = "b00001".U 317 def mulhsu = "b00010".U 318 def mulhu = "b00011".U 319 def mulw = "b00100".U 320 321 def mulw7 = "b01100".U 322 323 // div 324 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 325 def div = "b10000".U 326 def divu = "b10010".U 327 def rem = "b10001".U 328 def remu = "b10011".U 329 330 def divw = "b10100".U 331 def divuw = "b10110".U 332 def remw = "b10101".U 333 def remuw = "b10111".U 334 335 def isMul(op: UInt) = !op(4) 336 def isDiv(op: UInt) = op(4) 337 338 def isDivSign(op: UInt) = isDiv(op) && !op(1) 339 def isW(op: UInt) = op(2) 340 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 341 def getMulOp(op: UInt) = op(1, 0) 342 } 343 344 object LSUOpType { 345 // normal load/store 346 // bit(1, 0) are size 347 def lb = "b000000".U 348 def lh = "b000001".U 349 def lw = "b000010".U 350 def ld = "b000011".U 351 def lbu = "b000100".U 352 def lhu = "b000101".U 353 def lwu = "b000110".U 354 def sb = "b001000".U 355 def sh = "b001001".U 356 def sw = "b001010".U 357 def sd = "b001011".U 358 359 def isLoad(op: UInt): Bool = !op(3) 360 def isStore(op: UInt): Bool = op(3) 361 362 // atomics 363 // bit(1, 0) are size 364 // since atomics use a different fu type 365 // so we can safely reuse other load/store's encodings 366 def lr_w = "b000010".U 367 def sc_w = "b000110".U 368 def amoswap_w = "b001010".U 369 def amoadd_w = "b001110".U 370 def amoxor_w = "b010010".U 371 def amoand_w = "b010110".U 372 def amoor_w = "b011010".U 373 def amomin_w = "b011110".U 374 def amomax_w = "b100010".U 375 def amominu_w = "b100110".U 376 def amomaxu_w = "b101010".U 377 378 def lr_d = "b000011".U 379 def sc_d = "b000111".U 380 def amoswap_d = "b001011".U 381 def amoadd_d = "b001111".U 382 def amoxor_d = "b010011".U 383 def amoand_d = "b010111".U 384 def amoor_d = "b011011".U 385 def amomin_d = "b011111".U 386 def amomax_d = "b100011".U 387 def amominu_d = "b100111".U 388 def amomaxu_d = "b101011".U 389 } 390 391 object BMUOpType { 392 393 def clmul = "b00000".U 394 def clmulh = "b00010".U 395 def clmulr = "b00100".U 396 397 def clz = "b01000".U 398 def clzw = "b01001".U 399 def ctz = "b01010".U 400 def ctzw = "b01011".U 401 def cpop = "b01100".U 402 def cpopw = "b01101".U 403 404 // TODO: move to alu 405 def xpermn = "b10000".U 406 def xpermb = "b10001".U 407 def pack = "b10100".U 408 def packh = "b10101".U 409 def packw = "b10110".U 410 def revb = "b11000".U 411 } 412 413 object BTBtype { 414 def B = "b00".U // branch 415 def J = "b01".U // jump 416 def I = "b10".U // indirect 417 def R = "b11".U // return 418 419 def apply() = UInt(2.W) 420 } 421 422 object SelImm { 423 def IMM_X = "b0111".U 424 def IMM_S = "b0000".U 425 def IMM_SB = "b0001".U 426 def IMM_U = "b0010".U 427 def IMM_UJ = "b0011".U 428 def IMM_I = "b0100".U 429 def IMM_Z = "b0101".U 430 def INVALID_INSTR = "b0110".U 431 def IMM_B6 = "b1000".U 432 433 def apply() = UInt(4.W) 434 } 435 436 def dividerGen(p: Parameters) = new SRT16Divider(p(XLen))(p) 437 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 438 def aluGen(p: Parameters) = new Alu()(p) 439 def bmuGen(p: Parameters) = new Bmu()(p) 440 def jmpGen(p: Parameters) = new Jump()(p) 441 def fenceGen(p: Parameters) = new Fence()(p) 442 def csrGen(p: Parameters) = new CSR()(p) 443 def i2fGen(p: Parameters) = new IntToFP()(p) 444 def fmacGen(p: Parameters) = new FMA()(p) 445 def f2iGen(p: Parameters) = new FPToInt()(p) 446 def f2fGen(p: Parameters) = new FPToFP()(p) 447 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 448 def stdGen(p: Parameters) = new Std()(p) 449 450 def f2iSel(uop: MicroOp): Bool = { 451 uop.ctrl.rfWen 452 } 453 454 def i2fSel(uop: MicroOp): Bool = { 455 uop.ctrl.fpu.fromInt 456 } 457 458 def f2fSel(uop: MicroOp): Bool = { 459 val ctrl = uop.ctrl.fpu 460 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 461 } 462 463 def fdivSqrtSel(uop: MicroOp): Bool = { 464 val ctrl = uop.ctrl.fpu 465 ctrl.div || ctrl.sqrt 466 } 467 468 val aluCfg = FuConfig( 469 name = "alu", 470 fuGen = aluGen, 471 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 472 fuType = FuType.alu, 473 numIntSrc = 2, 474 numFpSrc = 0, 475 writeIntRf = true, 476 writeFpRf = false, 477 hasRedirect = true, 478 ) 479 480 val jmpCfg = FuConfig( 481 name = "jmp", 482 fuGen = jmpGen, 483 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 484 fuType = FuType.jmp, 485 numIntSrc = 1, 486 numFpSrc = 0, 487 writeIntRf = true, 488 writeFpRf = false, 489 hasRedirect = true, 490 ) 491 492 val fenceCfg = FuConfig( 493 name = "fence", 494 fuGen = fenceGen, 495 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 496 FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 497 latency = UncertainLatency(), // TODO: need rewrite latency structure, not just this value, 498 hasExceptionOut = true 499 ) 500 501 val csrCfg = FuConfig( 502 name = "csr", 503 fuGen = csrGen, 504 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 505 fuType = FuType.csr, 506 numIntSrc = 1, 507 numFpSrc = 0, 508 writeIntRf = true, 509 writeFpRf = false, 510 hasRedirect = false, 511 hasExceptionOut = true 512 ) 513 514 val i2fCfg = FuConfig( 515 name = "i2f", 516 fuGen = i2fGen, 517 fuSel = i2fSel, 518 FuType.i2f, 519 numIntSrc = 1, 520 numFpSrc = 0, 521 writeIntRf = false, 522 writeFpRf = true, 523 hasRedirect = false, 524 latency = CertainLatency(2), 525 fastUopOut = true, fastImplemented = true 526 ) 527 528 val divCfg = FuConfig( 529 name = "div", 530 fuGen = dividerGen, 531 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 532 FuType.div, 533 2, 534 0, 535 writeIntRf = true, 536 writeFpRf = false, 537 hasRedirect = false, 538 latency = UncertainLatency(), 539 fastUopOut = true, 540 fastImplemented = false 541 ) 542 543 val mulCfg = FuConfig( 544 name = "mul", 545 fuGen = multiplierGen, 546 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 547 FuType.mul, 548 2, 549 0, 550 writeIntRf = true, 551 writeFpRf = false, 552 hasRedirect = false, 553 latency = CertainLatency(2), 554 fastUopOut = true, 555 fastImplemented = true 556 ) 557 558 val bmuCfg = FuConfig( 559 name = "bmu", 560 fuGen = bmuGen, 561 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bmu, 562 fuType = FuType.bmu, 563 numIntSrc = 2, 564 numFpSrc = 0, 565 writeIntRf = true, 566 writeFpRf = false, 567 hasRedirect = false, 568 latency = CertainLatency(1), 569 fastUopOut = true, 570 fastImplemented = true 571 ) 572 573 val fmacCfg = FuConfig( 574 name = "fmac", 575 fuGen = fmacGen, 576 fuSel = _ => true.B, 577 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, 578 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 579 ) 580 581 val f2iCfg = FuConfig( 582 name = "f2i", 583 fuGen = f2iGen, 584 fuSel = f2iSel, 585 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2), 586 fastUopOut = true, fastImplemented = true 587 ) 588 589 val f2fCfg = FuConfig( 590 name = "f2f", 591 fuGen = f2fGen, 592 fuSel = f2fSel, 593 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2), 594 fastUopOut = true, fastImplemented = true 595 ) 596 597 val fdivSqrtCfg = FuConfig( 598 name = "fdivSqrt", 599 fuGen = fdivSqrtGen, 600 fuSel = fdivSqrtSel, 601 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency(), 602 fastUopOut = true, fastImplemented = false, hasInputBuffer = true 603 ) 604 605 val lduCfg = FuConfig( 606 "ldu", 607 null, // DontCare 608 null, 609 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 610 latency = UncertainLatency(), hasExceptionOut = true 611 ) 612 613 val staCfg = FuConfig( 614 "sta", 615 null, 616 null, 617 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 618 latency = UncertainLatency(), hasExceptionOut = true 619 ) 620 621 val stdCfg = FuConfig( 622 "std", 623 fuGen = stdGen, fuSel = _ => true.B, FuType.stu, 1, 1, 624 writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = CertainLatency(1) 625 ) 626 627 val mouCfg = FuConfig( 628 "mou", 629 null, 630 null, 631 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 632 latency = UncertainLatency(), hasExceptionOut = true 633 ) 634 635 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 636 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 637 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 638 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bmuCfg), 1, Int.MaxValue) 639 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 640 val FmiscExeUnitCfg = ExuConfig( 641 "FmiscExeUnit", 642 "Fp", 643 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 644 Int.MaxValue, 1 645 ) 646 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0) 647 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 648 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 649} 650