1c6d43980SLemover/*************************************************************************************** 2c6d43980SLemover* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3f320e0f0SYinan Xu* Copyright (c) 2020-2021 Peng Cheng Laboratory 4c6d43980SLemover* 5c6d43980SLemover* XiangShan is licensed under Mulan PSL v2. 6c6d43980SLemover* You can use this software according to the terms and conditions of the Mulan PSL v2. 7c6d43980SLemover* You may obtain a copy of Mulan PSL v2 at: 8c6d43980SLemover* http://license.coscl.org.cn/MulanPSL2 9c6d43980SLemover* 10c6d43980SLemover* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11c6d43980SLemover* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12c6d43980SLemover* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13c6d43980SLemover* 14c6d43980SLemover* See the Mulan PSL v2 for more details. 15c6d43980SLemover***************************************************************************************/ 16c6d43980SLemover 179a2e6b8aSLinJiaweiimport chisel3._ 189a2e6b8aSLinJiaweiimport chisel3.util._ 192225d46eSJiawei Linimport chipsalliance.rocketchip.config.Parameters 202225d46eSJiawei Linimport freechips.rocketchip.tile.XLen 216ab6918fSYinan Xuimport xiangshan.ExceptionNO._ 2254034ccdSZhangZifeiimport xiangshan.backend.issue._ 232225d46eSJiawei Linimport xiangshan.backend.fu._ 242225d46eSJiawei Linimport xiangshan.backend.fu.fpu._ 256827759bSZhangZifeiimport xiangshan.backend.fu.vector._ 262225d46eSJiawei Linimport xiangshan.backend.exu._ 2754034ccdSZhangZifeiimport xiangshan.backend.{Std, ScheLaneConfig} 282225d46eSJiawei Lin 299a2e6b8aSLinJiaweipackage object xiangshan { 309ee9f926SYikeZhou object SrcType { 311285b047SXuan Hu def imm = "b000".U 321285b047SXuan Hu def pc = "b000".U 331285b047SXuan Hu def xp = "b001".U 341285b047SXuan Hu def fp = "b010".U 351285b047SXuan Hu def vp = "b100".U 3604b56283SZhangZifei 371285b047SXuan Hu // alias 381285b047SXuan Hu def reg = this.xp 391a3df1feSYikeZhou def DC = imm // Don't Care 4057a10886SXuan Hu def X = BitPat("b000") 414d24c305SYikeZhou 4204b56283SZhangZifei def isPc(srcType: UInt) = srcType===pc 4304b56283SZhangZifei def isImm(srcType: UInt) = srcType===imm 441285b047SXuan Hu def isReg(srcType: UInt) = srcType(0) 452b4e8253SYinan Xu def isFp(srcType: UInt) = srcType(1) 461285b047SXuan Hu def isVp(srcType: UInt) = srcType(2) 471285b047SXuan Hu def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 4804b56283SZhangZifei 49f062e05dSZhangZifei def isNull(srcType: UInt) = !(isPcOrImm(srcType) || isReg(srcType) || 50f062e05dSZhangZifei isFp(srcType) || isVp(srcType)) 51f062e05dSZhangZifei 521285b047SXuan Hu def apply() = UInt(3.W) 539a2e6b8aSLinJiawei } 549a2e6b8aSLinJiawei 559a2e6b8aSLinJiawei object SrcState { 56100aa93cSYinan Xu def busy = "b0".U 57100aa93cSYinan Xu def rdy = "b1".U 58100aa93cSYinan Xu // def specRdy = "b10".U // speculative ready, for future use 59100aa93cSYinan Xu def apply() = UInt(1.W) 609a2e6b8aSLinJiawei } 619a2e6b8aSLinJiawei 627f2b7720SXuan Hu // Todo: Use OH instead 632225d46eSJiawei Lin object FuType { 6457a10886SXuan Hu def jmp = "b00000".U 6557a10886SXuan Hu def i2f = "b00001".U 6657a10886SXuan Hu def csr = "b00010".U 6757a10886SXuan Hu def alu = "b00110".U 6857a10886SXuan Hu def mul = "b00100".U 6957a10886SXuan Hu def div = "b00101".U 7057a10886SXuan Hu def fence = "b00011".U 7157a10886SXuan Hu def bku = "b00111".U 72cafb3558SLinJiawei 7357a10886SXuan Hu def fmac = "b01000".U 7457a10886SXuan Hu def fmisc = "b01011".U 7557a10886SXuan Hu def fDivSqrt = "b01010".U 76cafb3558SLinJiawei 7757a10886SXuan Hu def ldu = "b01100".U 7857a10886SXuan Hu def stu = "b01101".U 7957a10886SXuan Hu def mou = "b01111".U // for amo, lr, sc, fence 80*99e169c5Sczw 8157a10886SXuan Hu def vipu = "b10000".U 8257a10886SXuan Hu def vfpu = "b11000".U 837f2b7720SXuan Hu def vldu = "b11100".U 847f2b7720SXuan Hu def vstu = "b11101".U 85*99e169c5Sczw def vppu = "b11001".U // for Permutation Unit 86*99e169c5Sczw def X = BitPat("b00000") // TODO: It may be a potential bug 876e7c9679Shuxuan0307 88*99e169c5Sczw def num = 19 892225d46eSJiawei Lin 909a2e6b8aSLinJiawei def apply() = UInt(log2Up(num).W) 919a2e6b8aSLinJiawei 920f038924SZhangZifei // TODO: Optimize FuTpye and its method 930f038924SZhangZifei // FIXME: Vector FuType coding is not ready 940f038924SZhangZifei def isVecExu(fuType: UInt) = fuType(4) 950f038924SZhangZifei def isIntExu(fuType: UInt) = !isVecExu(fuType) && !fuType(3) 966ac289b3SLinJiawei def isJumpExu(fuType: UInt) = fuType === jmp 970f038924SZhangZifei def isFpExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b10".U) 980f038924SZhangZifei def isMemExu(fuType: UInt) = !isVecExu(fuType) && (fuType(3, 2) === "b11".U) 9992ab24ebSYinan Xu def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 10092ab24ebSYinan Xu def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 1010f9d3717SYinan Xu def isAMO(fuType: UInt) = fuType(1) 102af2f7849Shappy-lx def isFence(fuType: UInt) = fuType === fence 103af2f7849Shappy-lx def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 104af2f7849Shappy-lx def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 105af2f7849Shappy-lx def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 10692ab24ebSYinan Xu 10792ab24ebSYinan Xu def jmpCanAccept(fuType: UInt) = !fuType(2) 108ee8ff153Szfw def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 109ee8ff153Szfw def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 11092ab24ebSYinan Xu 11192ab24ebSYinan Xu def fmacCanAccept(fuType: UInt) = !fuType(1) 11292ab24ebSYinan Xu def fmiscCanAccept(fuType: UInt) = fuType(1) 11392ab24ebSYinan Xu 11492ab24ebSYinan Xu def loadCanAccept(fuType: UInt) = !fuType(0) 11592ab24ebSYinan Xu def storeCanAccept(fuType: UInt) = fuType(0) 11692ab24ebSYinan Xu 11792ab24ebSYinan Xu def storeIsAMO(fuType: UInt) = fuType(1) 118cafb3558SLinJiawei 119cafb3558SLinJiawei val functionNameMap = Map( 120cafb3558SLinJiawei jmp.litValue() -> "jmp", 121ebb8ebf8SYinan Xu i2f.litValue() -> "int_to_float", 122cafb3558SLinJiawei csr.litValue() -> "csr", 123cafb3558SLinJiawei alu.litValue() -> "alu", 124cafb3558SLinJiawei mul.litValue() -> "mul", 125cafb3558SLinJiawei div.litValue() -> "div", 126b8f08ca0SZhangZifei fence.litValue() -> "fence", 1273feeca58Szfw bku.litValue() -> "bku", 128cafb3558SLinJiawei fmac.litValue() -> "fmac", 129cafb3558SLinJiawei fmisc.litValue() -> "fmisc", 130d18dc7e6Swakafa fDivSqrt.litValue() -> "fdiv_fsqrt", 131cafb3558SLinJiawei ldu.litValue() -> "load", 132ebb8ebf8SYinan Xu stu.litValue() -> "store", 133ebb8ebf8SYinan Xu mou.litValue() -> "mou" 134cafb3558SLinJiawei ) 1359a2e6b8aSLinJiawei } 1369a2e6b8aSLinJiawei 13757a10886SXuan Hu def FuOpTypeWidth = 8 1382225d46eSJiawei Lin object FuOpType { 13957a10886SXuan Hu def apply() = UInt(FuOpTypeWidth.W) 14057a10886SXuan Hu def X = BitPat("b00000000") 141ebd97ecbSzhanglinjuan } 142518d8658SYinan Xu 1433a2e64c4SZhangZifei // move VipuType and VfpuType into YunSuan/package.scala 1443a2e64c4SZhangZifei // object VipuType { 1453a2e64c4SZhangZifei // def dummy = 0.U(7.W) 1463a2e64c4SZhangZifei // } 1477f2b7720SXuan Hu 1483a2e64c4SZhangZifei // object VfpuType { 1493a2e64c4SZhangZifei // def dummy = 0.U(7.W) 1503a2e64c4SZhangZifei // } 1517f2b7720SXuan Hu 1527f2b7720SXuan Hu object VlduType { 15357a10886SXuan Hu def dummy = 0.U 1547f2b7720SXuan Hu } 1557f2b7720SXuan Hu 1567f2b7720SXuan Hu object VstuType { 15757a10886SXuan Hu def dummy = 0.U 1587f2b7720SXuan Hu } 1597f2b7720SXuan Hu 160a3edac52SYinan Xu object CommitType { 161c3abb8b6SYinan Xu def NORMAL = "b000".U // int/fp 162c3abb8b6SYinan Xu def BRANCH = "b001".U // branch 163c3abb8b6SYinan Xu def LOAD = "b010".U // load 164c3abb8b6SYinan Xu def STORE = "b011".U // store 165518d8658SYinan Xu 166c3abb8b6SYinan Xu def apply() = UInt(3.W) 167c3abb8b6SYinan Xu def isFused(commitType: UInt): Bool = commitType(2) 168c3abb8b6SYinan Xu def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 169c3abb8b6SYinan Xu def lsInstIsStore(commitType: UInt): Bool = commitType(0) 170c3abb8b6SYinan Xu def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 171c3abb8b6SYinan Xu def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 172518d8658SYinan Xu } 173bfb958a3SYinan Xu 174bfb958a3SYinan Xu object RedirectLevel { 1752d7c7105SYinan Xu def flushAfter = "b0".U 1762d7c7105SYinan Xu def flush = "b1".U 177bfb958a3SYinan Xu 1782d7c7105SYinan Xu def apply() = UInt(1.W) 1792d7c7105SYinan Xu // def isUnconditional(level: UInt) = level(1) 180bfb958a3SYinan Xu def flushItself(level: UInt) = level(0) 1812d7c7105SYinan Xu // def isException(level: UInt) = level(1) && level(0) 182bfb958a3SYinan Xu } 183baf8def6SYinan Xu 184baf8def6SYinan Xu object ExceptionVec { 185baf8def6SYinan Xu def apply() = Vec(16, Bool()) 186baf8def6SYinan Xu } 187a8e04b1dSYinan Xu 188c60c1ab4SWilliam Wang object PMAMode { 1898d9a04fcSWilliam Wang def R = "b1".U << 0 //readable 1908d9a04fcSWilliam Wang def W = "b1".U << 1 //writeable 1918d9a04fcSWilliam Wang def X = "b1".U << 2 //executable 1928d9a04fcSWilliam Wang def I = "b1".U << 3 //cacheable: icache 1938d9a04fcSWilliam Wang def D = "b1".U << 4 //cacheable: dcache 1948d9a04fcSWilliam Wang def S = "b1".U << 5 //enable speculative access 195cff68e26SWilliam Wang def A = "b1".U << 6 //enable atomic operation, A imply R & W 1968d9a04fcSWilliam Wang def C = "b1".U << 7 //if it is cacheable is configable 197c60c1ab4SWilliam Wang def Reserved = "b0".U 198c60c1ab4SWilliam Wang 199c60c1ab4SWilliam Wang def apply() = UInt(7.W) 200c60c1ab4SWilliam Wang 201c60c1ab4SWilliam Wang def read(mode: UInt) = mode(0) 202c60c1ab4SWilliam Wang def write(mode: UInt) = mode(1) 203c60c1ab4SWilliam Wang def execute(mode: UInt) = mode(2) 204c60c1ab4SWilliam Wang def icache(mode: UInt) = mode(3) 205c60c1ab4SWilliam Wang def dcache(mode: UInt) = mode(4) 206c60c1ab4SWilliam Wang def speculate(mode: UInt) = mode(5) 207c60c1ab4SWilliam Wang def atomic(mode: UInt) = mode(6) 208c60c1ab4SWilliam Wang def configable_cache(mode: UInt) = mode(7) 209c60c1ab4SWilliam Wang 210c60c1ab4SWilliam Wang def strToMode(s: String) = { 211423b9255SWilliam Wang var result = 0.U(8.W) 212c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("R") >= 0) result = result + R 213c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("W") >= 0) result = result + W 214c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("X") >= 0) result = result + X 215c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("I") >= 0) result = result + I 216c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("D") >= 0) result = result + D 217c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("S") >= 0) result = result + S 218c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("A") >= 0) result = result + A 219c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("C") >= 0) result = result + C 220c60c1ab4SWilliam Wang result 221c60c1ab4SWilliam Wang } 222c60c1ab4SWilliam Wang } 2232225d46eSJiawei Lin 2242225d46eSJiawei Lin 2252225d46eSJiawei Lin object CSROpType { 2262225d46eSJiawei Lin def jmp = "b000".U 2272225d46eSJiawei Lin def wrt = "b001".U 2282225d46eSJiawei Lin def set = "b010".U 2292225d46eSJiawei Lin def clr = "b011".U 230b6900d94SYinan Xu def wfi = "b100".U 2312225d46eSJiawei Lin def wrti = "b101".U 2322225d46eSJiawei Lin def seti = "b110".U 2332225d46eSJiawei Lin def clri = "b111".U 2345d669833SYinan Xu def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 2352225d46eSJiawei Lin } 2362225d46eSJiawei Lin 2372225d46eSJiawei Lin // jump 2382225d46eSJiawei Lin object JumpOpType { 2392225d46eSJiawei Lin def jal = "b00".U 2402225d46eSJiawei Lin def jalr = "b01".U 2412225d46eSJiawei Lin def auipc = "b10".U 2422225d46eSJiawei Lin// def call = "b11_011".U 2432225d46eSJiawei Lin// def ret = "b11_100".U 2442225d46eSJiawei Lin def jumpOpisJalr(op: UInt) = op(0) 2452225d46eSJiawei Lin def jumpOpisAuipc(op: UInt) = op(1) 2462225d46eSJiawei Lin } 2472225d46eSJiawei Lin 2482225d46eSJiawei Lin object FenceOpType { 2492225d46eSJiawei Lin def fence = "b10000".U 2502225d46eSJiawei Lin def sfence = "b10001".U 2512225d46eSJiawei Lin def fencei = "b10010".U 252af2f7849Shappy-lx def nofence= "b00000".U 2532225d46eSJiawei Lin } 2542225d46eSJiawei Lin 2552225d46eSJiawei Lin object ALUOpType { 256ee8ff153Szfw // shift optype 257675acc68SYinan Xu def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 258675acc68SYinan Xu def sll = "b000_0001".U // sll: src1 << src2 259ee8ff153Szfw 260675acc68SYinan Xu def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 261675acc68SYinan Xu def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 262675acc68SYinan Xu def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 263ee8ff153Szfw 264675acc68SYinan Xu def srl = "b000_0101".U // srl: src1 >> src2 265675acc68SYinan Xu def bext = "b000_0110".U // bext: (src1 >> src2)[0] 266675acc68SYinan Xu def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 267ee8ff153Szfw 2687b441e5eSYinan Xu def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 2697b441e5eSYinan Xu def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 270184a1958Szfw 271ee8ff153Szfw // RV64 32bit optype 272675acc68SYinan Xu def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 273675acc68SYinan Xu def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 274675acc68SYinan Xu def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 275ee8ff153Szfw 276675acc68SYinan Xu def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 277675acc68SYinan Xu def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 278675acc68SYinan Xu def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 279675acc68SYinan Xu def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 280ee8ff153Szfw 281675acc68SYinan Xu def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 282675acc68SYinan Xu def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 283675acc68SYinan Xu def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 284675acc68SYinan Xu def rolw = "b001_1100".U 285675acc68SYinan Xu def rorw = "b001_1101".U 286675acc68SYinan Xu 287675acc68SYinan Xu // ADD-op 288675acc68SYinan Xu def adduw = "b010_0000".U // adduw: src1[31:0] + src2 289675acc68SYinan Xu def add = "b010_0001".U // add: src1 + src2 290675acc68SYinan Xu def oddadd = "b010_0010".U // oddadd: src1[0] + src2 291675acc68SYinan Xu 292675acc68SYinan Xu def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 293675acc68SYinan Xu def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 294675acc68SYinan Xu def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 295675acc68SYinan Xu def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 296675acc68SYinan Xu 297675acc68SYinan Xu def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 298675acc68SYinan Xu def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 299675acc68SYinan Xu def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 300675acc68SYinan Xu def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 301675acc68SYinan Xu def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 302675acc68SYinan Xu def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 303675acc68SYinan Xu def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 304675acc68SYinan Xu 305675acc68SYinan Xu // SUB-op: src1 - src2 306675acc68SYinan Xu def sub = "b011_0000".U 307675acc68SYinan Xu def sltu = "b011_0001".U 308675acc68SYinan Xu def slt = "b011_0010".U 309675acc68SYinan Xu def maxu = "b011_0100".U 310675acc68SYinan Xu def minu = "b011_0101".U 311675acc68SYinan Xu def max = "b011_0110".U 312675acc68SYinan Xu def min = "b011_0111".U 313675acc68SYinan Xu 314675acc68SYinan Xu // branch 315675acc68SYinan Xu def beq = "b111_0000".U 316675acc68SYinan Xu def bne = "b111_0010".U 317675acc68SYinan Xu def blt = "b111_1000".U 318675acc68SYinan Xu def bge = "b111_1010".U 319675acc68SYinan Xu def bltu = "b111_1100".U 320675acc68SYinan Xu def bgeu = "b111_1110".U 321675acc68SYinan Xu 322675acc68SYinan Xu // misc optype 323675acc68SYinan Xu def and = "b100_0000".U 324675acc68SYinan Xu def andn = "b100_0001".U 325675acc68SYinan Xu def or = "b100_0010".U 326675acc68SYinan Xu def orn = "b100_0011".U 327675acc68SYinan Xu def xor = "b100_0100".U 328675acc68SYinan Xu def xnor = "b100_0101".U 329675acc68SYinan Xu def orcb = "b100_0110".U 330675acc68SYinan Xu 331675acc68SYinan Xu def sextb = "b100_1000".U 332675acc68SYinan Xu def packh = "b100_1001".U 333675acc68SYinan Xu def sexth = "b100_1010".U 334675acc68SYinan Xu def packw = "b100_1011".U 335675acc68SYinan Xu 336675acc68SYinan Xu def revb = "b101_0000".U 337675acc68SYinan Xu def rev8 = "b101_0001".U 338675acc68SYinan Xu def pack = "b101_0010".U 339675acc68SYinan Xu def orh48 = "b101_0011".U 340675acc68SYinan Xu 341675acc68SYinan Xu def szewl1 = "b101_1000".U 342675acc68SYinan Xu def szewl2 = "b101_1001".U 343675acc68SYinan Xu def szewl3 = "b101_1010".U 344675acc68SYinan Xu def byte2 = "b101_1011".U 345675acc68SYinan Xu 346675acc68SYinan Xu def andlsb = "b110_0000".U 347675acc68SYinan Xu def andzexth = "b110_0001".U 348675acc68SYinan Xu def orlsb = "b110_0010".U 349675acc68SYinan Xu def orzexth = "b110_0011".U 350675acc68SYinan Xu def xorlsb = "b110_0100".U 351675acc68SYinan Xu def xorzexth = "b110_0101".U 352675acc68SYinan Xu def orcblsb = "b110_0110".U 353675acc68SYinan Xu def orcbzexth = "b110_0111".U 3544aa9ed34Sfdy def vsetvli1 = "b1000_0000".U 3554aa9ed34Sfdy def vsetvli2 = "b1000_0100".U 3564aa9ed34Sfdy def vsetvl1 = "b1000_0001".U 3574aa9ed34Sfdy def vsetvl2 = "b1000_0101".U 3584aa9ed34Sfdy def vsetivli1 = "b1000_0010".U 3594aa9ed34Sfdy def vsetivli2 = "b1000_0110".U 360675acc68SYinan Xu 361675acc68SYinan Xu def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 362675acc68SYinan Xu def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 363675acc68SYinan Xu def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 364675acc68SYinan Xu def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 365675acc68SYinan Xu def isBranch(func: UInt) = func(6, 4) === "b111".U 366675acc68SYinan Xu def getBranchType(func: UInt) = func(3, 2) 367675acc68SYinan Xu def isBranchInvert(func: UInt) = func(1) 3684aa9ed34Sfdy def isVset(func: UInt) = func(7, 3) === "b1000_0".U 3694aa9ed34Sfdy def isVsetvl(func: UInt) = isVset(func) && func(0) 3704aa9ed34Sfdy def isVsetvli(func: UInt) = isVset(func) && !func(1, 0).orR 3714aa9ed34Sfdy def vsetExchange(func: UInt) = Cat(func(7, 3), "b1".U, func(1, 0)) 372675acc68SYinan Xu 37357a10886SXuan Hu def apply() = UInt(FuOpTypeWidth.W) 3742225d46eSJiawei Lin } 3752225d46eSJiawei Lin 3762225d46eSJiawei Lin object MDUOpType { 3772225d46eSJiawei Lin // mul 3782225d46eSJiawei Lin // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 3792225d46eSJiawei Lin def mul = "b00000".U 3802225d46eSJiawei Lin def mulh = "b00001".U 3812225d46eSJiawei Lin def mulhsu = "b00010".U 3822225d46eSJiawei Lin def mulhu = "b00011".U 3832225d46eSJiawei Lin def mulw = "b00100".U 3842225d46eSJiawei Lin 38588825c5cSYinan Xu def mulw7 = "b01100".U 38688825c5cSYinan Xu 3872225d46eSJiawei Lin // div 3882225d46eSJiawei Lin // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 38988825c5cSYinan Xu def div = "b10000".U 39088825c5cSYinan Xu def divu = "b10010".U 39188825c5cSYinan Xu def rem = "b10001".U 39288825c5cSYinan Xu def remu = "b10011".U 3932225d46eSJiawei Lin 39488825c5cSYinan Xu def divw = "b10100".U 39588825c5cSYinan Xu def divuw = "b10110".U 39688825c5cSYinan Xu def remw = "b10101".U 39788825c5cSYinan Xu def remuw = "b10111".U 3982225d46eSJiawei Lin 39988825c5cSYinan Xu def isMul(op: UInt) = !op(4) 40088825c5cSYinan Xu def isDiv(op: UInt) = op(4) 4012225d46eSJiawei Lin 4022225d46eSJiawei Lin def isDivSign(op: UInt) = isDiv(op) && !op(1) 4032225d46eSJiawei Lin def isW(op: UInt) = op(2) 4042225d46eSJiawei Lin def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 4052225d46eSJiawei Lin def getMulOp(op: UInt) = op(1, 0) 4062225d46eSJiawei Lin } 4072225d46eSJiawei Lin 4082225d46eSJiawei Lin object LSUOpType { 409d200f594SWilliam Wang // load pipeline 4102225d46eSJiawei Lin 411d200f594SWilliam Wang // normal load 412d200f594SWilliam Wang // Note: bit(1, 0) are size, DO NOT CHANGE 413d200f594SWilliam Wang // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 414d200f594SWilliam Wang def lb = "b0000".U 415d200f594SWilliam Wang def lh = "b0001".U 416d200f594SWilliam Wang def lw = "b0010".U 417d200f594SWilliam Wang def ld = "b0011".U 418d200f594SWilliam Wang def lbu = "b0100".U 419d200f594SWilliam Wang def lhu = "b0101".U 420d200f594SWilliam Wang def lwu = "b0110".U 421ca18a0b4SWilliam Wang 422d200f594SWilliam Wang // Zicbop software prefetch 423d200f594SWilliam Wang // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 424d200f594SWilliam Wang def prefetch_i = "b1000".U // TODO 425d200f594SWilliam Wang def prefetch_r = "b1001".U 426d200f594SWilliam Wang def prefetch_w = "b1010".U 427ca18a0b4SWilliam Wang 428d200f594SWilliam Wang def isPrefetch(op: UInt): Bool = op(3) 429d200f594SWilliam Wang 430d200f594SWilliam Wang // store pipeline 431d200f594SWilliam Wang // normal store 432d200f594SWilliam Wang // bit encoding: | store 00 | size(2bit) | 433d200f594SWilliam Wang def sb = "b0000".U 434d200f594SWilliam Wang def sh = "b0001".U 435d200f594SWilliam Wang def sw = "b0010".U 436d200f594SWilliam Wang def sd = "b0011".U 437d200f594SWilliam Wang 438d200f594SWilliam Wang // l1 cache op 439d200f594SWilliam Wang // bit encoding: | cbo_zero 01 | size(2bit) 11 | 440d200f594SWilliam Wang def cbo_zero = "b0111".U 441d200f594SWilliam Wang 442d200f594SWilliam Wang // llc op 443d200f594SWilliam Wang // bit encoding: | prefetch 11 | suboptype(2bit) | 444d200f594SWilliam Wang def cbo_clean = "b1100".U 445d200f594SWilliam Wang def cbo_flush = "b1101".U 446d200f594SWilliam Wang def cbo_inval = "b1110".U 447d200f594SWilliam Wang 448d200f594SWilliam Wang def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 4492225d46eSJiawei Lin 4502225d46eSJiawei Lin // atomics 4512225d46eSJiawei Lin // bit(1, 0) are size 4522225d46eSJiawei Lin // since atomics use a different fu type 4532225d46eSJiawei Lin // so we can safely reuse other load/store's encodings 454d200f594SWilliam Wang // bit encoding: | optype(4bit) | size (2bit) | 4552225d46eSJiawei Lin def lr_w = "b000010".U 4562225d46eSJiawei Lin def sc_w = "b000110".U 4572225d46eSJiawei Lin def amoswap_w = "b001010".U 4582225d46eSJiawei Lin def amoadd_w = "b001110".U 4592225d46eSJiawei Lin def amoxor_w = "b010010".U 4602225d46eSJiawei Lin def amoand_w = "b010110".U 4612225d46eSJiawei Lin def amoor_w = "b011010".U 4622225d46eSJiawei Lin def amomin_w = "b011110".U 4632225d46eSJiawei Lin def amomax_w = "b100010".U 4642225d46eSJiawei Lin def amominu_w = "b100110".U 4652225d46eSJiawei Lin def amomaxu_w = "b101010".U 4662225d46eSJiawei Lin 4672225d46eSJiawei Lin def lr_d = "b000011".U 4682225d46eSJiawei Lin def sc_d = "b000111".U 4692225d46eSJiawei Lin def amoswap_d = "b001011".U 4702225d46eSJiawei Lin def amoadd_d = "b001111".U 4712225d46eSJiawei Lin def amoxor_d = "b010011".U 4722225d46eSJiawei Lin def amoand_d = "b010111".U 4732225d46eSJiawei Lin def amoor_d = "b011011".U 4742225d46eSJiawei Lin def amomin_d = "b011111".U 4752225d46eSJiawei Lin def amomax_d = "b100011".U 4762225d46eSJiawei Lin def amominu_d = "b100111".U 4772225d46eSJiawei Lin def amomaxu_d = "b101011".U 478b6982e83SLemover 479b6982e83SLemover def size(op: UInt) = op(1,0) 4802225d46eSJiawei Lin } 4812225d46eSJiawei Lin 4823feeca58Szfw object BKUOpType { 483ee8ff153Szfw 4843feeca58Szfw def clmul = "b000000".U 4853feeca58Szfw def clmulh = "b000001".U 4863feeca58Szfw def clmulr = "b000010".U 4873feeca58Szfw def xpermn = "b000100".U 4883feeca58Szfw def xpermb = "b000101".U 489ee8ff153Szfw 4903feeca58Szfw def clz = "b001000".U 4913feeca58Szfw def clzw = "b001001".U 4923feeca58Szfw def ctz = "b001010".U 4933feeca58Szfw def ctzw = "b001011".U 4943feeca58Szfw def cpop = "b001100".U 4953feeca58Szfw def cpopw = "b001101".U 49607596dc6Szfw 4973feeca58Szfw // 01xxxx is reserve 4983feeca58Szfw def aes64es = "b100000".U 4993feeca58Szfw def aes64esm = "b100001".U 5003feeca58Szfw def aes64ds = "b100010".U 5013feeca58Szfw def aes64dsm = "b100011".U 5023feeca58Szfw def aes64im = "b100100".U 5033feeca58Szfw def aes64ks1i = "b100101".U 5043feeca58Szfw def aes64ks2 = "b100110".U 5053feeca58Szfw 5063feeca58Szfw // merge to two instruction sm4ks & sm4ed 50719bcce38SFawang Zhang def sm4ed0 = "b101000".U 50819bcce38SFawang Zhang def sm4ed1 = "b101001".U 50919bcce38SFawang Zhang def sm4ed2 = "b101010".U 51019bcce38SFawang Zhang def sm4ed3 = "b101011".U 51119bcce38SFawang Zhang def sm4ks0 = "b101100".U 51219bcce38SFawang Zhang def sm4ks1 = "b101101".U 51319bcce38SFawang Zhang def sm4ks2 = "b101110".U 51419bcce38SFawang Zhang def sm4ks3 = "b101111".U 5153feeca58Szfw 5163feeca58Szfw def sha256sum0 = "b110000".U 5173feeca58Szfw def sha256sum1 = "b110001".U 5183feeca58Szfw def sha256sig0 = "b110010".U 5193feeca58Szfw def sha256sig1 = "b110011".U 5203feeca58Szfw def sha512sum0 = "b110100".U 5213feeca58Szfw def sha512sum1 = "b110101".U 5223feeca58Szfw def sha512sig0 = "b110110".U 5233feeca58Szfw def sha512sig1 = "b110111".U 5243feeca58Szfw 5253feeca58Szfw def sm3p0 = "b111000".U 5263feeca58Szfw def sm3p1 = "b111001".U 527ee8ff153Szfw } 528ee8ff153Szfw 5292225d46eSJiawei Lin object BTBtype { 5302225d46eSJiawei Lin def B = "b00".U // branch 5312225d46eSJiawei Lin def J = "b01".U // jump 5322225d46eSJiawei Lin def I = "b10".U // indirect 5332225d46eSJiawei Lin def R = "b11".U // return 5342225d46eSJiawei Lin 5352225d46eSJiawei Lin def apply() = UInt(2.W) 5362225d46eSJiawei Lin } 5372225d46eSJiawei Lin 5382225d46eSJiawei Lin object SelImm { 539ee8ff153Szfw def IMM_X = "b0111".U 54066ce8f52Sczw def IMM_S = "b1110".U 541ee8ff153Szfw def IMM_SB = "b0001".U 542ee8ff153Szfw def IMM_U = "b0010".U 543ee8ff153Szfw def IMM_UJ = "b0011".U 544ee8ff153Szfw def IMM_I = "b0100".U 545ee8ff153Szfw def IMM_Z = "b0101".U 546ee8ff153Szfw def INVALID_INSTR = "b0110".U 547ee8ff153Szfw def IMM_B6 = "b1000".U 5482225d46eSJiawei Lin 54958c35d23Shuxuan0307 def IMM_OPIVIS = "b1001".U 55058c35d23Shuxuan0307 def IMM_OPIVIU = "b1010".U 551912e2179SXuan Hu def IMM_VSETVLI = "b1100".U 552912e2179SXuan Hu def IMM_VSETIVLI = "b1101".U 55358c35d23Shuxuan0307 55457a10886SXuan Hu def X = BitPat("b0000") 5556e7c9679Shuxuan0307 556ee8ff153Szfw def apply() = UInt(4.W) 5572225d46eSJiawei Lin } 5582225d46eSJiawei Lin 5596ab6918fSYinan Xu object ExceptionNO { 5606ab6918fSYinan Xu def instrAddrMisaligned = 0 5616ab6918fSYinan Xu def instrAccessFault = 1 5626ab6918fSYinan Xu def illegalInstr = 2 5636ab6918fSYinan Xu def breakPoint = 3 5646ab6918fSYinan Xu def loadAddrMisaligned = 4 5656ab6918fSYinan Xu def loadAccessFault = 5 5666ab6918fSYinan Xu def storeAddrMisaligned = 6 5676ab6918fSYinan Xu def storeAccessFault = 7 5686ab6918fSYinan Xu def ecallU = 8 5696ab6918fSYinan Xu def ecallS = 9 5706ab6918fSYinan Xu def ecallM = 11 5716ab6918fSYinan Xu def instrPageFault = 12 5726ab6918fSYinan Xu def loadPageFault = 13 5736ab6918fSYinan Xu // def singleStep = 14 5746ab6918fSYinan Xu def storePageFault = 15 5756ab6918fSYinan Xu def priorities = Seq( 5766ab6918fSYinan Xu breakPoint, // TODO: different BP has different priority 5776ab6918fSYinan Xu instrPageFault, 5786ab6918fSYinan Xu instrAccessFault, 5796ab6918fSYinan Xu illegalInstr, 5806ab6918fSYinan Xu instrAddrMisaligned, 5816ab6918fSYinan Xu ecallM, ecallS, ecallU, 582d880177dSYinan Xu storeAddrMisaligned, 583d880177dSYinan Xu loadAddrMisaligned, 5846ab6918fSYinan Xu storePageFault, 5856ab6918fSYinan Xu loadPageFault, 5866ab6918fSYinan Xu storeAccessFault, 587d880177dSYinan Xu loadAccessFault 5886ab6918fSYinan Xu ) 5896ab6918fSYinan Xu def all = priorities.distinct.sorted 5906ab6918fSYinan Xu def frontendSet = Seq( 5916ab6918fSYinan Xu instrAddrMisaligned, 5926ab6918fSYinan Xu instrAccessFault, 5936ab6918fSYinan Xu illegalInstr, 5946ab6918fSYinan Xu instrPageFault 5956ab6918fSYinan Xu ) 5966ab6918fSYinan Xu def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 5976ab6918fSYinan Xu val new_vec = Wire(ExceptionVec()) 5986ab6918fSYinan Xu new_vec.foreach(_ := false.B) 5996ab6918fSYinan Xu select.foreach(i => new_vec(i) := vec(i)) 6006ab6918fSYinan Xu new_vec 6016ab6918fSYinan Xu } 6026ab6918fSYinan Xu def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 6036ab6918fSYinan Xu def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 6046ab6918fSYinan Xu def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 6056ab6918fSYinan Xu partialSelect(vec, fuConfig.exceptionOut) 6066ab6918fSYinan Xu def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 6076ab6918fSYinan Xu partialSelect(vec, exuConfig.exceptionOut) 6086ab6918fSYinan Xu def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 6096ab6918fSYinan Xu partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 6106ab6918fSYinan Xu } 6116ab6918fSYinan Xu 6121c62c387SYinan Xu def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 613c3d7991bSJiawei Lin def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 6142225d46eSJiawei Lin def aluGen(p: Parameters) = new Alu()(p) 6153feeca58Szfw def bkuGen(p: Parameters) = new Bku()(p) 6162225d46eSJiawei Lin def jmpGen(p: Parameters) = new Jump()(p) 6172225d46eSJiawei Lin def fenceGen(p: Parameters) = new Fence()(p) 6182225d46eSJiawei Lin def csrGen(p: Parameters) = new CSR()(p) 6192225d46eSJiawei Lin def i2fGen(p: Parameters) = new IntToFP()(p) 6202225d46eSJiawei Lin def fmacGen(p: Parameters) = new FMA()(p) 6212225d46eSJiawei Lin def f2iGen(p: Parameters) = new FPToInt()(p) 6222225d46eSJiawei Lin def f2fGen(p: Parameters) = new FPToFP()(p) 6232225d46eSJiawei Lin def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 62485b4cd54SYinan Xu def stdGen(p: Parameters) = new Std()(p) 6256ab6918fSYinan Xu def mouDataGen(p: Parameters) = new Std()(p) 6266827759bSZhangZifei def vipuGen(p: Parameters) = new VIPU()(p) 627*99e169c5Sczw def vppuGen(p: Parameters) = new VPPU()(p) 6282225d46eSJiawei Lin 6296cdd85d9SYinan Xu def f2iSel(uop: MicroOp): Bool = { 6306cdd85d9SYinan Xu uop.ctrl.rfWen 6312225d46eSJiawei Lin } 6322225d46eSJiawei Lin 6336cdd85d9SYinan Xu def i2fSel(uop: MicroOp): Bool = { 6346cdd85d9SYinan Xu uop.ctrl.fpu.fromInt 6352225d46eSJiawei Lin } 6362225d46eSJiawei Lin 6376cdd85d9SYinan Xu def f2fSel(uop: MicroOp): Bool = { 6386cdd85d9SYinan Xu val ctrl = uop.ctrl.fpu 6392225d46eSJiawei Lin ctrl.fpWen && !ctrl.div && !ctrl.sqrt 6402225d46eSJiawei Lin } 6412225d46eSJiawei Lin 6426cdd85d9SYinan Xu def fdivSqrtSel(uop: MicroOp): Bool = { 6436cdd85d9SYinan Xu val ctrl = uop.ctrl.fpu 6442225d46eSJiawei Lin ctrl.div || ctrl.sqrt 6452225d46eSJiawei Lin } 6462225d46eSJiawei Lin 6472225d46eSJiawei Lin val aluCfg = FuConfig( 6481a0f06eeSYinan Xu name = "alu", 6492225d46eSJiawei Lin fuGen = aluGen, 6506cdd85d9SYinan Xu fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 6512225d46eSJiawei Lin fuType = FuType.alu, 6522225d46eSJiawei Lin numIntSrc = 2, 6532225d46eSJiawei Lin numFpSrc = 0, 6542225d46eSJiawei Lin writeIntRf = true, 6552225d46eSJiawei Lin writeFpRf = false, 6562225d46eSJiawei Lin hasRedirect = true, 6572225d46eSJiawei Lin ) 6582225d46eSJiawei Lin 6592225d46eSJiawei Lin val jmpCfg = FuConfig( 6601a0f06eeSYinan Xu name = "jmp", 6612225d46eSJiawei Lin fuGen = jmpGen, 6626cdd85d9SYinan Xu fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 6632225d46eSJiawei Lin fuType = FuType.jmp, 6642225d46eSJiawei Lin numIntSrc = 1, 6652225d46eSJiawei Lin numFpSrc = 0, 6662225d46eSJiawei Lin writeIntRf = true, 6672225d46eSJiawei Lin writeFpRf = false, 6682225d46eSJiawei Lin hasRedirect = true, 6692225d46eSJiawei Lin ) 6702225d46eSJiawei Lin 6712225d46eSJiawei Lin val fenceCfg = FuConfig( 6721a0f06eeSYinan Xu name = "fence", 6732225d46eSJiawei Lin fuGen = fenceGen, 6746cdd85d9SYinan Xu fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 6756ab6918fSYinan Xu FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 676f1fe8698SLemover latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 677f1fe8698SLemover flushPipe = true 6782225d46eSJiawei Lin ) 6792225d46eSJiawei Lin 6802225d46eSJiawei Lin val csrCfg = FuConfig( 6811a0f06eeSYinan Xu name = "csr", 6822225d46eSJiawei Lin fuGen = csrGen, 6836cdd85d9SYinan Xu fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 6842225d46eSJiawei Lin fuType = FuType.csr, 6852225d46eSJiawei Lin numIntSrc = 1, 6862225d46eSJiawei Lin numFpSrc = 0, 6872225d46eSJiawei Lin writeIntRf = true, 6882225d46eSJiawei Lin writeFpRf = false, 6896ab6918fSYinan Xu exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 6906ab6918fSYinan Xu flushPipe = true 6912225d46eSJiawei Lin ) 6922225d46eSJiawei Lin 6932225d46eSJiawei Lin val i2fCfg = FuConfig( 6941a0f06eeSYinan Xu name = "i2f", 6952225d46eSJiawei Lin fuGen = i2fGen, 6962225d46eSJiawei Lin fuSel = i2fSel, 6972225d46eSJiawei Lin FuType.i2f, 6982225d46eSJiawei Lin numIntSrc = 1, 6992225d46eSJiawei Lin numFpSrc = 0, 7002225d46eSJiawei Lin writeIntRf = false, 7012225d46eSJiawei Lin writeFpRf = true, 7026ab6918fSYinan Xu writeFflags = true, 703e174d629SJiawei Lin latency = CertainLatency(2), 704e174d629SJiawei Lin fastUopOut = true, fastImplemented = true 7052225d46eSJiawei Lin ) 7062225d46eSJiawei Lin 7072225d46eSJiawei Lin val divCfg = FuConfig( 7081a0f06eeSYinan Xu name = "div", 7092225d46eSJiawei Lin fuGen = dividerGen, 71007596dc6Szfw fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 7112225d46eSJiawei Lin FuType.div, 7122225d46eSJiawei Lin 2, 7132225d46eSJiawei Lin 0, 7142225d46eSJiawei Lin writeIntRf = true, 7152225d46eSJiawei Lin writeFpRf = false, 716f83b578aSYinan Xu latency = UncertainLatency(), 717f83b578aSYinan Xu fastUopOut = true, 7181c62c387SYinan Xu fastImplemented = true, 7195ee7cabeSYinan Xu hasInputBuffer = (true, 4, true) 7202225d46eSJiawei Lin ) 7212225d46eSJiawei Lin 7222225d46eSJiawei Lin val mulCfg = FuConfig( 7231a0f06eeSYinan Xu name = "mul", 7242225d46eSJiawei Lin fuGen = multiplierGen, 72507596dc6Szfw fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 7262225d46eSJiawei Lin FuType.mul, 7272225d46eSJiawei Lin 2, 7282225d46eSJiawei Lin 0, 7292225d46eSJiawei Lin writeIntRf = true, 7302225d46eSJiawei Lin writeFpRf = false, 731b2482bc1SYinan Xu latency = CertainLatency(2), 732f83b578aSYinan Xu fastUopOut = true, 733b2482bc1SYinan Xu fastImplemented = true 7342225d46eSJiawei Lin ) 7352225d46eSJiawei Lin 7363feeca58Szfw val bkuCfg = FuConfig( 7373feeca58Szfw name = "bku", 7383feeca58Szfw fuGen = bkuGen, 7393feeca58Szfw fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 7403feeca58Szfw fuType = FuType.bku, 741ee8ff153Szfw numIntSrc = 2, 742ee8ff153Szfw numFpSrc = 0, 743ee8ff153Szfw writeIntRf = true, 744ee8ff153Szfw writeFpRf = false, 745f83b578aSYinan Xu latency = CertainLatency(1), 746f83b578aSYinan Xu fastUopOut = true, 74707596dc6Szfw fastImplemented = true 748ee8ff153Szfw ) 749ee8ff153Szfw 7502225d46eSJiawei Lin val fmacCfg = FuConfig( 7511a0f06eeSYinan Xu name = "fmac", 7522225d46eSJiawei Lin fuGen = fmacGen, 7530f038924SZhangZifei fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fmac, 7546ab6918fSYinan Xu FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 7554b65fc7eSJiawei Lin latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 7562225d46eSJiawei Lin ) 7572225d46eSJiawei Lin 7582225d46eSJiawei Lin val f2iCfg = FuConfig( 7591a0f06eeSYinan Xu name = "f2i", 7602225d46eSJiawei Lin fuGen = f2iGen, 7612225d46eSJiawei Lin fuSel = f2iSel, 7626ab6918fSYinan Xu FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 763b2482bc1SYinan Xu fastUopOut = true, fastImplemented = true 7642225d46eSJiawei Lin ) 7652225d46eSJiawei Lin 7662225d46eSJiawei Lin val f2fCfg = FuConfig( 7671a0f06eeSYinan Xu name = "f2f", 7682225d46eSJiawei Lin fuGen = f2fGen, 7692225d46eSJiawei Lin fuSel = f2fSel, 7706ab6918fSYinan Xu FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 771b2482bc1SYinan Xu fastUopOut = true, fastImplemented = true 7722225d46eSJiawei Lin ) 7732225d46eSJiawei Lin 7742225d46eSJiawei Lin val fdivSqrtCfg = FuConfig( 7751a0f06eeSYinan Xu name = "fdivSqrt", 7762225d46eSJiawei Lin fuGen = fdivSqrtGen, 7772225d46eSJiawei Lin fuSel = fdivSqrtSel, 7786ab6918fSYinan Xu FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 779140aff85SYinan Xu fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 7802225d46eSJiawei Lin ) 7812225d46eSJiawei Lin 7822225d46eSJiawei Lin val lduCfg = FuConfig( 7831a0f06eeSYinan Xu "ldu", 7842225d46eSJiawei Lin null, // DontCare 7852b4e8253SYinan Xu (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 7866ab6918fSYinan Xu FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 7876ab6918fSYinan Xu latency = UncertainLatency(), 7886ab6918fSYinan Xu exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 7896ab6918fSYinan Xu flushPipe = true, 7906786cfb7SWilliam Wang replayInst = true, 7916786cfb7SWilliam Wang hasLoadError = true 7922225d46eSJiawei Lin ) 7932225d46eSJiawei Lin 79485b4cd54SYinan Xu val staCfg = FuConfig( 7951a0f06eeSYinan Xu "sta", 7962225d46eSJiawei Lin null, 7972b4e8253SYinan Xu (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 7986ab6918fSYinan Xu FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 7996ab6918fSYinan Xu latency = UncertainLatency(), 8006ab6918fSYinan Xu exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 8012225d46eSJiawei Lin ) 8022225d46eSJiawei Lin 80385b4cd54SYinan Xu val stdCfg = FuConfig( 8041a0f06eeSYinan Xu "std", 8052b4e8253SYinan Xu fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 8066ab6918fSYinan Xu writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 80785b4cd54SYinan Xu ) 80885b4cd54SYinan Xu 8092225d46eSJiawei Lin val mouCfg = FuConfig( 8101a0f06eeSYinan Xu "mou", 8112225d46eSJiawei Lin null, 8122b4e8253SYinan Xu (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 8136ab6918fSYinan Xu FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 8146ab6918fSYinan Xu latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 8152b4e8253SYinan Xu ) 8162b4e8253SYinan Xu 8172b4e8253SYinan Xu val mouDataCfg = FuConfig( 8182b4e8253SYinan Xu "mou", 8192b4e8253SYinan Xu mouDataGen, 8202b4e8253SYinan Xu (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 8216ab6918fSYinan Xu FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 8226ab6918fSYinan Xu latency = UncertainLatency() 8232225d46eSJiawei Lin ) 8242225d46eSJiawei Lin 8256827759bSZhangZifei val vipuCfg = FuConfig( 8266827759bSZhangZifei name = "vipu", 8276827759bSZhangZifei fuGen = vipuGen, 8286827759bSZhangZifei fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType, 8296827759bSZhangZifei fuType = FuType.vipu, 8306827759bSZhangZifei numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, 8316827759bSZhangZifei numVecSrc = 2, writeVecRf = true, 8320f038924SZhangZifei fastUopOut = false, // TODO: check 8336827759bSZhangZifei fastImplemented = true, //TODO: check 8346827759bSZhangZifei ) 8356827759bSZhangZifei 836*99e169c5Sczw val vppuCfg = FuConfig( 837*99e169c5Sczw name = "vppu", 838*99e169c5Sczw fuGen = vppuGen, 839*99e169c5Sczw fuSel = (uop: MicroOp) => FuType.vppu === uop.ctrl.fuType, 840*99e169c5Sczw fuType = FuType.vppu, 841*99e169c5Sczw numIntSrc = 0, numFpSrc = 1, writeIntRf = false, writeFpRf = false, writeFflags = false, 842*99e169c5Sczw numVecSrc = 1, writeVecRf = true, 843*99e169c5Sczw fastUopOut = false, // TODO: check 844*99e169c5Sczw fastImplemented = true, //TODO: check 845*99e169c5Sczw ) 846*99e169c5Sczw 847adb5df20SYinan Xu val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 848b6220f0dSLemover val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 849adb5df20SYinan Xu val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 8503feeca58Szfw val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 851*99e169c5Sczw val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg, vppuCfg), Int.MaxValue, 0) 8522225d46eSJiawei Lin val FmiscExeUnitCfg = ExuConfig( 8532225d46eSJiawei Lin "FmiscExeUnit", 854b6220f0dSLemover "Fp", 8552225d46eSJiawei Lin Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 8562225d46eSJiawei Lin Int.MaxValue, 1 8572225d46eSJiawei Lin ) 8582b4e8253SYinan Xu val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 8592b4e8253SYinan Xu val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 8602b4e8253SYinan Xu val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 86154034ccdSZhangZifei 862d16f4ea4SZhangZifei // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 863d16f4ea4SZhangZifei // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 864d16f4ea4SZhangZifei // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 865d16f4ea4SZhangZifei // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 866d16f4ea4SZhangZifei // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 867d16f4ea4SZhangZifei // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 868d16f4ea4SZhangZifei // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 86954034ccdSZhangZifei 870d16f4ea4SZhangZifei val aluRSMod = new RSMod( 871d16f4ea4SZhangZifei rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 872d16f4ea4SZhangZifei rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 873d16f4ea4SZhangZifei immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 874d16f4ea4SZhangZifei ) 875d16f4ea4SZhangZifei val fmaRSMod = new RSMod( 876d16f4ea4SZhangZifei rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 877d16f4ea4SZhangZifei rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 878d16f4ea4SZhangZifei ) 879d16f4ea4SZhangZifei val fmiscRSMod = new RSMod( 880d16f4ea4SZhangZifei rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 881d16f4ea4SZhangZifei rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 882d16f4ea4SZhangZifei ) 883d16f4ea4SZhangZifei val jumpRSMod = new RSMod( 884d16f4ea4SZhangZifei rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 885d16f4ea4SZhangZifei rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 886d16f4ea4SZhangZifei immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 887d16f4ea4SZhangZifei ) 888d16f4ea4SZhangZifei val loadRSMod = new RSMod( 889d16f4ea4SZhangZifei rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 890d16f4ea4SZhangZifei rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 891d16f4ea4SZhangZifei immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 892d16f4ea4SZhangZifei ) 893d16f4ea4SZhangZifei val mulRSMod = new RSMod( 894d16f4ea4SZhangZifei rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 895d16f4ea4SZhangZifei rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 896d16f4ea4SZhangZifei immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 897d16f4ea4SZhangZifei ) 898d16f4ea4SZhangZifei val staRSMod = new RSMod( 899d16f4ea4SZhangZifei rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 900d16f4ea4SZhangZifei rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 901d16f4ea4SZhangZifei ) 902d16f4ea4SZhangZifei val stdRSMod = new RSMod( 903d16f4ea4SZhangZifei rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 904d16f4ea4SZhangZifei rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 905d16f4ea4SZhangZifei ) 9069a2e6b8aSLinJiawei} 907