1c6d43980SLemover/*************************************************************************************** 2c6d43980SLemover* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3f320e0f0SYinan Xu* Copyright (c) 2020-2021 Peng Cheng Laboratory 4c6d43980SLemover* 5c6d43980SLemover* XiangShan is licensed under Mulan PSL v2. 6c6d43980SLemover* You can use this software according to the terms and conditions of the Mulan PSL v2. 7c6d43980SLemover* You may obtain a copy of Mulan PSL v2 at: 8c6d43980SLemover* http://license.coscl.org.cn/MulanPSL2 9c6d43980SLemover* 10c6d43980SLemover* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11c6d43980SLemover* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12c6d43980SLemover* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13c6d43980SLemover* 14c6d43980SLemover* See the Mulan PSL v2 for more details. 15c6d43980SLemover***************************************************************************************/ 16c6d43980SLemover 179a2e6b8aSLinJiaweiimport chisel3._ 189a2e6b8aSLinJiaweiimport chisel3.util._ 198891a219SYinan Xuimport org.chipsalliance.cde.config.Parameters 202225d46eSJiawei Linimport freechips.rocketchip.tile.XLen 216ab6918fSYinan Xuimport xiangshan.ExceptionNO._ 222225d46eSJiawei Linimport xiangshan.backend.fu._ 232225d46eSJiawei Linimport xiangshan.backend.fu.fpu._ 246827759bSZhangZifeiimport xiangshan.backend.fu.vector._ 258f3b164bSXuan Huimport xiangshan.backend.issue._ 26730cfbc0SXuan Huimport xiangshan.backend.fu.FuConfig 27520f7dacSsinsanctionimport xiangshan.backend.decode.{Imm, ImmUnion} 282225d46eSJiawei Lin 299a2e6b8aSLinJiaweipackage object xiangshan { 309ee9f926SYikeZhou object SrcType { 31e4e68f86Sxiaofeibao def imm = "b0000".U 32e4e68f86Sxiaofeibao def pc = "b0000".U 33e4e68f86Sxiaofeibao def xp = "b0001".U 34e4e68f86Sxiaofeibao def fp = "b0010".U 35e4e68f86Sxiaofeibao def vp = "b0100".U 36e4e68f86Sxiaofeibao def v0 = "b1000".U 37e4e68f86Sxiaofeibao def no = "b0000".U // this src read no reg but cannot be Any value 3804b56283SZhangZifei 391285b047SXuan Hu // alias 401285b047SXuan Hu def reg = this.xp 411a3df1feSYikeZhou def DC = imm // Don't Care 42e4e68f86Sxiaofeibao def X = BitPat("b0000") 434d24c305SYikeZhou 4404b56283SZhangZifei def isPc(srcType: UInt) = srcType===pc 4504b56283SZhangZifei def isImm(srcType: UInt) = srcType===imm 461285b047SXuan Hu def isReg(srcType: UInt) = srcType(0) 479ca09953SXuan Hu def isXp(srcType: UInt) = srcType(0) 482b4e8253SYinan Xu def isFp(srcType: UInt) = srcType(1) 491285b047SXuan Hu def isVp(srcType: UInt) = srcType(2) 50e4e68f86Sxiaofeibao def isV0(srcType: UInt) = srcType(3) 511285b047SXuan Hu def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 529ca09953SXuan Hu def isNotReg(srcType: UInt): Bool = !srcType.orR 53351e22f2SXuan Hu def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 54e4e68f86Sxiaofeibao def apply() = UInt(4.W) 559a2e6b8aSLinJiawei } 569a2e6b8aSLinJiawei 579a2e6b8aSLinJiawei object SrcState { 58100aa93cSYinan Xu def busy = "b0".U 59100aa93cSYinan Xu def rdy = "b1".U 60100aa93cSYinan Xu // def specRdy = "b10".U // speculative ready, for future use 61100aa93cSYinan Xu def apply() = UInt(1.W) 629ca09953SXuan Hu 639ca09953SXuan Hu def isReady(state: UInt): Bool = state === this.rdy 649ca09953SXuan Hu def isBusy(state: UInt): Bool = state === this.busy 659a2e6b8aSLinJiawei } 669a2e6b8aSLinJiawei 679019e3efSXuan Hu def FuOpTypeWidth = 9 682225d46eSJiawei Lin object FuOpType { 6957a10886SXuan Hu def apply() = UInt(FuOpTypeWidth.W) 7034f9ccd0SZiyue Zhang def X = BitPat("b0_0000_0000") 7134f9ccd0SZiyue Zhang def FMVXF = BitPat("b1_1000_0000") //for fmv_x_d & fmv_x_w 72ebd97ecbSzhanglinjuan } 73518d8658SYinan Xu 747f2b7720SXuan Hu object VlduType { 756dbb4e08SXuan Hu // bit encoding: | vector or scala (2bit) || mop (2bit) | lumop(5bit) | 76c379dcbeSZiyue-Zhang // only unit-stride use lumop 77c379dcbeSZiyue-Zhang // mop [1:0] 78c379dcbeSZiyue-Zhang // 0 0 : unit-stride 79c379dcbeSZiyue-Zhang // 0 1 : indexed-unordered 80c379dcbeSZiyue-Zhang // 1 0 : strided 81c379dcbeSZiyue-Zhang // 1 1 : indexed-ordered 82c379dcbeSZiyue-Zhang // lumop[4:0] 83c379dcbeSZiyue-Zhang // 0 0 0 0 0 : unit-stride load 84c379dcbeSZiyue-Zhang // 0 1 0 0 0 : unit-stride, whole register load 85c379dcbeSZiyue-Zhang // 0 1 0 1 1 : unit-stride, mask load, EEW=8 86c379dcbeSZiyue-Zhang // 1 0 0 0 0 : unit-stride fault-only-first 876dbb4e08SXuan Hu def vle = "b01_00_00000".U 886dbb4e08SXuan Hu def vlr = "b01_00_01000".U // whole 896dbb4e08SXuan Hu def vlm = "b01_00_01011".U // mask 906dbb4e08SXuan Hu def vleff = "b01_00_10000".U 916dbb4e08SXuan Hu def vluxe = "b01_01_00000".U // index 926dbb4e08SXuan Hu def vlse = "b01_10_00000".U // strided 936dbb4e08SXuan Hu def vloxe = "b01_11_00000".U // index 9492c6b7edSzhanglinjuan 950b55f3fbSlwd def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U && (fuOpType(8) ^ fuOpType(7)) 960b55f3fbSlwd def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U && (fuOpType(8) ^ fuOpType(7)) 970b55f3fbSlwd def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U && (fuOpType(8) ^ fuOpType(7)) 980b55f3fbSlwd def isIndexed(fuOpType: UInt): Bool = fuOpType(5) && (fuOpType(8) ^ fuOpType(7)) 996dbb4e08SXuan Hu def isVecLd (fuOpType: UInt): Bool = fuOpType(8, 7) === "b01".U 1007f2b7720SXuan Hu } 1017f2b7720SXuan Hu 1027f2b7720SXuan Hu object VstuType { 103c379dcbeSZiyue-Zhang // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 104c379dcbeSZiyue-Zhang // only unit-stride use sumop 105c379dcbeSZiyue-Zhang // mop [1:0] 106c379dcbeSZiyue-Zhang // 0 0 : unit-stride 107c379dcbeSZiyue-Zhang // 0 1 : indexed-unordered 108c379dcbeSZiyue-Zhang // 1 0 : strided 109c379dcbeSZiyue-Zhang // 1 1 : indexed-ordered 110c379dcbeSZiyue-Zhang // sumop[4:0] 111c379dcbeSZiyue-Zhang // 0 0 0 0 0 : unit-stride load 112c379dcbeSZiyue-Zhang // 0 1 0 0 0 : unit-stride, whole register load 113c379dcbeSZiyue-Zhang // 0 1 0 1 1 : unit-stride, mask load, EEW=8 1146dbb4e08SXuan Hu def vse = "b10_00_00000".U 1156dbb4e08SXuan Hu def vsr = "b10_00_01000".U // whole 1166dbb4e08SXuan Hu def vsm = "b10_00_01011".U // mask 1176dbb4e08SXuan Hu def vsuxe = "b10_01_00000".U // index 1186dbb4e08SXuan Hu def vsse = "b10_10_00000".U // strided 1196dbb4e08SXuan Hu def vsoxe = "b10_11_00000".U // index 12092c6b7edSzhanglinjuan 1210b55f3fbSlwd def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U && (fuOpType(8) ^ fuOpType(7)) 1220b55f3fbSlwd def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U && (fuOpType(8) ^ fuOpType(7)) 1230b55f3fbSlwd def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U && (fuOpType(8) ^ fuOpType(7)) 1240b55f3fbSlwd def isIndexed(fuOpType: UInt): Bool = fuOpType(5) && (fuOpType(8) ^ fuOpType(7)) 1256dbb4e08SXuan Hu def isVecSt (fuOpType: UInt): Bool = fuOpType(8, 7) === "b10".U 1267f2b7720SXuan Hu } 1277f2b7720SXuan Hu 128d6059658SZiyue Zhang object IF2VectorType { 129b1712600SZiyue Zhang // use last 2 bits for vsew 130b1712600SZiyue Zhang def iDup2Vec = "b1_00".U 1315820cff8Slewislzh def fDup2Vec = "b1_01".U 132b1712600SZiyue Zhang def immDup2Vec = "b1_10".U 133b1712600SZiyue Zhang def i2Vec = "b0_00".U 134395c8649SZiyue-Zhang def f2Vec = "b0_01".U 135b1712600SZiyue Zhang def imm2Vec = "b0_10".U 136b1712600SZiyue Zhang def needDup(bits: UInt): Bool = bits(2) 137b1712600SZiyue Zhang def isImm(bits: UInt): Bool = bits(1) 1385820cff8Slewislzh def isFp(bits: UInt): Bool = bits(0) 1395820cff8Slewislzh def isFmv(bits: UInt): Bool = bits(0) & !bits(2) 140964d9a87SZiyue Zhang def FMX_D_X = "b0_01_11".U 141964d9a87SZiyue Zhang def FMX_W_X = "b0_01_10".U 142d6059658SZiyue Zhang } 143d6059658SZiyue Zhang 144a3edac52SYinan Xu object CommitType { 145c3abb8b6SYinan Xu def NORMAL = "b000".U // int/fp 146c3abb8b6SYinan Xu def BRANCH = "b001".U // branch 147c3abb8b6SYinan Xu def LOAD = "b010".U // load 148c3abb8b6SYinan Xu def STORE = "b011".U // store 149518d8658SYinan Xu 150c3abb8b6SYinan Xu def apply() = UInt(3.W) 151c3abb8b6SYinan Xu def isFused(commitType: UInt): Bool = commitType(2) 152c3abb8b6SYinan Xu def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 153c3abb8b6SYinan Xu def lsInstIsStore(commitType: UInt): Bool = commitType(0) 154c3abb8b6SYinan Xu def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 155c3abb8b6SYinan Xu def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 156518d8658SYinan Xu } 157bfb958a3SYinan Xu 158bfb958a3SYinan Xu object RedirectLevel { 1592d7c7105SYinan Xu def flushAfter = "b0".U 1602d7c7105SYinan Xu def flush = "b1".U 161bfb958a3SYinan Xu 1622d7c7105SYinan Xu def apply() = UInt(1.W) 1632d7c7105SYinan Xu // def isUnconditional(level: UInt) = level(1) 164bfb958a3SYinan Xu def flushItself(level: UInt) = level(0) 1652d7c7105SYinan Xu // def isException(level: UInt) = level(1) && level(0) 166bfb958a3SYinan Xu } 167baf8def6SYinan Xu 168baf8def6SYinan Xu object ExceptionVec { 169d0de7e4aSpeixiaokun val ExceptionVecSize = 24 170da3bf434SMaxpicca-Li def apply() = Vec(ExceptionVecSize, Bool()) 171baf8def6SYinan Xu } 172a8e04b1dSYinan Xu 173c60c1ab4SWilliam Wang object PMAMode { 1748d9a04fcSWilliam Wang def R = "b1".U << 0 //readable 1758d9a04fcSWilliam Wang def W = "b1".U << 1 //writeable 1768d9a04fcSWilliam Wang def X = "b1".U << 2 //executable 1778d9a04fcSWilliam Wang def I = "b1".U << 3 //cacheable: icache 1788d9a04fcSWilliam Wang def D = "b1".U << 4 //cacheable: dcache 1798d9a04fcSWilliam Wang def S = "b1".U << 5 //enable speculative access 180cff68e26SWilliam Wang def A = "b1".U << 6 //enable atomic operation, A imply R & W 1818d9a04fcSWilliam Wang def C = "b1".U << 7 //if it is cacheable is configable 182c60c1ab4SWilliam Wang def Reserved = "b0".U 183c60c1ab4SWilliam Wang 184c60c1ab4SWilliam Wang def apply() = UInt(7.W) 185c60c1ab4SWilliam Wang 186c60c1ab4SWilliam Wang def read(mode: UInt) = mode(0) 187c60c1ab4SWilliam Wang def write(mode: UInt) = mode(1) 188c60c1ab4SWilliam Wang def execute(mode: UInt) = mode(2) 189c60c1ab4SWilliam Wang def icache(mode: UInt) = mode(3) 190c60c1ab4SWilliam Wang def dcache(mode: UInt) = mode(4) 191c60c1ab4SWilliam Wang def speculate(mode: UInt) = mode(5) 192c60c1ab4SWilliam Wang def atomic(mode: UInt) = mode(6) 193c60c1ab4SWilliam Wang def configable_cache(mode: UInt) = mode(7) 194c60c1ab4SWilliam Wang 195c60c1ab4SWilliam Wang def strToMode(s: String) = { 196423b9255SWilliam Wang var result = 0.U(8.W) 197c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("R") >= 0) result = result + R 198c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("W") >= 0) result = result + W 199c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("X") >= 0) result = result + X 200c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("I") >= 0) result = result + I 201c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("D") >= 0) result = result + D 202c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("S") >= 0) result = result + S 203c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("A") >= 0) result = result + A 204c60c1ab4SWilliam Wang if (s.toUpperCase.indexOf("C") >= 0) result = result + C 205c60c1ab4SWilliam Wang result 206c60c1ab4SWilliam Wang } 207c60c1ab4SWilliam Wang } 2082225d46eSJiawei Lin 2092225d46eSJiawei Lin 2102225d46eSJiawei Lin object CSROpType { 2111be7b39aSXuan Hu def jmp = "b010_000".U 2121be7b39aSXuan Hu def wfi = "b100_000".U 2131be7b39aSXuan Hu def wrt = "b001_001".U 2141be7b39aSXuan Hu def set = "b001_010".U 2151be7b39aSXuan Hu def clr = "b001_011".U 2161be7b39aSXuan Hu def wrti = "b001_101".U 2171be7b39aSXuan Hu def seti = "b001_110".U 2181be7b39aSXuan Hu def clri = "b001_111".U 2191be7b39aSXuan Hu def ro = "b001_000".U 2201be7b39aSXuan Hu 2211be7b39aSXuan Hu def isSystemOp (op: UInt): Bool = op(4) 2221be7b39aSXuan Hu def isWfi (op: UInt): Bool = op(5) 2231be7b39aSXuan Hu def isCsrAccess(op: UInt): Bool = op(3) 2241be7b39aSXuan Hu def isReadOnly (op: UInt): Bool = op(3) && op(2, 0) === 0.U 2251be7b39aSXuan Hu def notReadOnly(op: UInt): Bool = op(3) && op(2, 0) =/= 0.U 226f7c21cb5SXuan Hu 227f7c21cb5SXuan Hu def getCSROp(op: UInt) = op(1, 0) 228f7c21cb5SXuan Hu def needImm(op: UInt) = op(2) 2292225d46eSJiawei Lin } 2302225d46eSJiawei Lin 2312225d46eSJiawei Lin // jump 2322225d46eSJiawei Lin object JumpOpType { 2332225d46eSJiawei Lin def jal = "b00".U 2342225d46eSJiawei Lin def jalr = "b01".U 2352225d46eSJiawei Lin def auipc = "b10".U 2362225d46eSJiawei Lin// def call = "b11_011".U 2372225d46eSJiawei Lin// def ret = "b11_100".U 2382225d46eSJiawei Lin def jumpOpisJalr(op: UInt) = op(0) 2392225d46eSJiawei Lin def jumpOpisAuipc(op: UInt) = op(1) 2402225d46eSJiawei Lin } 2412225d46eSJiawei Lin 2422225d46eSJiawei Lin object FenceOpType { 2432225d46eSJiawei Lin def fence = "b10000".U 2442225d46eSJiawei Lin def sfence = "b10001".U 2452225d46eSJiawei Lin def fencei = "b10010".U 246d0de7e4aSpeixiaokun def hfence_v = "b10011".U 247d0de7e4aSpeixiaokun def hfence_g = "b10100".U 248af2f7849Shappy-lx def nofence= "b00000".U 2492225d46eSJiawei Lin } 2502225d46eSJiawei Lin 2512225d46eSJiawei Lin object ALUOpType { 252ee8ff153Szfw // shift optype 253675acc68SYinan Xu def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 254675acc68SYinan Xu def sll = "b000_0001".U // sll: src1 << src2 255ee8ff153Szfw 256675acc68SYinan Xu def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 257675acc68SYinan Xu def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 258675acc68SYinan Xu def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 259ee8ff153Szfw 260675acc68SYinan Xu def srl = "b000_0101".U // srl: src1 >> src2 261675acc68SYinan Xu def bext = "b000_0110".U // bext: (src1 >> src2)[0] 262675acc68SYinan Xu def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 263ee8ff153Szfw 2647b441e5eSYinan Xu def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 2657b441e5eSYinan Xu def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 266184a1958Szfw 267ee8ff153Szfw // RV64 32bit optype 268675acc68SYinan Xu def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 269675acc68SYinan Xu def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 270675acc68SYinan Xu def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 27154711376Ssinsanction def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 272ee8ff153Szfw 273675acc68SYinan Xu def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 274675acc68SYinan Xu def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 275675acc68SYinan Xu def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 276675acc68SYinan Xu def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 277ee8ff153Szfw 278675acc68SYinan Xu def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 279675acc68SYinan Xu def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 280675acc68SYinan Xu def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 281675acc68SYinan Xu def rolw = "b001_1100".U 282675acc68SYinan Xu def rorw = "b001_1101".U 283675acc68SYinan Xu 284675acc68SYinan Xu // ADD-op 285675acc68SYinan Xu def adduw = "b010_0000".U // adduw: src1[31:0] + src2 286675acc68SYinan Xu def add = "b010_0001".U // add: src1 + src2 287675acc68SYinan Xu def oddadd = "b010_0010".U // oddadd: src1[0] + src2 288fe528fd6Ssinsanction def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 289675acc68SYinan Xu 290675acc68SYinan Xu def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 291675acc68SYinan Xu def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 292675acc68SYinan Xu def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 293675acc68SYinan Xu def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 294675acc68SYinan Xu 295675acc68SYinan Xu def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 296675acc68SYinan Xu def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 297675acc68SYinan Xu def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 298675acc68SYinan Xu def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 299675acc68SYinan Xu def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 300675acc68SYinan Xu def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 301675acc68SYinan Xu def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 302675acc68SYinan Xu 303675acc68SYinan Xu // SUB-op: src1 - src2 304675acc68SYinan Xu def sub = "b011_0000".U 305675acc68SYinan Xu def sltu = "b011_0001".U 306675acc68SYinan Xu def slt = "b011_0010".U 307675acc68SYinan Xu def maxu = "b011_0100".U 308675acc68SYinan Xu def minu = "b011_0101".U 309675acc68SYinan Xu def max = "b011_0110".U 310675acc68SYinan Xu def min = "b011_0111".U 311675acc68SYinan Xu 312545d7be0SYangyu Chen // Zicond 313545d7be0SYangyu Chen def czero_eqz = "b111_0100".U 314545d7be0SYangyu Chen def czero_nez = "b111_0110".U 315545d7be0SYangyu Chen 316675acc68SYinan Xu // misc optype 317675acc68SYinan Xu def and = "b100_0000".U 318675acc68SYinan Xu def andn = "b100_0001".U 319675acc68SYinan Xu def or = "b100_0010".U 320675acc68SYinan Xu def orn = "b100_0011".U 321675acc68SYinan Xu def xor = "b100_0100".U 322675acc68SYinan Xu def xnor = "b100_0101".U 323675acc68SYinan Xu def orcb = "b100_0110".U 324675acc68SYinan Xu 325675acc68SYinan Xu def sextb = "b100_1000".U 326675acc68SYinan Xu def packh = "b100_1001".U 327675acc68SYinan Xu def sexth = "b100_1010".U 328675acc68SYinan Xu def packw = "b100_1011".U 329675acc68SYinan Xu 330675acc68SYinan Xu def revb = "b101_0000".U 331675acc68SYinan Xu def rev8 = "b101_0001".U 332675acc68SYinan Xu def pack = "b101_0010".U 333675acc68SYinan Xu def orh48 = "b101_0011".U 334675acc68SYinan Xu 335675acc68SYinan Xu def szewl1 = "b101_1000".U 336675acc68SYinan Xu def szewl2 = "b101_1001".U 337675acc68SYinan Xu def szewl3 = "b101_1010".U 338675acc68SYinan Xu def byte2 = "b101_1011".U 339675acc68SYinan Xu 340675acc68SYinan Xu def andlsb = "b110_0000".U 341675acc68SYinan Xu def andzexth = "b110_0001".U 342675acc68SYinan Xu def orlsb = "b110_0010".U 343675acc68SYinan Xu def orzexth = "b110_0011".U 344675acc68SYinan Xu def xorlsb = "b110_0100".U 345675acc68SYinan Xu def xorzexth = "b110_0101".U 346675acc68SYinan Xu def orcblsb = "b110_0110".U 347675acc68SYinan Xu def orcbzexth = "b110_0111".U 348675acc68SYinan Xu 349675acc68SYinan Xu def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 350675acc68SYinan Xu def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 351675acc68SYinan Xu def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 352675acc68SYinan Xu def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 353675acc68SYinan Xu 35457a10886SXuan Hu def apply() = UInt(FuOpTypeWidth.W) 3552225d46eSJiawei Lin } 3562225d46eSJiawei Lin 357d91483a6Sfdy object VSETOpType { 358a8db15d8Sfdy val setVlmaxBit = 0 359a8db15d8Sfdy val keepVlBit = 1 360a8db15d8Sfdy // destTypeBit == 0: write vl to rd 361a8db15d8Sfdy // destTypeBit == 1: write vconfig 362a8db15d8Sfdy val destTypeBit = 5 363a8db15d8Sfdy 364a32c56f4SXuan Hu // vsetvli's uop 365a32c56f4SXuan Hu // rs1!=x0, normal 366a32c56f4SXuan Hu // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 367a32c56f4SXuan Hu // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 368a32c56f4SXuan Hu def uvsetvcfg_xi = "b1010_0000".U 369a32c56f4SXuan Hu def uvsetrd_xi = "b1000_0000".U 370a32c56f4SXuan Hu // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 371a32c56f4SXuan Hu // uop0: w(vconfig) | vlmax, vtypei -> vconfig 372a32c56f4SXuan Hu // uop1: w(rd) | vlmax, vtypei -> x[rd] 373a32c56f4SXuan Hu def uvsetvcfg_vlmax_i = "b1010_0001".U 374a32c56f4SXuan Hu def uvsetrd_vlmax_i = "b1000_0001".U 375a32c56f4SXuan Hu // rs1==x0, rd==x0, keep vl, set vtype 376a32c56f4SXuan Hu // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 377a32c56f4SXuan Hu def uvsetvcfg_keep_v = "b1010_0010".U 378d91483a6Sfdy 379a32c56f4SXuan Hu // vsetvl's uop 380a32c56f4SXuan Hu // rs1!=x0, normal 381a32c56f4SXuan Hu // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 382a32c56f4SXuan Hu // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 383a32c56f4SXuan Hu def uvsetvcfg_xx = "b0110_0000".U 384a32c56f4SXuan Hu def uvsetrd_xx = "b0100_0000".U 385a32c56f4SXuan Hu // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 386a32c56f4SXuan Hu // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 387a32c56f4SXuan Hu // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 388a32c56f4SXuan Hu def uvsetvcfg_vlmax_x = "b0110_0001".U 389a32c56f4SXuan Hu def uvsetrd_vlmax_x = "b0100_0001".U 390a32c56f4SXuan Hu // rs1==x0, rd==x0, keep vl, set vtype 391a32c56f4SXuan Hu // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 392a32c56f4SXuan Hu // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 393a32c56f4SXuan Hu def uvmv_v_x = "b0110_0010".U 394a32c56f4SXuan Hu def uvsetvcfg_vv = "b0111_0010".U 395a32c56f4SXuan Hu 396a32c56f4SXuan Hu // vsetivli's uop 397a32c56f4SXuan Hu // uop0: w(vconfig) | vli, vtypei -> vconfig 398a32c56f4SXuan Hu // uop1: w(rd) | vli, vtypei -> x[rd] 399a32c56f4SXuan Hu def uvsetvcfg_ii = "b0010_0000".U 400a32c56f4SXuan Hu def uvsetrd_ii = "b0000_0000".U 401a32c56f4SXuan Hu 402cc1eb70dSXuan Hu // read vec, write int 403cc1eb70dSXuan Hu // keep vl 404cc1eb70dSXuan Hu def csrrvl = "b0001_0110".U 405cc1eb70dSXuan Hu 406a32c56f4SXuan Hu def isVsetvl (func: UInt) = func(6) 407a32c56f4SXuan Hu def isVsetvli (func: UInt) = func(7) 408a32c56f4SXuan Hu def isVsetivli(func: UInt) = func(7, 6) === 0.U 409a32c56f4SXuan Hu def isNormal (func: UInt) = func(1, 0) === 0.U 410a8db15d8Sfdy def isSetVlmax(func: UInt) = func(setVlmaxBit) 411a8db15d8Sfdy def isKeepVl (func: UInt) = func(keepVlBit) 412a32c56f4SXuan Hu // RG: region 413a32c56f4SXuan Hu def writeIntRG(func: UInt) = !func(5) 414a32c56f4SXuan Hu def writeVecRG(func: UInt) = func(5) 415a32c56f4SXuan Hu def readIntRG (func: UInt) = !func(4) 416a32c56f4SXuan Hu def readVecRG (func: UInt) = func(4) 417a8db15d8Sfdy // modify fuOpType 418a8db15d8Sfdy def keepVl(func: UInt) = func | (1 << keepVlBit).U 419a8db15d8Sfdy def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 420d91483a6Sfdy } 421d91483a6Sfdy 4223b739f49SXuan Hu object BRUOpType { 4233b739f49SXuan Hu // branch 4243b739f49SXuan Hu def beq = "b000_000".U 4253b739f49SXuan Hu def bne = "b000_001".U 4263b739f49SXuan Hu def blt = "b000_100".U 4273b739f49SXuan Hu def bge = "b000_101".U 4283b739f49SXuan Hu def bltu = "b001_000".U 4293b739f49SXuan Hu def bgeu = "b001_001".U 4303b739f49SXuan Hu 4313b739f49SXuan Hu def getBranchType(func: UInt) = func(3, 1) 4323b739f49SXuan Hu def isBranchInvert(func: UInt) = func(0) 4333b739f49SXuan Hu } 4343b739f49SXuan Hu 4353b739f49SXuan Hu object MULOpType { 4363b739f49SXuan Hu // mul 4373b739f49SXuan Hu // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 4383b739f49SXuan Hu def mul = "b00000".U 4393b739f49SXuan Hu def mulh = "b00001".U 4403b739f49SXuan Hu def mulhsu = "b00010".U 4413b739f49SXuan Hu def mulhu = "b00011".U 4423b739f49SXuan Hu def mulw = "b00100".U 4433b739f49SXuan Hu 4443b739f49SXuan Hu def mulw7 = "b01100".U 4453b739f49SXuan Hu def isSign(op: UInt) = !op(1) 4463b739f49SXuan Hu def isW(op: UInt) = op(2) 4473b739f49SXuan Hu def isH(op: UInt) = op(1, 0) =/= 0.U 4483b739f49SXuan Hu def getOp(op: UInt) = Cat(op(3), op(1, 0)) 4493b739f49SXuan Hu } 4503b739f49SXuan Hu 4513b739f49SXuan Hu object DIVOpType { 4523b739f49SXuan Hu // div 4533b739f49SXuan Hu // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 4543b739f49SXuan Hu def div = "b10000".U 4553b739f49SXuan Hu def divu = "b10010".U 4563b739f49SXuan Hu def rem = "b10001".U 4573b739f49SXuan Hu def remu = "b10011".U 4583b739f49SXuan Hu 4593b739f49SXuan Hu def divw = "b10100".U 4603b739f49SXuan Hu def divuw = "b10110".U 4613b739f49SXuan Hu def remw = "b10101".U 4623b739f49SXuan Hu def remuw = "b10111".U 4633b739f49SXuan Hu 4643b739f49SXuan Hu def isSign(op: UInt) = !op(1) 4653b739f49SXuan Hu def isW(op: UInt) = op(2) 4663b739f49SXuan Hu def isH(op: UInt) = op(0) 4673b739f49SXuan Hu } 4683b739f49SXuan Hu 4692225d46eSJiawei Lin object MDUOpType { 4702225d46eSJiawei Lin // mul 4712225d46eSJiawei Lin // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 4722225d46eSJiawei Lin def mul = "b00000".U 4732225d46eSJiawei Lin def mulh = "b00001".U 4742225d46eSJiawei Lin def mulhsu = "b00010".U 4752225d46eSJiawei Lin def mulhu = "b00011".U 4762225d46eSJiawei Lin def mulw = "b00100".U 4772225d46eSJiawei Lin 47888825c5cSYinan Xu def mulw7 = "b01100".U 47988825c5cSYinan Xu 4802225d46eSJiawei Lin // div 4812225d46eSJiawei Lin // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 48288825c5cSYinan Xu def div = "b10000".U 48388825c5cSYinan Xu def divu = "b10010".U 48488825c5cSYinan Xu def rem = "b10001".U 48588825c5cSYinan Xu def remu = "b10011".U 4862225d46eSJiawei Lin 48788825c5cSYinan Xu def divw = "b10100".U 48888825c5cSYinan Xu def divuw = "b10110".U 48988825c5cSYinan Xu def remw = "b10101".U 49088825c5cSYinan Xu def remuw = "b10111".U 4912225d46eSJiawei Lin 49288825c5cSYinan Xu def isMul(op: UInt) = !op(4) 49388825c5cSYinan Xu def isDiv(op: UInt) = op(4) 4942225d46eSJiawei Lin 4952225d46eSJiawei Lin def isDivSign(op: UInt) = isDiv(op) && !op(1) 4962225d46eSJiawei Lin def isW(op: UInt) = op(2) 4972225d46eSJiawei Lin def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 4982225d46eSJiawei Lin def getMulOp(op: UInt) = op(1, 0) 4992225d46eSJiawei Lin } 5002225d46eSJiawei Lin 5012225d46eSJiawei Lin object LSUOpType { 502136f6497SXiaokun-Pei // The max length is 6 bits 503d200f594SWilliam Wang // load pipeline 5042225d46eSJiawei Lin 505d200f594SWilliam Wang // normal load 506d200f594SWilliam Wang // Note: bit(1, 0) are size, DO NOT CHANGE 507d200f594SWilliam Wang // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 508d200f594SWilliam Wang def lb = "b0000".U 509d200f594SWilliam Wang def lh = "b0001".U 510d200f594SWilliam Wang def lw = "b0010".U 511d200f594SWilliam Wang def ld = "b0011".U 512d200f594SWilliam Wang def lbu = "b0100".U 513d200f594SWilliam Wang def lhu = "b0101".U 514d200f594SWilliam Wang def lwu = "b0110".U 515d0de7e4aSpeixiaokun // hypervior load 51684c44d24Slwd // bit encoding: | hlv 1 | hlvx 1 | is unsigned(1bit) | size(2bit) | 517d0de7e4aSpeixiaokun def hlvb = "b10000".U 518d0de7e4aSpeixiaokun def hlvh = "b10001".U 519d0de7e4aSpeixiaokun def hlvw = "b10010".U 520d0de7e4aSpeixiaokun def hlvd = "b10011".U 521d0de7e4aSpeixiaokun def hlvbu = "b10100".U 522d0de7e4aSpeixiaokun def hlvhu = "b10101".U 523d0de7e4aSpeixiaokun def hlvwu = "b10110".U 524136f6497SXiaokun-Pei def hlvxhu = "b11101".U 525136f6497SXiaokun-Pei def hlvxwu = "b11110".U 5260b55f3fbSlwd def isHlv(op: UInt): Bool = op(4) && (op(5) === "b0".U) && (op(8, 7) === "b00".U) 5270b55f3fbSlwd def isHlvx(op: UInt): Bool = op(4) && op(3) && (op(5) === "b0".U) && (op(8, 7) === "b00".U) 528ca18a0b4SWilliam Wang 529d200f594SWilliam Wang // Zicbop software prefetch 530d200f594SWilliam Wang // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 531d200f594SWilliam Wang def prefetch_i = "b1000".U // TODO 532d200f594SWilliam Wang def prefetch_r = "b1001".U 533d200f594SWilliam Wang def prefetch_w = "b1010".U 534ca18a0b4SWilliam Wang 5350b55f3fbSlwd def isPrefetch(op: UInt): Bool = op(3) && (op(5, 4) === "b000".U) && (op(8, 7) === "b00".U) 536d200f594SWilliam Wang 537d200f594SWilliam Wang // store pipeline 538d200f594SWilliam Wang // normal store 539d200f594SWilliam Wang // bit encoding: | store 00 | size(2bit) | 540d200f594SWilliam Wang def sb = "b0000".U 541d200f594SWilliam Wang def sh = "b0001".U 542d200f594SWilliam Wang def sw = "b0010".U 543d200f594SWilliam Wang def sd = "b0011".U 544d200f594SWilliam Wang 545d0de7e4aSpeixiaokun //hypervisor store 546d0de7e4aSpeixiaokun // bit encoding: |hsv 1 | store 00 | size(2bit) | 547d0de7e4aSpeixiaokun def hsvb = "b10000".U 548d0de7e4aSpeixiaokun def hsvh = "b10001".U 549d0de7e4aSpeixiaokun def hsvw = "b10010".U 550d0de7e4aSpeixiaokun def hsvd = "b10011".U 5510b55f3fbSlwd def isHsv(op: UInt): Bool = op(4) && (op(5) === "b0".U) && (op(8, 7) === "b00".U) 552d200f594SWilliam Wang // l1 cache op 553d200f594SWilliam Wang // bit encoding: | cbo_zero 01 | size(2bit) 11 | 554d200f594SWilliam Wang def cbo_zero = "b0111".U 555d200f594SWilliam Wang 556d200f594SWilliam Wang // llc op 557d200f594SWilliam Wang // bit encoding: | prefetch 11 | suboptype(2bit) | 558d200f594SWilliam Wang def cbo_clean = "b1100".U 559d200f594SWilliam Wang def cbo_flush = "b1101".U 560d200f594SWilliam Wang def cbo_inval = "b1110".U 561d200f594SWilliam Wang 562136f6497SXiaokun-Pei def isCbo(op: UInt): Bool = op(3, 2) === "b11".U && (op(6, 4) === "b000".U) 5632225d46eSJiawei Lin 5642225d46eSJiawei Lin // atomics 5652225d46eSJiawei Lin // bit(1, 0) are size 5662225d46eSJiawei Lin // since atomics use a different fu type 5672225d46eSJiawei Lin // so we can safely reuse other load/store's encodings 568d200f594SWilliam Wang // bit encoding: | optype(4bit) | size (2bit) | 5692225d46eSJiawei Lin def lr_w = "b000010".U 5702225d46eSJiawei Lin def sc_w = "b000110".U 5712225d46eSJiawei Lin def amoswap_w = "b001010".U 5722225d46eSJiawei Lin def amoadd_w = "b001110".U 5732225d46eSJiawei Lin def amoxor_w = "b010010".U 5742225d46eSJiawei Lin def amoand_w = "b010110".U 5752225d46eSJiawei Lin def amoor_w = "b011010".U 5762225d46eSJiawei Lin def amomin_w = "b011110".U 5772225d46eSJiawei Lin def amomax_w = "b100010".U 5782225d46eSJiawei Lin def amominu_w = "b100110".U 5792225d46eSJiawei Lin def amomaxu_w = "b101010".U 5802225d46eSJiawei Lin 5812225d46eSJiawei Lin def lr_d = "b000011".U 5822225d46eSJiawei Lin def sc_d = "b000111".U 5832225d46eSJiawei Lin def amoswap_d = "b001011".U 5842225d46eSJiawei Lin def amoadd_d = "b001111".U 5852225d46eSJiawei Lin def amoxor_d = "b010011".U 5862225d46eSJiawei Lin def amoand_d = "b010111".U 5872225d46eSJiawei Lin def amoor_d = "b011011".U 5882225d46eSJiawei Lin def amomin_d = "b011111".U 5892225d46eSJiawei Lin def amomax_d = "b100011".U 5902225d46eSJiawei Lin def amominu_d = "b100111".U 5912225d46eSJiawei Lin def amomaxu_d = "b101011".U 592b6982e83SLemover 593b6982e83SLemover def size(op: UInt) = op(1,0) 5946dbb4e08SXuan Hu 59532977e5dSAnzooooo def getVecLSMop(fuOpType: UInt): UInt = fuOpType(6, 5) 59632977e5dSAnzooooo 5970b55f3fbSlwd def isAllUS (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && !fuOpType(4) && (fuOpType(8) ^ fuOpType(7))// Unit-Stride Whole Masked 5980b55f3fbSlwd def isUStride(fuOpType: UInt): Bool = fuOpType(6, 0) === "b00_00000".U && (fuOpType(8) ^ fuOpType(7)) 5990b55f3fbSlwd def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U && (fuOpType(8) ^ fuOpType(7)) 6000b55f3fbSlwd def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U && (fuOpType(8) ^ fuOpType(7)) 6010b55f3fbSlwd def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U && (fuOpType(8) ^ fuOpType(7)) 6020b55f3fbSlwd def isIndexed(fuOpType: UInt): Bool = fuOpType(5) && (fuOpType(8) ^ fuOpType(7)) 6032225d46eSJiawei Lin } 6042225d46eSJiawei Lin 6053feeca58Szfw object BKUOpType { 606ee8ff153Szfw 6073feeca58Szfw def clmul = "b000000".U 6083feeca58Szfw def clmulh = "b000001".U 6093feeca58Szfw def clmulr = "b000010".U 6103feeca58Szfw def xpermn = "b000100".U 6113feeca58Szfw def xpermb = "b000101".U 612ee8ff153Szfw 6133feeca58Szfw def clz = "b001000".U 6143feeca58Szfw def clzw = "b001001".U 6153feeca58Szfw def ctz = "b001010".U 6163feeca58Szfw def ctzw = "b001011".U 6173feeca58Szfw def cpop = "b001100".U 6183feeca58Szfw def cpopw = "b001101".U 61907596dc6Szfw 6203feeca58Szfw // 01xxxx is reserve 6213feeca58Szfw def aes64es = "b100000".U 6223feeca58Szfw def aes64esm = "b100001".U 6233feeca58Szfw def aes64ds = "b100010".U 6243feeca58Szfw def aes64dsm = "b100011".U 6253feeca58Szfw def aes64im = "b100100".U 6263feeca58Szfw def aes64ks1i = "b100101".U 6273feeca58Szfw def aes64ks2 = "b100110".U 6283feeca58Szfw 6293feeca58Szfw // merge to two instruction sm4ks & sm4ed 63019bcce38SFawang Zhang def sm4ed0 = "b101000".U 63119bcce38SFawang Zhang def sm4ed1 = "b101001".U 63219bcce38SFawang Zhang def sm4ed2 = "b101010".U 63319bcce38SFawang Zhang def sm4ed3 = "b101011".U 63419bcce38SFawang Zhang def sm4ks0 = "b101100".U 63519bcce38SFawang Zhang def sm4ks1 = "b101101".U 63619bcce38SFawang Zhang def sm4ks2 = "b101110".U 63719bcce38SFawang Zhang def sm4ks3 = "b101111".U 6383feeca58Szfw 6393feeca58Szfw def sha256sum0 = "b110000".U 6403feeca58Szfw def sha256sum1 = "b110001".U 6413feeca58Szfw def sha256sig0 = "b110010".U 6423feeca58Szfw def sha256sig1 = "b110011".U 6433feeca58Szfw def sha512sum0 = "b110100".U 6443feeca58Szfw def sha512sum1 = "b110101".U 6453feeca58Szfw def sha512sig0 = "b110110".U 6463feeca58Szfw def sha512sig1 = "b110111".U 6473feeca58Szfw 6483feeca58Szfw def sm3p0 = "b111000".U 6493feeca58Szfw def sm3p1 = "b111001".U 650ee8ff153Szfw } 651ee8ff153Szfw 6522225d46eSJiawei Lin object BTBtype { 6532225d46eSJiawei Lin def B = "b00".U // branch 6542225d46eSJiawei Lin def J = "b01".U // jump 6552225d46eSJiawei Lin def I = "b10".U // indirect 6562225d46eSJiawei Lin def R = "b11".U // return 6572225d46eSJiawei Lin 6582225d46eSJiawei Lin def apply() = UInt(2.W) 6592225d46eSJiawei Lin } 6602225d46eSJiawei Lin 6612225d46eSJiawei Lin object SelImm { 662ee8ff153Szfw def IMM_X = "b0111".U 663d91483a6Sfdy def IMM_S = "b1110".U 664ee8ff153Szfw def IMM_SB = "b0001".U 665ee8ff153Szfw def IMM_U = "b0010".U 666ee8ff153Szfw def IMM_UJ = "b0011".U 667ee8ff153Szfw def IMM_I = "b0100".U 668ee8ff153Szfw def IMM_Z = "b0101".U 669ee8ff153Szfw def INVALID_INSTR = "b0110".U 670ee8ff153Szfw def IMM_B6 = "b1000".U 6712225d46eSJiawei Lin 67258c35d23Shuxuan0307 def IMM_OPIVIS = "b1001".U 67358c35d23Shuxuan0307 def IMM_OPIVIU = "b1010".U 674912e2179SXuan Hu def IMM_VSETVLI = "b1100".U 675912e2179SXuan Hu def IMM_VSETIVLI = "b1101".U 676fe528fd6Ssinsanction def IMM_LUI32 = "b1011".U 677867aae77Sweiding liu def IMM_VRORVI = "b1111".U 67858c35d23Shuxuan0307 67957a10886SXuan Hu def X = BitPat("b0000") 6806e7c9679Shuxuan0307 681ee8ff153Szfw def apply() = UInt(4.W) 6820655b1a0SXuan Hu 6830655b1a0SXuan Hu def mkString(immType: UInt) : String = { 6840655b1a0SXuan Hu val strMap = Map( 6850655b1a0SXuan Hu IMM_S.litValue -> "S", 6860655b1a0SXuan Hu IMM_SB.litValue -> "SB", 6870655b1a0SXuan Hu IMM_U.litValue -> "U", 6880655b1a0SXuan Hu IMM_UJ.litValue -> "UJ", 6890655b1a0SXuan Hu IMM_I.litValue -> "I", 6900655b1a0SXuan Hu IMM_Z.litValue -> "Z", 6910655b1a0SXuan Hu IMM_B6.litValue -> "B6", 6920655b1a0SXuan Hu IMM_OPIVIS.litValue -> "VIS", 6930655b1a0SXuan Hu IMM_OPIVIU.litValue -> "VIU", 6940655b1a0SXuan Hu IMM_VSETVLI.litValue -> "VSETVLI", 6950655b1a0SXuan Hu IMM_VSETIVLI.litValue -> "VSETIVLI", 696fe528fd6Ssinsanction IMM_LUI32.litValue -> "LUI32", 6977e30d16cSZhaoyang You IMM_VRORVI.litValue -> "VRORVI", 6980655b1a0SXuan Hu INVALID_INSTR.litValue -> "INVALID", 6990655b1a0SXuan Hu ) 7000655b1a0SXuan Hu strMap(immType.litValue) 7010655b1a0SXuan Hu } 702520f7dacSsinsanction 703520f7dacSsinsanction def getImmUnion(immType: UInt) : Imm = { 704520f7dacSsinsanction val iuMap = Map( 705520f7dacSsinsanction IMM_S.litValue -> ImmUnion.S, 706520f7dacSsinsanction IMM_SB.litValue -> ImmUnion.B, 707520f7dacSsinsanction IMM_U.litValue -> ImmUnion.U, 708520f7dacSsinsanction IMM_UJ.litValue -> ImmUnion.J, 709520f7dacSsinsanction IMM_I.litValue -> ImmUnion.I, 710520f7dacSsinsanction IMM_Z.litValue -> ImmUnion.Z, 711520f7dacSsinsanction IMM_B6.litValue -> ImmUnion.B6, 712520f7dacSsinsanction IMM_OPIVIS.litValue -> ImmUnion.OPIVIS, 713520f7dacSsinsanction IMM_OPIVIU.litValue -> ImmUnion.OPIVIU, 714520f7dacSsinsanction IMM_VSETVLI.litValue -> ImmUnion.VSETVLI, 715520f7dacSsinsanction IMM_VSETIVLI.litValue -> ImmUnion.VSETIVLI, 716520f7dacSsinsanction IMM_LUI32.litValue -> ImmUnion.LUI32, 7173ca6072cSsinceforYy IMM_VRORVI.litValue -> ImmUnion.VRORVI, 718520f7dacSsinsanction ) 719520f7dacSsinsanction iuMap(immType.litValue) 720520f7dacSsinsanction } 7212225d46eSJiawei Lin } 7222225d46eSJiawei Lin 723e2695e90SzhanglyGit object UopSplitType { 724d91483a6Sfdy def SCA_SIM = "b000000".U // 725e25c13faSXuan Hu def VSET = "b010001".U // dirty: vset 726d91483a6Sfdy def VEC_VVV = "b010010".U // VEC_VVV 727d91483a6Sfdy def VEC_VXV = "b010011".U // VEC_VXV 728d91483a6Sfdy def VEC_0XV = "b010100".U // VEC_0XV 729d91483a6Sfdy def VEC_VVW = "b010101".U // VEC_VVW 730d91483a6Sfdy def VEC_WVW = "b010110".U // VEC_WVW 731d91483a6Sfdy def VEC_VXW = "b010111".U // VEC_VXW 732d91483a6Sfdy def VEC_WXW = "b011000".U // VEC_WXW 733d91483a6Sfdy def VEC_WVV = "b011001".U // VEC_WVV 734d91483a6Sfdy def VEC_WXV = "b011010".U // VEC_WXV 735d91483a6Sfdy def VEC_EXT2 = "b011011".U // VF2 0 -> V 736d91483a6Sfdy def VEC_EXT4 = "b011100".U // VF4 0 -> V 737d91483a6Sfdy def VEC_EXT8 = "b011101".U // VF8 0 -> V 738d91483a6Sfdy def VEC_VVM = "b011110".U // VEC_VVM 739d91483a6Sfdy def VEC_VXM = "b011111".U // VEC_VXM 740d91483a6Sfdy def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 741d91483a6Sfdy def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 742d91483a6Sfdy def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 743d91483a6Sfdy def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 744d91483a6Sfdy def VEC_VRED = "b100100".U // VEC_VRED 745d91483a6Sfdy def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 746d91483a6Sfdy def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 747d91483a6Sfdy def VEC_M0X = "b101001".U // VEC_M0X 0MV 748d91483a6Sfdy def VEC_MVV = "b101010".U // VEC_MVV VMV 74984260280Sczw def VEC_VWW = "b101100".U // 75065df1368Sczw def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 75165df1368Sczw def VEC_RGATHER_VX = "b101110".U // vrgather.vx 75265df1368Sczw def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 753adf68ff3Sczw def VEC_COMPRESS = "b110000".U // vcompress.vm 754c4501a6fSZiyue-Zhang def VEC_US_LDST = "b110001".U // vector unit-strided load/store 755c4501a6fSZiyue-Zhang def VEC_S_LDST = "b110010".U // vector strided load/store 756c4501a6fSZiyue-Zhang def VEC_I_LDST = "b110011".U // vector indexed load/store 757684d7aceSxiaofeibao-xjtu def VEC_VFV = "b111000".U // VEC_VFV 7583748ec56Sxiaofeibao-xjtu def VEC_VFW = "b111001".U // VEC_VFW 7593748ec56Sxiaofeibao-xjtu def VEC_WFW = "b111010".U // VEC_WVW 760f06d6d60Sxiaofeibao-xjtu def VEC_VFM = "b111011".U // VEC_VFM 761582849ffSxiaofeibao-xjtu def VEC_VFRED = "b111100".U // VEC_VFRED 762b94b1889Sxiaofeibao-xjtu def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 763d91483a6Sfdy def VEC_M0M = "b000000".U // VEC_M0M 764d91483a6Sfdy def VEC_MMM = "b000000".U // VEC_MMM 7650a34fc22SZiyue Zhang def VEC_MVNR = "b000100".U // vmvnr 766d91483a6Sfdy def dummy = "b111111".U 767d91483a6Sfdy 768d91483a6Sfdy def X = BitPat("b000000") 769d91483a6Sfdy 770d91483a6Sfdy def apply() = UInt(6.W) 771e2695e90SzhanglyGit def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 772d91483a6Sfdy } 773d91483a6Sfdy 7746ab6918fSYinan Xu object ExceptionNO { 7756ab6918fSYinan Xu def instrAddrMisaligned = 0 7766ab6918fSYinan Xu def instrAccessFault = 1 7776ab6918fSYinan Xu def illegalInstr = 2 7786ab6918fSYinan Xu def breakPoint = 3 7796ab6918fSYinan Xu def loadAddrMisaligned = 4 7806ab6918fSYinan Xu def loadAccessFault = 5 7816ab6918fSYinan Xu def storeAddrMisaligned = 6 7826ab6918fSYinan Xu def storeAccessFault = 7 7836ab6918fSYinan Xu def ecallU = 8 7846ab6918fSYinan Xu def ecallS = 9 785d0de7e4aSpeixiaokun def ecallVS = 10 7866ab6918fSYinan Xu def ecallM = 11 7876ab6918fSYinan Xu def instrPageFault = 12 7886ab6918fSYinan Xu def loadPageFault = 13 7896ab6918fSYinan Xu // def singleStep = 14 7906ab6918fSYinan Xu def storePageFault = 15 791d0de7e4aSpeixiaokun def instrGuestPageFault = 20 792d0de7e4aSpeixiaokun def loadGuestPageFault = 21 793d0de7e4aSpeixiaokun def virtualInstr = 22 794d0de7e4aSpeixiaokun def storeGuestPageFault = 23 795826a8e0eSXuan Hu 796826a8e0eSXuan Hu // Just alias 797826a8e0eSXuan Hu def EX_IAM = instrAddrMisaligned 798826a8e0eSXuan Hu def EX_IAF = instrAccessFault 799826a8e0eSXuan Hu def EX_II = illegalInstr 800826a8e0eSXuan Hu def EX_BP = breakPoint 801826a8e0eSXuan Hu def EX_LAM = loadAddrMisaligned 802826a8e0eSXuan Hu def EX_LAF = loadAccessFault 803826a8e0eSXuan Hu def EX_SAM = storeAddrMisaligned 804826a8e0eSXuan Hu def EX_SAF = storeAccessFault 805826a8e0eSXuan Hu def EX_UCALL = ecallU 806826a8e0eSXuan Hu def EX_HSCALL = ecallS 807826a8e0eSXuan Hu def EX_VSCALL = ecallVS 808826a8e0eSXuan Hu def EX_MCALL = ecallM 809826a8e0eSXuan Hu def EX_IPF = instrPageFault 810826a8e0eSXuan Hu def EX_LPF = loadPageFault 811826a8e0eSXuan Hu def EX_SPF = storePageFault 812826a8e0eSXuan Hu def EX_IGPF = instrGuestPageFault 813826a8e0eSXuan Hu def EX_LGPF = loadGuestPageFault 814826a8e0eSXuan Hu def EX_VI = virtualInstr 815826a8e0eSXuan Hu def EX_SGPF = storeGuestPageFault 816826a8e0eSXuan Hu 817f60da58cSXuan Hu def getAddressMisaligned = Seq(EX_IAM, EX_LAM, EX_SAM) 818f60da58cSXuan Hu 819f60da58cSXuan Hu def getAccessFault = Seq(EX_IAF, EX_LAF, EX_SAF) 820f60da58cSXuan Hu 821f60da58cSXuan Hu def getPageFault = Seq(EX_IPF, EX_LPF, EX_SPF) 822f60da58cSXuan Hu 823f60da58cSXuan Hu def getGuestPageFault = Seq(EX_IGPF, EX_LGPF, EX_SGPF) 824f60da58cSXuan Hu 825bfac3305Speixiaokun def getLSGuestPageFault = Seq(EX_LGPF, EX_SGPF) 826bfac3305Speixiaokun 827f60da58cSXuan Hu def getFetchFault = Seq(EX_IAM, EX_IAF, EX_IPF) 828f60da58cSXuan Hu 829f60da58cSXuan Hu def getLoadFault = Seq(EX_LAM, EX_LAF, EX_LPF) 830f60da58cSXuan Hu 831f60da58cSXuan Hu def getStoreFault = Seq(EX_SAM, EX_SAF, EX_SPF) 832f60da58cSXuan Hu 8336ab6918fSYinan Xu def priorities = Seq( 8346ab6918fSYinan Xu breakPoint, // TODO: different BP has different priority 8356ab6918fSYinan Xu instrPageFault, 836d0de7e4aSpeixiaokun instrGuestPageFault, 8376ab6918fSYinan Xu instrAccessFault, 8386ab6918fSYinan Xu illegalInstr, 839d0de7e4aSpeixiaokun virtualInstr, 8406ab6918fSYinan Xu instrAddrMisaligned, 841d0de7e4aSpeixiaokun ecallM, ecallS, ecallVS, ecallU, 842d880177dSYinan Xu storeAddrMisaligned, 843d880177dSYinan Xu loadAddrMisaligned, 8446ab6918fSYinan Xu storePageFault, 8456ab6918fSYinan Xu loadPageFault, 846d0de7e4aSpeixiaokun storeGuestPageFault, 847d0de7e4aSpeixiaokun loadGuestPageFault, 8486ab6918fSYinan Xu storeAccessFault, 849d880177dSYinan Xu loadAccessFault 8506ab6918fSYinan Xu ) 85173e616deSXuan Hu 85273e616deSXuan Hu def getHigherExcpThan(excp: Int): Seq[Int] = { 85373e616deSXuan Hu val idx = this.priorities.indexOf(excp, 0) 85473e616deSXuan Hu require(idx != -1, s"The irq($excp) does not exists in IntPriority Seq") 85573e616deSXuan Hu this.priorities.slice(0, idx) 85673e616deSXuan Hu } 85773e616deSXuan Hu 8586ab6918fSYinan Xu def all = priorities.distinct.sorted 8596ab6918fSYinan Xu def frontendSet = Seq( 8606ab6918fSYinan Xu instrAddrMisaligned, 8616ab6918fSYinan Xu instrAccessFault, 8626ab6918fSYinan Xu illegalInstr, 863d0de7e4aSpeixiaokun instrPageFault, 864d0de7e4aSpeixiaokun instrGuestPageFault, 865*7e0f64b0SGuanghui Cheng virtualInstr, 866*7e0f64b0SGuanghui Cheng breakPoint 8676ab6918fSYinan Xu ) 8686ab6918fSYinan Xu def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 8696ab6918fSYinan Xu val new_vec = Wire(ExceptionVec()) 8706ab6918fSYinan Xu new_vec.foreach(_ := false.B) 8716ab6918fSYinan Xu select.foreach(i => new_vec(i) := vec(i)) 8726ab6918fSYinan Xu new_vec 8736ab6918fSYinan Xu } 8746ab6918fSYinan Xu def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 8756ab6918fSYinan Xu def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 8766ab6918fSYinan Xu def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 8776ab6918fSYinan Xu partialSelect(vec, fuConfig.exceptionOut) 8786ab6918fSYinan Xu } 8796ab6918fSYinan Xu 880d2b20d1aSTang Haojin object TopDownCounters extends Enumeration { 881d2b20d1aSTang Haojin val NoStall = Value("NoStall") // Base 882d2b20d1aSTang Haojin // frontend 883d2b20d1aSTang Haojin val OverrideBubble = Value("OverrideBubble") 884d2b20d1aSTang Haojin val FtqUpdateBubble = Value("FtqUpdateBubble") 885d2b20d1aSTang Haojin // val ControlRedirectBubble = Value("ControlRedirectBubble") 886d2b20d1aSTang Haojin val TAGEMissBubble = Value("TAGEMissBubble") 887d2b20d1aSTang Haojin val SCMissBubble = Value("SCMissBubble") 888d2b20d1aSTang Haojin val ITTAGEMissBubble = Value("ITTAGEMissBubble") 889d2b20d1aSTang Haojin val RASMissBubble = Value("RASMissBubble") 890d2b20d1aSTang Haojin val MemVioRedirectBubble = Value("MemVioRedirectBubble") 891d2b20d1aSTang Haojin val OtherRedirectBubble = Value("OtherRedirectBubble") 892d2b20d1aSTang Haojin val FtqFullStall = Value("FtqFullStall") 893d2b20d1aSTang Haojin 894d2b20d1aSTang Haojin val ICacheMissBubble = Value("ICacheMissBubble") 895d2b20d1aSTang Haojin val ITLBMissBubble = Value("ITLBMissBubble") 896d2b20d1aSTang Haojin val BTBMissBubble = Value("BTBMissBubble") 897d2b20d1aSTang Haojin val FetchFragBubble = Value("FetchFragBubble") 898d2b20d1aSTang Haojin 899d2b20d1aSTang Haojin // backend 900d2b20d1aSTang Haojin // long inst stall at rob head 901d2b20d1aSTang Haojin val DivStall = Value("DivStall") // int div, float div/sqrt 902d2b20d1aSTang Haojin val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 903d2b20d1aSTang Haojin val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 904d2b20d1aSTang Haojin val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 905d2b20d1aSTang Haojin // freelist full 906d2b20d1aSTang Haojin val IntFlStall = Value("IntFlStall") 907d2b20d1aSTang Haojin val FpFlStall = Value("FpFlStall") 9084eebf274Ssinsanction val VecFlStall = Value("VecFlStall") 909368cbcecSxiaofeibao val V0FlStall = Value("V0FlStall") 910368cbcecSxiaofeibao val VlFlStall = Value("VlFlStall") 911368cbcecSxiaofeibao val MultiFlStall = Value("MultiFlStall") 912d2b20d1aSTang Haojin // dispatch queue full 913d2b20d1aSTang Haojin val IntDqStall = Value("IntDqStall") 914d2b20d1aSTang Haojin val FpDqStall = Value("FpDqStall") 915d2b20d1aSTang Haojin val LsDqStall = Value("LsDqStall") 916d2b20d1aSTang Haojin 917d2b20d1aSTang Haojin // memblock 918d2b20d1aSTang Haojin val LoadTLBStall = Value("LoadTLBStall") 919d2b20d1aSTang Haojin val LoadL1Stall = Value("LoadL1Stall") 920d2b20d1aSTang Haojin val LoadL2Stall = Value("LoadL2Stall") 921d2b20d1aSTang Haojin val LoadL3Stall = Value("LoadL3Stall") 922d2b20d1aSTang Haojin val LoadMemStall = Value("LoadMemStall") 923d2b20d1aSTang Haojin val StoreStall = Value("StoreStall") // include store tlb miss 924d2b20d1aSTang Haojin val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 925d2b20d1aSTang Haojin 926d2b20d1aSTang Haojin // xs replay (different to gem5) 927d2b20d1aSTang Haojin val LoadVioReplayStall = Value("LoadVioReplayStall") 928d2b20d1aSTang Haojin val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 929d2b20d1aSTang Haojin 930d2b20d1aSTang Haojin // bad speculation 931d2b20d1aSTang Haojin val ControlRecoveryStall = Value("ControlRecoveryStall") 932d2b20d1aSTang Haojin val MemVioRecoveryStall = Value("MemVioRecoveryStall") 933d2b20d1aSTang Haojin val OtherRecoveryStall = Value("OtherRecoveryStall") 934d2b20d1aSTang Haojin 935d2b20d1aSTang Haojin val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 936d2b20d1aSTang Haojin 937d2b20d1aSTang Haojin val OtherCoreStall = Value("OtherCoreStall") 938d2b20d1aSTang Haojin 939d2b20d1aSTang Haojin val NumStallReasons = Value("NumStallReasons") 940d2b20d1aSTang Haojin } 9419a2e6b8aSLinJiawei} 942