xref: /XiangShan/src/main/scala/xiangshan/package.scala (revision 3a2e64c4cc8eb6361b77f8cc81e35f391922dd99)
1c6d43980SLemover/***************************************************************************************
2c6d43980SLemover* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3f320e0f0SYinan Xu* Copyright (c) 2020-2021 Peng Cheng Laboratory
4c6d43980SLemover*
5c6d43980SLemover* XiangShan is licensed under Mulan PSL v2.
6c6d43980SLemover* You can use this software according to the terms and conditions of the Mulan PSL v2.
7c6d43980SLemover* You may obtain a copy of Mulan PSL v2 at:
8c6d43980SLemover*          http://license.coscl.org.cn/MulanPSL2
9c6d43980SLemover*
10c6d43980SLemover* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11c6d43980SLemover* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12c6d43980SLemover* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13c6d43980SLemover*
14c6d43980SLemover* See the Mulan PSL v2 for more details.
15c6d43980SLemover***************************************************************************************/
16c6d43980SLemover
179a2e6b8aSLinJiaweiimport chisel3._
189a2e6b8aSLinJiaweiimport chisel3.util._
192225d46eSJiawei Linimport chipsalliance.rocketchip.config.Parameters
202225d46eSJiawei Linimport freechips.rocketchip.tile.XLen
216ab6918fSYinan Xuimport xiangshan.ExceptionNO._
2254034ccdSZhangZifeiimport xiangshan.backend.issue._
232225d46eSJiawei Linimport xiangshan.backend.fu._
242225d46eSJiawei Linimport xiangshan.backend.fu.fpu._
256827759bSZhangZifeiimport xiangshan.backend.fu.vector._
262225d46eSJiawei Linimport xiangshan.backend.exu._
2754034ccdSZhangZifeiimport xiangshan.backend.{Std, ScheLaneConfig}
282225d46eSJiawei Lin
299a2e6b8aSLinJiaweipackage object xiangshan {
309ee9f926SYikeZhou  object SrcType {
311285b047SXuan Hu    def imm = "b000".U
321285b047SXuan Hu    def pc  = "b000".U
331285b047SXuan Hu    def xp  = "b001".U
341285b047SXuan Hu    def fp  = "b010".U
351285b047SXuan Hu    def vp  = "b100".U
3604b56283SZhangZifei
371285b047SXuan Hu    // alias
381285b047SXuan Hu    def reg = this.xp
391a3df1feSYikeZhou    def DC  = imm // Don't Care
401285b047SXuan Hu    def X   = BitPat("b???")
414d24c305SYikeZhou
4204b56283SZhangZifei    def isPc(srcType: UInt) = srcType===pc
4304b56283SZhangZifei    def isImm(srcType: UInt) = srcType===imm
441285b047SXuan Hu    def isReg(srcType: UInt) = srcType(0)
452b4e8253SYinan Xu    def isFp(srcType: UInt) = srcType(1)
461285b047SXuan Hu    def isVp(srcType: UInt) = srcType(2)
471285b047SXuan Hu    def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType)
4804b56283SZhangZifei
491285b047SXuan Hu    def apply() = UInt(3.W)
509a2e6b8aSLinJiawei  }
519a2e6b8aSLinJiawei
529a2e6b8aSLinJiawei  object SrcState {
53100aa93cSYinan Xu    def busy    = "b0".U
54100aa93cSYinan Xu    def rdy     = "b1".U
55100aa93cSYinan Xu    // def specRdy = "b10".U // speculative ready, for future use
56100aa93cSYinan Xu    def apply() = UInt(1.W)
579a2e6b8aSLinJiawei  }
589a2e6b8aSLinJiawei
597f2b7720SXuan Hu  // Todo: Use OH instead
602225d46eSJiawei Lin  object FuType {
61cafb3558SLinJiawei    def jmp          = "b0000".U
62cafb3558SLinJiawei    def i2f          = "b0001".U
63cafb3558SLinJiawei    def csr          = "b0010".U
64975b9ea3SYinan Xu    def alu          = "b0110".U
65cafb3558SLinJiawei    def mul          = "b0100".U
66cafb3558SLinJiawei    def div          = "b0101".U
67975b9ea3SYinan Xu    def fence        = "b0011".U
683feeca58Szfw    def bku          = "b0111".U
69cafb3558SLinJiawei
70cafb3558SLinJiawei    def fmac         = "b1000".U
7192ab24ebSYinan Xu    def fmisc        = "b1011".U
72cafb3558SLinJiawei    def fDivSqrt     = "b1010".U
73cafb3558SLinJiawei
74cafb3558SLinJiawei    def ldu          = "b1100".U
75cafb3558SLinJiawei    def stu          = "b1101".U
7692ab24ebSYinan Xu    def mou          = "b1111".U // for amo, lr, sc, fence
777f2b7720SXuan Hu    def vipu         = "b10000".U
787f2b7720SXuan Hu    def vfpu         = "b11000".U
797f2b7720SXuan Hu    def vldu         = "b11100".U
807f2b7720SXuan Hu    def vstu         = "b11101".U
816e7c9679Shuxuan0307    def X            = BitPat("b????")
826e7c9679Shuxuan0307
837f2b7720SXuan Hu    def num = 18
842225d46eSJiawei Lin
859a2e6b8aSLinJiawei    def apply() = UInt(log2Up(num).W)
869a2e6b8aSLinJiawei
87cafb3558SLinJiawei    def isIntExu(fuType: UInt) = !fuType(3)
886ac289b3SLinJiawei    def isJumpExu(fuType: UInt) = fuType === jmp
89cafb3558SLinJiawei    def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U
90cafb3558SLinJiawei    def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U
9192ab24ebSYinan Xu    def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1)
9292ab24ebSYinan Xu    def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0)
930f9d3717SYinan Xu    def isAMO(fuType: UInt) = fuType(1)
94af2f7849Shappy-lx    def isFence(fuType: UInt) = fuType === fence
95af2f7849Shappy-lx    def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush
96af2f7849Shappy-lx    def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush
97af2f7849Shappy-lx    def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush
98af2f7849Shappy-lx
9992ab24ebSYinan Xu
10092ab24ebSYinan Xu    def jmpCanAccept(fuType: UInt) = !fuType(2)
101ee8ff153Szfw    def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0)
102ee8ff153Szfw    def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0)
10392ab24ebSYinan Xu
10492ab24ebSYinan Xu    def fmacCanAccept(fuType: UInt) = !fuType(1)
10592ab24ebSYinan Xu    def fmiscCanAccept(fuType: UInt) = fuType(1)
10692ab24ebSYinan Xu
10792ab24ebSYinan Xu    def loadCanAccept(fuType: UInt) = !fuType(0)
10892ab24ebSYinan Xu    def storeCanAccept(fuType: UInt) = fuType(0)
10992ab24ebSYinan Xu
11092ab24ebSYinan Xu    def storeIsAMO(fuType: UInt) = fuType(1)
111cafb3558SLinJiawei
112cafb3558SLinJiawei    val functionNameMap = Map(
113cafb3558SLinJiawei      jmp.litValue() -> "jmp",
114ebb8ebf8SYinan Xu      i2f.litValue() -> "int_to_float",
115cafb3558SLinJiawei      csr.litValue() -> "csr",
116cafb3558SLinJiawei      alu.litValue() -> "alu",
117cafb3558SLinJiawei      mul.litValue() -> "mul",
118cafb3558SLinJiawei      div.litValue() -> "div",
119b8f08ca0SZhangZifei      fence.litValue() -> "fence",
1203feeca58Szfw      bku.litValue() -> "bku",
121cafb3558SLinJiawei      fmac.litValue() -> "fmac",
122cafb3558SLinJiawei      fmisc.litValue() -> "fmisc",
123d18dc7e6Swakafa      fDivSqrt.litValue() -> "fdiv_fsqrt",
124cafb3558SLinJiawei      ldu.litValue() -> "load",
125ebb8ebf8SYinan Xu      stu.litValue() -> "store",
126ebb8ebf8SYinan Xu      mou.litValue() -> "mou"
127cafb3558SLinJiawei    )
1289a2e6b8aSLinJiawei  }
1299a2e6b8aSLinJiawei
1302225d46eSJiawei Lin  object FuOpType {
131675acc68SYinan Xu    def apply() = UInt(7.W)
132361e6d51SJiuyang Liu    def X = BitPat("b???????")
133ebd97ecbSzhanglinjuan  }
134518d8658SYinan Xu
135*3a2e64c4SZhangZifei  // move VipuType and VfpuType into YunSuan/package.scala
136*3a2e64c4SZhangZifei  // object VipuType {
137*3a2e64c4SZhangZifei  //   def dummy = 0.U(7.W)
138*3a2e64c4SZhangZifei  // }
1397f2b7720SXuan Hu
140*3a2e64c4SZhangZifei  // object VfpuType {
141*3a2e64c4SZhangZifei  //   def dummy = 0.U(7.W)
142*3a2e64c4SZhangZifei  // }
1437f2b7720SXuan Hu
1447f2b7720SXuan Hu  object VlduType {
1457f2b7720SXuan Hu    def dummy = 0.U(7.W)
1467f2b7720SXuan Hu  }
1477f2b7720SXuan Hu
1487f2b7720SXuan Hu  object VstuType {
1497f2b7720SXuan Hu    def dummy = 0.U(7.W)
1507f2b7720SXuan Hu  }
1517f2b7720SXuan Hu
152a3edac52SYinan Xu  object CommitType {
153c3abb8b6SYinan Xu    def NORMAL = "b000".U  // int/fp
154c3abb8b6SYinan Xu    def BRANCH = "b001".U  // branch
155c3abb8b6SYinan Xu    def LOAD   = "b010".U  // load
156c3abb8b6SYinan Xu    def STORE  = "b011".U  // store
157518d8658SYinan Xu
158c3abb8b6SYinan Xu    def apply() = UInt(3.W)
159c3abb8b6SYinan Xu    def isFused(commitType: UInt): Bool = commitType(2)
160c3abb8b6SYinan Xu    def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1)
161c3abb8b6SYinan Xu    def lsInstIsStore(commitType: UInt): Bool = commitType(0)
162c3abb8b6SYinan Xu    def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType)
163c3abb8b6SYinan Xu    def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType)
164518d8658SYinan Xu  }
165bfb958a3SYinan Xu
166bfb958a3SYinan Xu  object RedirectLevel {
1672d7c7105SYinan Xu    def flushAfter = "b0".U
1682d7c7105SYinan Xu    def flush      = "b1".U
169bfb958a3SYinan Xu
1702d7c7105SYinan Xu    def apply() = UInt(1.W)
1712d7c7105SYinan Xu    // def isUnconditional(level: UInt) = level(1)
172bfb958a3SYinan Xu    def flushItself(level: UInt) = level(0)
1732d7c7105SYinan Xu    // def isException(level: UInt) = level(1) && level(0)
174bfb958a3SYinan Xu  }
175baf8def6SYinan Xu
176baf8def6SYinan Xu  object ExceptionVec {
177baf8def6SYinan Xu    def apply() = Vec(16, Bool())
178baf8def6SYinan Xu  }
179a8e04b1dSYinan Xu
180c60c1ab4SWilliam Wang  object PMAMode {
1818d9a04fcSWilliam Wang    def R = "b1".U << 0 //readable
1828d9a04fcSWilliam Wang    def W = "b1".U << 1 //writeable
1838d9a04fcSWilliam Wang    def X = "b1".U << 2 //executable
1848d9a04fcSWilliam Wang    def I = "b1".U << 3 //cacheable: icache
1858d9a04fcSWilliam Wang    def D = "b1".U << 4 //cacheable: dcache
1868d9a04fcSWilliam Wang    def S = "b1".U << 5 //enable speculative access
187cff68e26SWilliam Wang    def A = "b1".U << 6 //enable atomic operation, A imply R & W
1888d9a04fcSWilliam Wang    def C = "b1".U << 7 //if it is cacheable is configable
189c60c1ab4SWilliam Wang    def Reserved = "b0".U
190c60c1ab4SWilliam Wang
191c60c1ab4SWilliam Wang    def apply() = UInt(7.W)
192c60c1ab4SWilliam Wang
193c60c1ab4SWilliam Wang    def read(mode: UInt) = mode(0)
194c60c1ab4SWilliam Wang    def write(mode: UInt) = mode(1)
195c60c1ab4SWilliam Wang    def execute(mode: UInt) = mode(2)
196c60c1ab4SWilliam Wang    def icache(mode: UInt) = mode(3)
197c60c1ab4SWilliam Wang    def dcache(mode: UInt) = mode(4)
198c60c1ab4SWilliam Wang    def speculate(mode: UInt) = mode(5)
199c60c1ab4SWilliam Wang    def atomic(mode: UInt) = mode(6)
200c60c1ab4SWilliam Wang    def configable_cache(mode: UInt) = mode(7)
201c60c1ab4SWilliam Wang
202c60c1ab4SWilliam Wang    def strToMode(s: String) = {
203423b9255SWilliam Wang      var result = 0.U(8.W)
204c60c1ab4SWilliam Wang      if (s.toUpperCase.indexOf("R") >= 0) result = result + R
205c60c1ab4SWilliam Wang      if (s.toUpperCase.indexOf("W") >= 0) result = result + W
206c60c1ab4SWilliam Wang      if (s.toUpperCase.indexOf("X") >= 0) result = result + X
207c60c1ab4SWilliam Wang      if (s.toUpperCase.indexOf("I") >= 0) result = result + I
208c60c1ab4SWilliam Wang      if (s.toUpperCase.indexOf("D") >= 0) result = result + D
209c60c1ab4SWilliam Wang      if (s.toUpperCase.indexOf("S") >= 0) result = result + S
210c60c1ab4SWilliam Wang      if (s.toUpperCase.indexOf("A") >= 0) result = result + A
211c60c1ab4SWilliam Wang      if (s.toUpperCase.indexOf("C") >= 0) result = result + C
212c60c1ab4SWilliam Wang      result
213c60c1ab4SWilliam Wang    }
214c60c1ab4SWilliam Wang  }
2152225d46eSJiawei Lin
2162225d46eSJiawei Lin
2172225d46eSJiawei Lin  object CSROpType {
2182225d46eSJiawei Lin    def jmp  = "b000".U
2192225d46eSJiawei Lin    def wrt  = "b001".U
2202225d46eSJiawei Lin    def set  = "b010".U
2212225d46eSJiawei Lin    def clr  = "b011".U
222b6900d94SYinan Xu    def wfi  = "b100".U
2232225d46eSJiawei Lin    def wrti = "b101".U
2242225d46eSJiawei Lin    def seti = "b110".U
2252225d46eSJiawei Lin    def clri = "b111".U
2265d669833SYinan Xu    def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U
2272225d46eSJiawei Lin  }
2282225d46eSJiawei Lin
2292225d46eSJiawei Lin  // jump
2302225d46eSJiawei Lin  object JumpOpType {
2312225d46eSJiawei Lin    def jal  = "b00".U
2322225d46eSJiawei Lin    def jalr = "b01".U
2332225d46eSJiawei Lin    def auipc = "b10".U
2342225d46eSJiawei Lin//    def call = "b11_011".U
2352225d46eSJiawei Lin//    def ret  = "b11_100".U
2362225d46eSJiawei Lin    def jumpOpisJalr(op: UInt) = op(0)
2372225d46eSJiawei Lin    def jumpOpisAuipc(op: UInt) = op(1)
2382225d46eSJiawei Lin  }
2392225d46eSJiawei Lin
2402225d46eSJiawei Lin  object FenceOpType {
2412225d46eSJiawei Lin    def fence  = "b10000".U
2422225d46eSJiawei Lin    def sfence = "b10001".U
2432225d46eSJiawei Lin    def fencei = "b10010".U
244af2f7849Shappy-lx    def nofence= "b00000".U
2452225d46eSJiawei Lin  }
2462225d46eSJiawei Lin
2472225d46eSJiawei Lin  object ALUOpType {
248ee8ff153Szfw    // shift optype
249675acc68SYinan Xu    def slliuw     = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt
250675acc68SYinan Xu    def sll        = "b000_0001".U // sll:     src1 << src2
251ee8ff153Szfw
252675acc68SYinan Xu    def bclr       = "b000_0010".U // bclr:    src1 & ~(1 << src2[5:0])
253675acc68SYinan Xu    def bset       = "b000_0011".U // bset:    src1 | (1 << src2[5:0])
254675acc68SYinan Xu    def binv       = "b000_0100".U // binv:    src1 ^ ~(1 << src2[5:0])
255ee8ff153Szfw
256675acc68SYinan Xu    def srl        = "b000_0101".U // srl:     src1 >> src2
257675acc68SYinan Xu    def bext       = "b000_0110".U // bext:    (src1 >> src2)[0]
258675acc68SYinan Xu    def sra        = "b000_0111".U // sra:     src1 >> src2 (arithmetic)
259ee8ff153Szfw
2607b441e5eSYinan Xu    def rol        = "b000_1001".U // rol:     (src1 << src2) | (src1 >> (xlen - src2))
2617b441e5eSYinan Xu    def ror        = "b000_1011".U // ror:     (src1 >> src2) | (src1 << (xlen - src2))
262184a1958Szfw
263ee8ff153Szfw    // RV64 32bit optype
264675acc68SYinan Xu    def addw       = "b001_0000".U // addw:      SEXT((src1 + src2)[31:0])
265675acc68SYinan Xu    def oddaddw    = "b001_0001".U // oddaddw:   SEXT((src1[0] + src2)[31:0])
266675acc68SYinan Xu    def subw       = "b001_0010".U // subw:      SEXT((src1 - src2)[31:0])
267ee8ff153Szfw
268675acc68SYinan Xu    def addwbit    = "b001_0100".U // addwbit:   (src1 + src2)[0]
269675acc68SYinan Xu    def addwbyte   = "b001_0101".U // addwbyte:  (src1 + src2)[7:0]
270675acc68SYinan Xu    def addwzexth  = "b001_0110".U // addwzexth: ZEXT((src1  + src2)[15:0])
271675acc68SYinan Xu    def addwsexth  = "b001_0111".U // addwsexth: SEXT((src1  + src2)[15:0])
272ee8ff153Szfw
273675acc68SYinan Xu    def sllw       = "b001_1000".U // sllw:     SEXT((src1 << src2)[31:0])
274675acc68SYinan Xu    def srlw       = "b001_1001".U // srlw:     SEXT((src1[31:0] >> src2)[31:0])
275675acc68SYinan Xu    def sraw       = "b001_1010".U // sraw:     SEXT((src1[31:0] >> src2)[31:0])
276675acc68SYinan Xu    def rolw       = "b001_1100".U
277675acc68SYinan Xu    def rorw       = "b001_1101".U
278675acc68SYinan Xu
279675acc68SYinan Xu    // ADD-op
280675acc68SYinan Xu    def adduw      = "b010_0000".U // adduw:  src1[31:0]  + src2
281675acc68SYinan Xu    def add        = "b010_0001".U // add:     src1        + src2
282675acc68SYinan Xu    def oddadd     = "b010_0010".U // oddadd:  src1[0]     + src2
283675acc68SYinan Xu
284675acc68SYinan Xu    def sr29add    = "b010_0100".U // sr29add: src1[63:29] + src2
285675acc68SYinan Xu    def sr30add    = "b010_0101".U // sr30add: src1[63:30] + src2
286675acc68SYinan Xu    def sr31add    = "b010_0110".U // sr31add: src1[63:31] + src2
287675acc68SYinan Xu    def sr32add    = "b010_0111".U // sr32add: src1[63:32] + src2
288675acc68SYinan Xu
289675acc68SYinan Xu    def sh1adduw   = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2
290675acc68SYinan Xu    def sh1add     = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2
291675acc68SYinan Xu    def sh2adduw   = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2
292675acc68SYinan Xu    def sh2add     = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2
293675acc68SYinan Xu    def sh3adduw   = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2
294675acc68SYinan Xu    def sh3add     = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2
295675acc68SYinan Xu    def sh4add     = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2
296675acc68SYinan Xu
297675acc68SYinan Xu    // SUB-op: src1 - src2
298675acc68SYinan Xu    def sub        = "b011_0000".U
299675acc68SYinan Xu    def sltu       = "b011_0001".U
300675acc68SYinan Xu    def slt        = "b011_0010".U
301675acc68SYinan Xu    def maxu       = "b011_0100".U
302675acc68SYinan Xu    def minu       = "b011_0101".U
303675acc68SYinan Xu    def max        = "b011_0110".U
304675acc68SYinan Xu    def min        = "b011_0111".U
305675acc68SYinan Xu
306675acc68SYinan Xu    // branch
307675acc68SYinan Xu    def beq        = "b111_0000".U
308675acc68SYinan Xu    def bne        = "b111_0010".U
309675acc68SYinan Xu    def blt        = "b111_1000".U
310675acc68SYinan Xu    def bge        = "b111_1010".U
311675acc68SYinan Xu    def bltu       = "b111_1100".U
312675acc68SYinan Xu    def bgeu       = "b111_1110".U
313675acc68SYinan Xu
314675acc68SYinan Xu    // misc optype
315675acc68SYinan Xu    def and        = "b100_0000".U
316675acc68SYinan Xu    def andn       = "b100_0001".U
317675acc68SYinan Xu    def or         = "b100_0010".U
318675acc68SYinan Xu    def orn        = "b100_0011".U
319675acc68SYinan Xu    def xor        = "b100_0100".U
320675acc68SYinan Xu    def xnor       = "b100_0101".U
321675acc68SYinan Xu    def orcb       = "b100_0110".U
322675acc68SYinan Xu
323675acc68SYinan Xu    def sextb      = "b100_1000".U
324675acc68SYinan Xu    def packh      = "b100_1001".U
325675acc68SYinan Xu    def sexth      = "b100_1010".U
326675acc68SYinan Xu    def packw      = "b100_1011".U
327675acc68SYinan Xu
328675acc68SYinan Xu    def revb       = "b101_0000".U
329675acc68SYinan Xu    def rev8       = "b101_0001".U
330675acc68SYinan Xu    def pack       = "b101_0010".U
331675acc68SYinan Xu    def orh48      = "b101_0011".U
332675acc68SYinan Xu
333675acc68SYinan Xu    def szewl1     = "b101_1000".U
334675acc68SYinan Xu    def szewl2     = "b101_1001".U
335675acc68SYinan Xu    def szewl3     = "b101_1010".U
336675acc68SYinan Xu    def byte2      = "b101_1011".U
337675acc68SYinan Xu
338675acc68SYinan Xu    def andlsb     = "b110_0000".U
339675acc68SYinan Xu    def andzexth   = "b110_0001".U
340675acc68SYinan Xu    def orlsb      = "b110_0010".U
341675acc68SYinan Xu    def orzexth    = "b110_0011".U
342675acc68SYinan Xu    def xorlsb     = "b110_0100".U
343675acc68SYinan Xu    def xorzexth   = "b110_0101".U
344675acc68SYinan Xu    def orcblsb    = "b110_0110".U
345675acc68SYinan Xu    def orcbzexth  = "b110_0111".U
346675acc68SYinan Xu
347675acc68SYinan Xu    def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1)
348675acc68SYinan Xu    def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0)
349675acc68SYinan Xu    def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W))
350675acc68SYinan Xu    def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W))
351675acc68SYinan Xu    def isBranch(func: UInt) = func(6, 4) === "b111".U
352675acc68SYinan Xu    def getBranchType(func: UInt) = func(3, 2)
353675acc68SYinan Xu    def isBranchInvert(func: UInt) = func(1)
354675acc68SYinan Xu
355675acc68SYinan Xu    def apply() = UInt(7.W)
3562225d46eSJiawei Lin  }
3572225d46eSJiawei Lin
3582225d46eSJiawei Lin  object MDUOpType {
3592225d46eSJiawei Lin    // mul
3602225d46eSJiawei Lin    // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) |
3612225d46eSJiawei Lin    def mul    = "b00000".U
3622225d46eSJiawei Lin    def mulh   = "b00001".U
3632225d46eSJiawei Lin    def mulhsu = "b00010".U
3642225d46eSJiawei Lin    def mulhu  = "b00011".U
3652225d46eSJiawei Lin    def mulw   = "b00100".U
3662225d46eSJiawei Lin
36788825c5cSYinan Xu    def mulw7  = "b01100".U
36888825c5cSYinan Xu
3692225d46eSJiawei Lin    // div
3702225d46eSJiawei Lin    // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) |
37188825c5cSYinan Xu    def div    = "b10000".U
37288825c5cSYinan Xu    def divu   = "b10010".U
37388825c5cSYinan Xu    def rem    = "b10001".U
37488825c5cSYinan Xu    def remu   = "b10011".U
3752225d46eSJiawei Lin
37688825c5cSYinan Xu    def divw   = "b10100".U
37788825c5cSYinan Xu    def divuw  = "b10110".U
37888825c5cSYinan Xu    def remw   = "b10101".U
37988825c5cSYinan Xu    def remuw  = "b10111".U
3802225d46eSJiawei Lin
38188825c5cSYinan Xu    def isMul(op: UInt) = !op(4)
38288825c5cSYinan Xu    def isDiv(op: UInt) = op(4)
3832225d46eSJiawei Lin
3842225d46eSJiawei Lin    def isDivSign(op: UInt) = isDiv(op) && !op(1)
3852225d46eSJiawei Lin    def isW(op: UInt) = op(2)
3862225d46eSJiawei Lin    def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U)
3872225d46eSJiawei Lin    def getMulOp(op: UInt) = op(1, 0)
3882225d46eSJiawei Lin  }
3892225d46eSJiawei Lin
3902225d46eSJiawei Lin  object LSUOpType {
391d200f594SWilliam Wang    // load pipeline
3922225d46eSJiawei Lin
393d200f594SWilliam Wang    // normal load
394d200f594SWilliam Wang    // Note: bit(1, 0) are size, DO NOT CHANGE
395d200f594SWilliam Wang    // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) |
396d200f594SWilliam Wang    def lb       = "b0000".U
397d200f594SWilliam Wang    def lh       = "b0001".U
398d200f594SWilliam Wang    def lw       = "b0010".U
399d200f594SWilliam Wang    def ld       = "b0011".U
400d200f594SWilliam Wang    def lbu      = "b0100".U
401d200f594SWilliam Wang    def lhu      = "b0101".U
402d200f594SWilliam Wang    def lwu      = "b0110".U
403ca18a0b4SWilliam Wang
404d200f594SWilliam Wang    // Zicbop software prefetch
405d200f594SWilliam Wang    // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) |
406d200f594SWilliam Wang    def prefetch_i = "b1000".U // TODO
407d200f594SWilliam Wang    def prefetch_r = "b1001".U
408d200f594SWilliam Wang    def prefetch_w = "b1010".U
409ca18a0b4SWilliam Wang
410d200f594SWilliam Wang    def isPrefetch(op: UInt): Bool = op(3)
411d200f594SWilliam Wang
412d200f594SWilliam Wang    // store pipeline
413d200f594SWilliam Wang    // normal store
414d200f594SWilliam Wang    // bit encoding: | store 00 | size(2bit) |
415d200f594SWilliam Wang    def sb       = "b0000".U
416d200f594SWilliam Wang    def sh       = "b0001".U
417d200f594SWilliam Wang    def sw       = "b0010".U
418d200f594SWilliam Wang    def sd       = "b0011".U
419d200f594SWilliam Wang
420d200f594SWilliam Wang    // l1 cache op
421d200f594SWilliam Wang    // bit encoding: | cbo_zero 01 | size(2bit) 11 |
422d200f594SWilliam Wang    def cbo_zero  = "b0111".U
423d200f594SWilliam Wang
424d200f594SWilliam Wang    // llc op
425d200f594SWilliam Wang    // bit encoding: | prefetch 11 | suboptype(2bit) |
426d200f594SWilliam Wang    def cbo_clean = "b1100".U
427d200f594SWilliam Wang    def cbo_flush = "b1101".U
428d200f594SWilliam Wang    def cbo_inval = "b1110".U
429d200f594SWilliam Wang
430d200f594SWilliam Wang    def isCbo(op: UInt): Bool = op(3, 2) === "b11".U
4312225d46eSJiawei Lin
4322225d46eSJiawei Lin    // atomics
4332225d46eSJiawei Lin    // bit(1, 0) are size
4342225d46eSJiawei Lin    // since atomics use a different fu type
4352225d46eSJiawei Lin    // so we can safely reuse other load/store's encodings
436d200f594SWilliam Wang    // bit encoding: | optype(4bit) | size (2bit) |
4372225d46eSJiawei Lin    def lr_w      = "b000010".U
4382225d46eSJiawei Lin    def sc_w      = "b000110".U
4392225d46eSJiawei Lin    def amoswap_w = "b001010".U
4402225d46eSJiawei Lin    def amoadd_w  = "b001110".U
4412225d46eSJiawei Lin    def amoxor_w  = "b010010".U
4422225d46eSJiawei Lin    def amoand_w  = "b010110".U
4432225d46eSJiawei Lin    def amoor_w   = "b011010".U
4442225d46eSJiawei Lin    def amomin_w  = "b011110".U
4452225d46eSJiawei Lin    def amomax_w  = "b100010".U
4462225d46eSJiawei Lin    def amominu_w = "b100110".U
4472225d46eSJiawei Lin    def amomaxu_w = "b101010".U
4482225d46eSJiawei Lin
4492225d46eSJiawei Lin    def lr_d      = "b000011".U
4502225d46eSJiawei Lin    def sc_d      = "b000111".U
4512225d46eSJiawei Lin    def amoswap_d = "b001011".U
4522225d46eSJiawei Lin    def amoadd_d  = "b001111".U
4532225d46eSJiawei Lin    def amoxor_d  = "b010011".U
4542225d46eSJiawei Lin    def amoand_d  = "b010111".U
4552225d46eSJiawei Lin    def amoor_d   = "b011011".U
4562225d46eSJiawei Lin    def amomin_d  = "b011111".U
4572225d46eSJiawei Lin    def amomax_d  = "b100011".U
4582225d46eSJiawei Lin    def amominu_d = "b100111".U
4592225d46eSJiawei Lin    def amomaxu_d = "b101011".U
460b6982e83SLemover
461b6982e83SLemover    def size(op: UInt) = op(1,0)
4622225d46eSJiawei Lin  }
4632225d46eSJiawei Lin
4643feeca58Szfw  object BKUOpType {
465ee8ff153Szfw
4663feeca58Szfw    def clmul       = "b000000".U
4673feeca58Szfw    def clmulh      = "b000001".U
4683feeca58Szfw    def clmulr      = "b000010".U
4693feeca58Szfw    def xpermn      = "b000100".U
4703feeca58Szfw    def xpermb      = "b000101".U
471ee8ff153Szfw
4723feeca58Szfw    def clz         = "b001000".U
4733feeca58Szfw    def clzw        = "b001001".U
4743feeca58Szfw    def ctz         = "b001010".U
4753feeca58Szfw    def ctzw        = "b001011".U
4763feeca58Szfw    def cpop        = "b001100".U
4773feeca58Szfw    def cpopw       = "b001101".U
47807596dc6Szfw
4793feeca58Szfw    // 01xxxx is reserve
4803feeca58Szfw    def aes64es     = "b100000".U
4813feeca58Szfw    def aes64esm    = "b100001".U
4823feeca58Szfw    def aes64ds     = "b100010".U
4833feeca58Szfw    def aes64dsm    = "b100011".U
4843feeca58Szfw    def aes64im     = "b100100".U
4853feeca58Szfw    def aes64ks1i   = "b100101".U
4863feeca58Szfw    def aes64ks2    = "b100110".U
4873feeca58Szfw
4883feeca58Szfw    // merge to two instruction sm4ks & sm4ed
48919bcce38SFawang Zhang    def sm4ed0      = "b101000".U
49019bcce38SFawang Zhang    def sm4ed1      = "b101001".U
49119bcce38SFawang Zhang    def sm4ed2      = "b101010".U
49219bcce38SFawang Zhang    def sm4ed3      = "b101011".U
49319bcce38SFawang Zhang    def sm4ks0      = "b101100".U
49419bcce38SFawang Zhang    def sm4ks1      = "b101101".U
49519bcce38SFawang Zhang    def sm4ks2      = "b101110".U
49619bcce38SFawang Zhang    def sm4ks3      = "b101111".U
4973feeca58Szfw
4983feeca58Szfw    def sha256sum0  = "b110000".U
4993feeca58Szfw    def sha256sum1  = "b110001".U
5003feeca58Szfw    def sha256sig0  = "b110010".U
5013feeca58Szfw    def sha256sig1  = "b110011".U
5023feeca58Szfw    def sha512sum0  = "b110100".U
5033feeca58Szfw    def sha512sum1  = "b110101".U
5043feeca58Szfw    def sha512sig0  = "b110110".U
5053feeca58Szfw    def sha512sig1  = "b110111".U
5063feeca58Szfw
5073feeca58Szfw    def sm3p0       = "b111000".U
5083feeca58Szfw    def sm3p1       = "b111001".U
509ee8ff153Szfw  }
510ee8ff153Szfw
5112225d46eSJiawei Lin  object BTBtype {
5122225d46eSJiawei Lin    def B = "b00".U  // branch
5132225d46eSJiawei Lin    def J = "b01".U  // jump
5142225d46eSJiawei Lin    def I = "b10".U  // indirect
5152225d46eSJiawei Lin    def R = "b11".U  // return
5162225d46eSJiawei Lin
5172225d46eSJiawei Lin    def apply() = UInt(2.W)
5182225d46eSJiawei Lin  }
5192225d46eSJiawei Lin
5202225d46eSJiawei Lin  object SelImm {
521ee8ff153Szfw    def IMM_X  = "b0111".U
522ee8ff153Szfw    def IMM_S  = "b0000".U
523ee8ff153Szfw    def IMM_SB = "b0001".U
524ee8ff153Szfw    def IMM_U  = "b0010".U
525ee8ff153Szfw    def IMM_UJ = "b0011".U
526ee8ff153Szfw    def IMM_I  = "b0100".U
527ee8ff153Szfw    def IMM_Z  = "b0101".U
528ee8ff153Szfw    def INVALID_INSTR = "b0110".U
529ee8ff153Szfw    def IMM_B6 = "b1000".U
5302225d46eSJiawei Lin
5316e7c9679Shuxuan0307    def X      = BitPat("b????")
5326e7c9679Shuxuan0307
533ee8ff153Szfw    def apply() = UInt(4.W)
5342225d46eSJiawei Lin  }
5352225d46eSJiawei Lin
5366ab6918fSYinan Xu  object ExceptionNO {
5376ab6918fSYinan Xu    def instrAddrMisaligned = 0
5386ab6918fSYinan Xu    def instrAccessFault    = 1
5396ab6918fSYinan Xu    def illegalInstr        = 2
5406ab6918fSYinan Xu    def breakPoint          = 3
5416ab6918fSYinan Xu    def loadAddrMisaligned  = 4
5426ab6918fSYinan Xu    def loadAccessFault     = 5
5436ab6918fSYinan Xu    def storeAddrMisaligned = 6
5446ab6918fSYinan Xu    def storeAccessFault    = 7
5456ab6918fSYinan Xu    def ecallU              = 8
5466ab6918fSYinan Xu    def ecallS              = 9
5476ab6918fSYinan Xu    def ecallM              = 11
5486ab6918fSYinan Xu    def instrPageFault      = 12
5496ab6918fSYinan Xu    def loadPageFault       = 13
5506ab6918fSYinan Xu    // def singleStep          = 14
5516ab6918fSYinan Xu    def storePageFault      = 15
5526ab6918fSYinan Xu    def priorities = Seq(
5536ab6918fSYinan Xu      breakPoint, // TODO: different BP has different priority
5546ab6918fSYinan Xu      instrPageFault,
5556ab6918fSYinan Xu      instrAccessFault,
5566ab6918fSYinan Xu      illegalInstr,
5576ab6918fSYinan Xu      instrAddrMisaligned,
5586ab6918fSYinan Xu      ecallM, ecallS, ecallU,
559d880177dSYinan Xu      storeAddrMisaligned,
560d880177dSYinan Xu      loadAddrMisaligned,
5616ab6918fSYinan Xu      storePageFault,
5626ab6918fSYinan Xu      loadPageFault,
5636ab6918fSYinan Xu      storeAccessFault,
564d880177dSYinan Xu      loadAccessFault
5656ab6918fSYinan Xu    )
5666ab6918fSYinan Xu    def all = priorities.distinct.sorted
5676ab6918fSYinan Xu    def frontendSet = Seq(
5686ab6918fSYinan Xu      instrAddrMisaligned,
5696ab6918fSYinan Xu      instrAccessFault,
5706ab6918fSYinan Xu      illegalInstr,
5716ab6918fSYinan Xu      instrPageFault
5726ab6918fSYinan Xu    )
5736ab6918fSYinan Xu    def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = {
5746ab6918fSYinan Xu      val new_vec = Wire(ExceptionVec())
5756ab6918fSYinan Xu      new_vec.foreach(_ := false.B)
5766ab6918fSYinan Xu      select.foreach(i => new_vec(i) := vec(i))
5776ab6918fSYinan Xu      new_vec
5786ab6918fSYinan Xu    }
5796ab6918fSYinan Xu    def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet)
5806ab6918fSYinan Xu    def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all)
5816ab6918fSYinan Xu    def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] =
5826ab6918fSYinan Xu      partialSelect(vec, fuConfig.exceptionOut)
5836ab6918fSYinan Xu    def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] =
5846ab6918fSYinan Xu      partialSelect(vec, exuConfig.exceptionOut)
5856ab6918fSYinan Xu    def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] =
5866ab6918fSYinan Xu      partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted)
5876ab6918fSYinan Xu  }
5886ab6918fSYinan Xu
5891c62c387SYinan Xu  def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p)
590c3d7991bSJiawei Lin  def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p)
5912225d46eSJiawei Lin  def aluGen(p: Parameters) = new Alu()(p)
5923feeca58Szfw  def bkuGen(p: Parameters) = new Bku()(p)
5932225d46eSJiawei Lin  def jmpGen(p: Parameters) = new Jump()(p)
5942225d46eSJiawei Lin  def fenceGen(p: Parameters) = new Fence()(p)
5952225d46eSJiawei Lin  def csrGen(p: Parameters) = new CSR()(p)
5962225d46eSJiawei Lin  def i2fGen(p: Parameters) = new IntToFP()(p)
5972225d46eSJiawei Lin  def fmacGen(p: Parameters) = new FMA()(p)
5982225d46eSJiawei Lin  def f2iGen(p: Parameters) = new FPToInt()(p)
5992225d46eSJiawei Lin  def f2fGen(p: Parameters) = new FPToFP()(p)
6002225d46eSJiawei Lin  def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p)
60185b4cd54SYinan Xu  def stdGen(p: Parameters) = new Std()(p)
6026ab6918fSYinan Xu  def mouDataGen(p: Parameters) = new Std()(p)
6036827759bSZhangZifei  def vipuGen(p: Parameters) = new VIPU()(p)
6042225d46eSJiawei Lin
6056cdd85d9SYinan Xu  def f2iSel(uop: MicroOp): Bool = {
6066cdd85d9SYinan Xu    uop.ctrl.rfWen
6072225d46eSJiawei Lin  }
6082225d46eSJiawei Lin
6096cdd85d9SYinan Xu  def i2fSel(uop: MicroOp): Bool = {
6106cdd85d9SYinan Xu    uop.ctrl.fpu.fromInt
6112225d46eSJiawei Lin  }
6122225d46eSJiawei Lin
6136cdd85d9SYinan Xu  def f2fSel(uop: MicroOp): Bool = {
6146cdd85d9SYinan Xu    val ctrl = uop.ctrl.fpu
6152225d46eSJiawei Lin    ctrl.fpWen && !ctrl.div && !ctrl.sqrt
6162225d46eSJiawei Lin  }
6172225d46eSJiawei Lin
6186cdd85d9SYinan Xu  def fdivSqrtSel(uop: MicroOp): Bool = {
6196cdd85d9SYinan Xu    val ctrl = uop.ctrl.fpu
6202225d46eSJiawei Lin    ctrl.div || ctrl.sqrt
6212225d46eSJiawei Lin  }
6222225d46eSJiawei Lin
6232225d46eSJiawei Lin  val aluCfg = FuConfig(
6241a0f06eeSYinan Xu    name = "alu",
6252225d46eSJiawei Lin    fuGen = aluGen,
6266cdd85d9SYinan Xu    fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu,
6272225d46eSJiawei Lin    fuType = FuType.alu,
6282225d46eSJiawei Lin    numIntSrc = 2,
6292225d46eSJiawei Lin    numFpSrc = 0,
6302225d46eSJiawei Lin    writeIntRf = true,
6312225d46eSJiawei Lin    writeFpRf = false,
6322225d46eSJiawei Lin    hasRedirect = true,
6332225d46eSJiawei Lin  )
6342225d46eSJiawei Lin
6352225d46eSJiawei Lin  val jmpCfg = FuConfig(
6361a0f06eeSYinan Xu    name = "jmp",
6372225d46eSJiawei Lin    fuGen = jmpGen,
6386cdd85d9SYinan Xu    fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp,
6392225d46eSJiawei Lin    fuType = FuType.jmp,
6402225d46eSJiawei Lin    numIntSrc = 1,
6412225d46eSJiawei Lin    numFpSrc = 0,
6422225d46eSJiawei Lin    writeIntRf = true,
6432225d46eSJiawei Lin    writeFpRf = false,
6442225d46eSJiawei Lin    hasRedirect = true,
6452225d46eSJiawei Lin  )
6462225d46eSJiawei Lin
6472225d46eSJiawei Lin  val fenceCfg = FuConfig(
6481a0f06eeSYinan Xu    name = "fence",
6492225d46eSJiawei Lin    fuGen = fenceGen,
6506cdd85d9SYinan Xu    fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence,
6516ab6918fSYinan Xu    FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false,
652f1fe8698SLemover    latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value,
653f1fe8698SLemover    flushPipe = true
6542225d46eSJiawei Lin  )
6552225d46eSJiawei Lin
6562225d46eSJiawei Lin  val csrCfg = FuConfig(
6571a0f06eeSYinan Xu    name = "csr",
6582225d46eSJiawei Lin    fuGen = csrGen,
6596cdd85d9SYinan Xu    fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr,
6602225d46eSJiawei Lin    fuType = FuType.csr,
6612225d46eSJiawei Lin    numIntSrc = 1,
6622225d46eSJiawei Lin    numFpSrc = 0,
6632225d46eSJiawei Lin    writeIntRf = true,
6642225d46eSJiawei Lin    writeFpRf = false,
6656ab6918fSYinan Xu    exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM),
6666ab6918fSYinan Xu    flushPipe = true
6672225d46eSJiawei Lin  )
6682225d46eSJiawei Lin
6692225d46eSJiawei Lin  val i2fCfg = FuConfig(
6701a0f06eeSYinan Xu    name = "i2f",
6712225d46eSJiawei Lin    fuGen = i2fGen,
6722225d46eSJiawei Lin    fuSel = i2fSel,
6732225d46eSJiawei Lin    FuType.i2f,
6742225d46eSJiawei Lin    numIntSrc = 1,
6752225d46eSJiawei Lin    numFpSrc = 0,
6762225d46eSJiawei Lin    writeIntRf = false,
6772225d46eSJiawei Lin    writeFpRf = true,
6786ab6918fSYinan Xu    writeFflags = true,
679e174d629SJiawei Lin    latency = CertainLatency(2),
680e174d629SJiawei Lin    fastUopOut = true, fastImplemented = true
6812225d46eSJiawei Lin  )
6822225d46eSJiawei Lin
6832225d46eSJiawei Lin  val divCfg = FuConfig(
6841a0f06eeSYinan Xu    name = "div",
6852225d46eSJiawei Lin    fuGen = dividerGen,
68607596dc6Szfw    fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div,
6872225d46eSJiawei Lin    FuType.div,
6882225d46eSJiawei Lin    2,
6892225d46eSJiawei Lin    0,
6902225d46eSJiawei Lin    writeIntRf = true,
6912225d46eSJiawei Lin    writeFpRf = false,
692f83b578aSYinan Xu    latency = UncertainLatency(),
693f83b578aSYinan Xu    fastUopOut = true,
6941c62c387SYinan Xu    fastImplemented = true,
6955ee7cabeSYinan Xu    hasInputBuffer = (true, 4, true)
6962225d46eSJiawei Lin  )
6972225d46eSJiawei Lin
6982225d46eSJiawei Lin  val mulCfg = FuConfig(
6991a0f06eeSYinan Xu    name = "mul",
7002225d46eSJiawei Lin    fuGen = multiplierGen,
70107596dc6Szfw    fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul,
7022225d46eSJiawei Lin    FuType.mul,
7032225d46eSJiawei Lin    2,
7042225d46eSJiawei Lin    0,
7052225d46eSJiawei Lin    writeIntRf = true,
7062225d46eSJiawei Lin    writeFpRf = false,
707b2482bc1SYinan Xu    latency = CertainLatency(2),
708f83b578aSYinan Xu    fastUopOut = true,
709b2482bc1SYinan Xu    fastImplemented = true
7102225d46eSJiawei Lin  )
7112225d46eSJiawei Lin
7123feeca58Szfw  val bkuCfg = FuConfig(
7133feeca58Szfw    name = "bku",
7143feeca58Szfw    fuGen = bkuGen,
7153feeca58Szfw    fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku,
7163feeca58Szfw    fuType = FuType.bku,
717ee8ff153Szfw    numIntSrc = 2,
718ee8ff153Szfw    numFpSrc = 0,
719ee8ff153Szfw    writeIntRf = true,
720ee8ff153Szfw    writeFpRf = false,
721f83b578aSYinan Xu    latency = CertainLatency(1),
722f83b578aSYinan Xu    fastUopOut = true,
72307596dc6Szfw    fastImplemented = true
724ee8ff153Szfw )
725ee8ff153Szfw
7262225d46eSJiawei Lin  val fmacCfg = FuConfig(
7271a0f06eeSYinan Xu    name = "fmac",
7282225d46eSJiawei Lin    fuGen = fmacGen,
7292225d46eSJiawei Lin    fuSel = _ => true.B,
7306ab6918fSYinan Xu    FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true,
7314b65fc7eSJiawei Lin    latency = UncertainLatency(), fastUopOut = true, fastImplemented = true
7322225d46eSJiawei Lin  )
7332225d46eSJiawei Lin
7342225d46eSJiawei Lin  val f2iCfg = FuConfig(
7351a0f06eeSYinan Xu    name = "f2i",
7362225d46eSJiawei Lin    fuGen = f2iGen,
7372225d46eSJiawei Lin    fuSel = f2iSel,
7386ab6918fSYinan Xu    FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2),
739b2482bc1SYinan Xu    fastUopOut = true, fastImplemented = true
7402225d46eSJiawei Lin  )
7412225d46eSJiawei Lin
7422225d46eSJiawei Lin  val f2fCfg = FuConfig(
7431a0f06eeSYinan Xu    name = "f2f",
7442225d46eSJiawei Lin    fuGen = f2fGen,
7452225d46eSJiawei Lin    fuSel = f2fSel,
7466ab6918fSYinan Xu    FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2),
747b2482bc1SYinan Xu    fastUopOut = true, fastImplemented = true
7482225d46eSJiawei Lin  )
7492225d46eSJiawei Lin
7502225d46eSJiawei Lin  val fdivSqrtCfg = FuConfig(
7511a0f06eeSYinan Xu    name = "fdivSqrt",
7522225d46eSJiawei Lin    fuGen = fdivSqrtGen,
7532225d46eSJiawei Lin    fuSel = fdivSqrtSel,
7546ab6918fSYinan Xu    FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(),
755140aff85SYinan Xu    fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true)
7562225d46eSJiawei Lin  )
7572225d46eSJiawei Lin
7582225d46eSJiawei Lin  val lduCfg = FuConfig(
7591a0f06eeSYinan Xu    "ldu",
7602225d46eSJiawei Lin    null, // DontCare
7612b4e8253SYinan Xu    (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType),
7626ab6918fSYinan Xu    FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true,
7636ab6918fSYinan Xu    latency = UncertainLatency(),
7646ab6918fSYinan Xu    exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault),
7656ab6918fSYinan Xu    flushPipe = true,
7666786cfb7SWilliam Wang    replayInst = true,
7676786cfb7SWilliam Wang    hasLoadError = true
7682225d46eSJiawei Lin  )
7692225d46eSJiawei Lin
77085b4cd54SYinan Xu  val staCfg = FuConfig(
7711a0f06eeSYinan Xu    "sta",
7722225d46eSJiawei Lin    null,
7732b4e8253SYinan Xu    (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType),
7746ab6918fSYinan Xu    FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false,
7756ab6918fSYinan Xu    latency = UncertainLatency(),
7766ab6918fSYinan Xu    exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault)
7772225d46eSJiawei Lin  )
7782225d46eSJiawei Lin
77985b4cd54SYinan Xu  val stdCfg = FuConfig(
7801a0f06eeSYinan Xu    "std",
7812b4e8253SYinan Xu    fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1,
7826ab6918fSYinan Xu    writeIntRf = false, writeFpRf = false, latency = CertainLatency(1)
78385b4cd54SYinan Xu  )
78485b4cd54SYinan Xu
7852225d46eSJiawei Lin  val mouCfg = FuConfig(
7861a0f06eeSYinan Xu    "mou",
7872225d46eSJiawei Lin    null,
7882b4e8253SYinan Xu    (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType),
7896ab6918fSYinan Xu    FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false,
7906ab6918fSYinan Xu    latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut
7912b4e8253SYinan Xu  )
7922b4e8253SYinan Xu
7932b4e8253SYinan Xu  val mouDataCfg = FuConfig(
7942b4e8253SYinan Xu    "mou",
7952b4e8253SYinan Xu    mouDataGen,
7962b4e8253SYinan Xu    (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType),
7976ab6918fSYinan Xu    FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false,
7986ab6918fSYinan Xu    latency = UncertainLatency()
7992225d46eSJiawei Lin  )
8002225d46eSJiawei Lin
8016827759bSZhangZifei  val vipuCfg = FuConfig(
8026827759bSZhangZifei    name = "vipu",
8036827759bSZhangZifei    fuGen = vipuGen,
8046827759bSZhangZifei    fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType,
8056827759bSZhangZifei    fuType = FuType.vipu,
8066827759bSZhangZifei    numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false,
8076827759bSZhangZifei    numVecSrc = 2, writeVecRf = true,
8086827759bSZhangZifei    fastUopOut = true, // TODO: check
8096827759bSZhangZifei    fastImplemented = true, //TODO: check
8106827759bSZhangZifei  )
8116827759bSZhangZifei
812adb5df20SYinan Xu  val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue)
813b6220f0dSLemover  val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue)
814adb5df20SYinan Xu  val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue)
8153feeca58Szfw  val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue)
8166827759bSZhangZifei  val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg, vipuCfg), Int.MaxValue, 0)
8172225d46eSJiawei Lin  val FmiscExeUnitCfg = ExuConfig(
8182225d46eSJiawei Lin    "FmiscExeUnit",
819b6220f0dSLemover    "Fp",
8202225d46eSJiawei Lin    Seq(f2iCfg, f2fCfg, fdivSqrtCfg),
8212225d46eSJiawei Lin    Int.MaxValue, 1
8222225d46eSJiawei Lin  )
8232b4e8253SYinan Xu  val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false)
8242b4e8253SYinan Xu  val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false)
8252b4e8253SYinan Xu  val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false)
82654034ccdSZhangZifei
827d16f4ea4SZhangZifei  // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p)
828d16f4ea4SZhangZifei  // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p)
829d16f4ea4SZhangZifei  // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p)
830d16f4ea4SZhangZifei  // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p)
831d16f4ea4SZhangZifei  // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p)
832d16f4ea4SZhangZifei  // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p)
833d16f4ea4SZhangZifei  // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p)
83454034ccdSZhangZifei
835d16f4ea4SZhangZifei  val aluRSMod = new RSMod(
836d16f4ea4SZhangZifei    rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p),
837d16f4ea4SZhangZifei    rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b),
838d16f4ea4SZhangZifei    immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p)
839d16f4ea4SZhangZifei  )
840d16f4ea4SZhangZifei  val fmaRSMod = new RSMod(
841d16f4ea4SZhangZifei    rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p),
842d16f4ea4SZhangZifei    rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b),
843d16f4ea4SZhangZifei  )
844d16f4ea4SZhangZifei  val fmiscRSMod = new RSMod(
845d16f4ea4SZhangZifei    rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p),
846d16f4ea4SZhangZifei    rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b),
847d16f4ea4SZhangZifei  )
848d16f4ea4SZhangZifei  val jumpRSMod = new RSMod(
849d16f4ea4SZhangZifei    rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p),
850d16f4ea4SZhangZifei    rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b),
851d16f4ea4SZhangZifei    immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p)
852d16f4ea4SZhangZifei  )
853d16f4ea4SZhangZifei  val loadRSMod = new RSMod(
854d16f4ea4SZhangZifei    rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p),
855d16f4ea4SZhangZifei    rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b),
856d16f4ea4SZhangZifei    immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p)
857d16f4ea4SZhangZifei  )
858d16f4ea4SZhangZifei  val mulRSMod = new RSMod(
859d16f4ea4SZhangZifei    rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p),
860d16f4ea4SZhangZifei    rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b),
861d16f4ea4SZhangZifei    immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p)
862d16f4ea4SZhangZifei  )
863d16f4ea4SZhangZifei  val staRSMod = new RSMod(
864d16f4ea4SZhangZifei    rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p),
865d16f4ea4SZhangZifei    rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b),
866d16f4ea4SZhangZifei  )
867d16f4ea4SZhangZifei  val stdRSMod = new RSMod(
868d16f4ea4SZhangZifei    rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p),
869d16f4ea4SZhangZifei    rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b),
870d16f4ea4SZhangZifei  )
8719a2e6b8aSLinJiawei}
872