1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.Bundles._ 27import xiangshan.mem._ 28import xiangshan.backend.fu.vector.Bundles._ 29 30 31class VSplitPipeline(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 32 val io = IO(new VSplitPipelineIO(isVStore)) 33 34 def us_whole_reg(fuOpType: UInt) = fuOpType === VlduType.vlr 35 def us_mask(fuOpType: UInt) = fuOpType === VlduType.vlm 36 def us_fof(fuOpType: UInt) = fuOpType === VlduType.vleff 37 38 val s1_ready = WireInit(false.B) 39 io.in.ready := s1_ready 40 41 /**----------------------------------------------------------- 42 * s0 stage 43 * decode and generate AlignedType, uop mask, preIsSplit 44 * ---------------------------------------------------------- 45 */ 46 val s0_vtype = io.in.bits.uop.vpu.vtype 47 val s0_sew = s0_vtype.vsew 48 val s0_eew = io.in.bits.uop.vpu.veew 49 val s0_lmul = s0_vtype.vlmul 50 // when load whole register or unit-stride masked , emul should be 1 51 val s0_fuOpType = io.in.bits.uop.fuOpType 52 val s0_mop = s0_fuOpType(6, 5) 53 val s0_nf = Mux(us_whole_reg(s0_fuOpType), 0.U, io.in.bits.uop.vpu.nf) 54 val s0_vm = io.in.bits.uop.vpu.vm 55 val s0_emul = Mux(us_whole_reg(s0_fuOpType) ,GenUSWholeEmul(io.in.bits.uop.vpu.nf), Mux(us_mask(s0_fuOpType), 0.U(mulBits.W), EewLog2(s0_eew) - s0_sew + s0_lmul)) 56 val s0_preIsSplit = !(isUnitStride(s0_mop) && !us_fof(s0_fuOpType)) 57 58 val s0_valid = Wire(Bool()) 59 val s0_kill = io.in.bits.uop.robIdx.needFlush(io.redirect) 60 val s0_can_go = s1_ready 61 val s0_fire = s0_valid && s0_can_go 62 val s0_out = Wire(new VLSBundle(isVStore)) 63 64 val isUsWholeReg = isUnitStride(s0_mop) && us_whole_reg(s0_fuOpType) 65 val isMaskReg = isUnitStride(s0_mop) && us_mask(s0_fuOpType) 66 val isSegment = s0_nf =/= 0.U && !us_whole_reg(s0_fuOpType) 67 val instType = Cat(isSegment, s0_mop) 68 val uopIdx = io.in.bits.uop.vpu.vuopIdx 69 val uopIdxInField = GenUopIdxInField(instType, s0_emul, s0_lmul, uopIdx) 70 val vdIdxInField = GenVdIdxInField(instType, s0_emul, s0_lmul, uopIdxInField) 71 val lmulLog2 = Mux(s0_lmul.asSInt >= 0.S, 0.U, s0_lmul) 72 val emulLog2 = Mux(s0_emul.asSInt >= 0.S, 0.U, s0_emul) 73 val numEewLog2 = emulLog2 - EewLog2(s0_eew) 74 val numSewLog2 = lmulLog2 - s0_sew 75 val numFlowsSameVdLog2 = Mux( 76 isIndexed(instType), 77 log2Up(VLENB).U - s0_sew(1,0), 78 log2Up(VLENB).U - s0_eew(1,0) 79 ) 80 // numUops = nf * max(lmul, emul) 81 val lmulLog2Pos = Mux(s0_lmul.asSInt < 0.S, 0.U, s0_lmul) 82 val emulLog2Pos = Mux(s0_emul.asSInt < 0.S, 0.U, s0_emul) 83 val numUops = Mux( 84 isIndexed(s0_mop) && s0_lmul.asSInt > s0_emul.asSInt, 85 (s0_nf +& 1.U) << lmulLog2Pos, 86 (s0_nf +& 1.U) << emulLog2Pos 87 ) 88 89 val vvl = io.in.bits.src_vl.asTypeOf(VConfig()).vl 90 val evl = Mux(isUsWholeReg, GenUSWholeRegVL(io.in.bits.uop.vpu.nf +& 1.U,s0_eew), Mux(isMaskReg, GenUSMaskRegVL(vvl), vvl)) 91 val vvstart = io.in.bits.uop.vpu.vstart 92 val alignedType = Mux(isIndexed(instType), s0_sew(1, 0), s0_eew(1, 0)) 93 val broadenAligendType = Mux(s0_preIsSplit, Cat("b0".U, alignedType), "b100".U) // if is unit-stride, use 128-bits memory access 94 val flowsLog2 = GenRealFlowLog2(instType, s0_emul, s0_lmul, s0_eew, s0_sew) 95 val flowsPrevThisUop = uopIdxInField << flowsLog2 // # of flows before this uop in a field 96 val flowsPrevThisVd = vdIdxInField << numFlowsSameVdLog2 // # of flows before this vd in a field 97 val flowsIncludeThisUop = (uopIdxInField +& 1.U) << flowsLog2 // # of flows before this uop besides this uop 98 val flowNum = io.in.bits.flowNum.get 99 val srcMask = GenFlowMask(Mux(s0_vm, Fill(VLEN, 1.U(1.W)), io.in.bits.src_mask), vvstart, evl, true) 100 101 val flowMask = ((srcMask & 102 UIntToMask(flowsIncludeThisUop.asUInt, VLEN + 1) & 103 (~UIntToMask(flowsPrevThisUop.asUInt, VLEN)).asUInt 104 ) >> flowsPrevThisVd)(VLENB - 1, 0) 105 val vlmax = GenVLMAX(s0_lmul, s0_sew) 106 107 // connect 108 s0_out := DontCare 109 s0_out match {case x => 110 x.uop := io.in.bits.uop 111 x.uop.vpu.vl := evl 112 x.uop.uopIdx := uopIdx 113 x.uop.numUops := numUops 114 x.uop.lastUop := (uopIdx +& 1.U) === numUops 115 x.uop.vpu.nf := s0_nf 116 x.flowMask := flowMask 117 x.byteMask := GenUopByteMask(flowMask, Cat("b0".U, alignedType))(VLENB - 1, 0) 118 x.fof := isUnitStride(s0_mop) && us_fof(s0_fuOpType) 119 x.baseAddr := io.in.bits.src_rs1 120 x.stride := io.in.bits.src_stride 121 x.flowNum := flowNum 122 x.nfields := s0_nf +& 1.U 123 x.vm := s0_vm 124 x.usWholeReg := isUsWholeReg 125 x.usMaskReg := isMaskReg 126 x.eew := s0_eew 127 x.sew := s0_sew 128 x.emul := s0_emul 129 x.lmul := s0_lmul 130 x.vlmax := Mux(isUsWholeReg, evl, vlmax) 131 x.instType := instType 132 x.data := io.in.bits.src_vs3 133 x.vdIdxInField := vdIdxInField 134 x.preIsSplit := s0_preIsSplit 135 x.alignedType := broadenAligendType 136 } 137 s0_valid := io.in.valid && !s0_kill 138 /**------------------------------------- 139 * s1 stage 140 * ------------------------------------ 141 * generate UopOffset 142 */ 143 val s1_valid = RegInit(false.B) 144 val s1_kill = Wire(Bool()) 145 val s1_in = Wire(new VLSBundle(isVStore)) 146 val s1_can_go = io.out.ready && io.toMergeBuffer.resp.valid 147 val s1_fire = s1_valid && !s1_kill && s1_can_go 148 149 s1_ready := s1_kill || !s1_valid || io.out.ready 150 151 when(s0_fire){ 152 s1_valid := true.B 153 }.elsewhen(s1_fire){ 154 s1_valid := false.B 155 }.elsewhen(s1_kill){ 156 s1_valid := false.B 157 } 158 s1_in := RegEnable(s0_out, s0_fire) 159 160 val s1_uopidx = s1_in.uop.vpu.vuopIdx 161 val s1_nf = s1_in.uop.vpu.nf 162 val s1_nfields = s1_in.nfields 163 val s1_eew = s1_in.eew 164 val s1_instType = s1_in.instType 165 val s1_stride = s1_in.stride 166 val s1_vmask = FillInterleaved(8, s1_in.byteMask)(VLEN-1, 0) 167 val s1_alignedType = s1_in.alignedType 168 val s1_notIndexedStride = Mux( // stride for strided/unit-stride instruction 169 isStrided(s1_instType), 170 s1_stride(XLEN - 1, 0), // for strided load, stride = x[rs2] 171 s1_nfields << s1_eew(1, 0) // for unit-stride load, stride = eew * NFIELDS 172 ) 173 val uopOffset = (s1_uopidx >> s1_nf) << s1_alignedType 174 val stride = Mux(isIndexed(s1_instType), s1_stride, s1_notIndexedStride) // if is index instructions, get index when split 175 176 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) 177 178 // query mergeBuffer 179 io.toMergeBuffer.req.valid := s1_fire // only can_go will get MergeBuffer entry 180 io.toMergeBuffer.req.bits.flowNum := Mux(s1_in.preIsSplit, PopCount(s1_in.flowMask), flowNum) 181 io.toMergeBuffer.req.bits.data := s1_in.data 182 io.toMergeBuffer.req.bits.uop := s1_in.uop 183 io.toMergeBuffer.req.bits.uop.vpu.vmask:= s1_vmask 184 io.toMergeBuffer.req.bits.mask := flowMask 185 io.toMergeBuffer.req.bits.vaddr := DontCare 186// io.toMergeBuffer.req.bits.vdOffset := 187 188 // out connect 189 io.out.valid := s1_valid 190 io.out.bits := s1_in 191 io.out.bits.uopOffset := uopOffset 192 io.out.bits.stride := stride 193 io.out.bits.mBIndex := io.toMergeBuffer.resp.bits.mBIndex 194} 195 196abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 197 val io = IO(new VSplitBufferIO(isVStore)) 198 199 val bufferSize: Int 200 201 class VSplitPtr(implicit p: Parameters) extends CircularQueuePtr[VSplitPtr](bufferSize){ 202 } 203 204 object VSplitPtr { 205 def apply(f: Bool, v: UInt)(implicit p: Parameters): VSplitPtr = { 206 val ptr = Wire(new VSplitPtr) 207 ptr.flag := f 208 ptr.value := v 209 ptr 210 } 211 } 212 213 val uopq = Reg(Vec(bufferSize, new VLSBundle(isVStore))) 214 val valid = RegInit(VecInit(Seq.fill(bufferSize)(false.B))) 215 val vstart = RegInit(VecInit(Seq.fill(bufferSize)(0.U(elemIdxBits.W)))) // index of the exception element 216 val vl = RegInit(VecInit(Seq.fill(bufferSize)(0.U.asTypeOf(Valid(UInt(elemIdxBits.W)))))) // only for fof instructions that modify vl 217 val srcMaskVec = Reg(Vec(bufferSize, UInt(VLEN.W))) 218 // ptr 219 val enqPtr = RegInit(0.U.asTypeOf(new VSplitPtr)) 220 val deqPtr = RegInit(0.U.asTypeOf(new VSplitPtr)) 221 // for split 222 val splitIdx = RegInit(0.U(flowIdxBits.W)) 223 val strideOffsetReg = RegInit(0.U(VLEN.W)) 224 225 /** 226 * Redirect 227 */ 228 val flushed = WireInit(VecInit(Seq.fill(bufferSize)(false.B))) // entry has been flushed by the redirect arrived in the pre 1 cycle 229 val flushVec = (valid zip flushed).zip(uopq).map { case ((v, f), entry) => v && entry.uop.robIdx.needFlush(io.redirect) && !f } 230 val flushEnq = io.in.fire && io.in.bits.uop.robIdx.needFlush(io.redirect) 231 val flushNumReg = RegNext(PopCount(flushEnq +: flushVec)) 232 val redirectReg = RegNext(io.redirect) 233 val flushVecReg = RegNext(WireInit(VecInit(flushVec))) 234 235 // enqueue 236 when (io.in.fire && !flushEnq) { 237 val id = enqPtr.value 238 uopq(id) := io.in.bits 239 valid(id) := true.B 240 } 241 io.in.ready := isNotBefore(enqPtr, deqPtr) 242 243 //split uops 244 val issueValid = valid(deqPtr.value) 245 val issueEntry = uopq(deqPtr.value) 246 val issueMbIndex = issueEntry.mBIndex 247 val issueFlowNum = issueEntry.flowNum 248 val issueBaseAddr = issueEntry.baseAddr 249 val issueUop = issueEntry.uop 250 val issueUopIdx = issueUop.vpu.vuopIdx 251 val issueInstType = issueEntry.instType 252 val issueUopOffset = issueEntry.uopOffset 253 val issueEew = issueEntry.eew 254 val issueSew = issueEntry.sew 255 val issueLmul = issueEntry.emul 256 val issueEmul = issueEntry.lmul 257 val issueAlignedType = issueEntry.alignedType 258 val issuePreIsSplit = issueEntry.preIsSplit 259 val issueByteMask = issueEntry.byteMask 260 val elemIdx = GenElemIdx( 261 instType = issueInstType, 262 emul = issueEmul, 263 lmul = issueLmul, 264 eew = issueEew, 265 sew = issueSew, 266 uopIdx = issueUopIdx, 267 flowIdx = splitIdx 268 ) // elemIdx inside an inst, for exception 269 val indexedStride = IndexAddr( // index for indexed instruction 270 index = issueEntry.stride, 271 flow_inner_idx = ((splitIdx << issueEew(1, 0))(vOffsetBits - 1, 0) >> issueEew(1, 0)).asUInt, 272 eew = issueEew 273 ) 274 val issueStride = Mux(isIndexed(issueInstType), indexedStride, strideOffsetReg) 275 val vaddr = issueBaseAddr + issueUopOffset + issueStride 276 val mask = genVWmask128(vaddr ,issueAlignedType) // scala maske for flow 277 val flowMask = issueEntry.flowMask 278 val vecActive = (flowMask & UIntToOH(splitIdx)).orR 279 /* 280 * Unit-Stride split to one flow or two flow. 281 * for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two 282 */ 283 284 val usAligned128 = (vaddr(3,0) === 0.U)// addr 128-bit aligned 285 val usSplitMask = genUSSplitMask(issueByteMask, splitIdx, vaddr(3,0)) 286 val usNoSplit = (usAligned128 || !(vaddr(3,0) +& PopCount(usSplitMask))(4)) && !issuePreIsSplit && (splitIdx === 0.U)// unit-stride uop don't need to split into two flow 287 val usSplitVaddr = genUSSplitAddr(vaddr, splitIdx) 288 val regOffset = vaddr(3,0) // offset in 256-bits vd 289 XSError((splitIdx > 1.U && usNoSplit) || (splitIdx > 1.U && !issuePreIsSplit) , "Unit-Stride addr split error!\n") 290 291 // data 292 io.out.bits match { case x => 293 x.uop := issueUop 294 x.vaddr := Mux(!issuePreIsSplit, usSplitVaddr, vaddr) 295 x.alignedType := issueAlignedType 296 x.isvec := true.B 297 x.mask := Mux(!issuePreIsSplit, usSplitMask, mask) 298 x.reg_offset := regOffset //for merge unit-stride 299 x.vecActive := vecActive 300 x.is_first_ele := DontCare 301 x.usSecondInv := usNoSplit 302 x.elemIdx := elemIdx 303 x.uop_unit_stride_fof := DontCare 304 x.isFirstIssue := DontCare 305 x.mBIndex := issueMbIndex 306 } 307 308 //update enqptr 309 when (redirectReg.valid && flushNumReg =/= 0.U) { 310 enqPtr := enqPtr - flushNumReg 311 }.otherwise { 312 when (io.in.fire) { 313 enqPtr := enqPtr + 1.U 314 } 315 } 316 317 // flush queue 318 for (i <- 0 until bufferSize) { 319 when(flushVecReg(i) && redirectReg.valid && flushNumReg =/= 0.U) { 320 valid(i) := false.B 321 flushed(i) := true.B 322 } 323 } 324 325 /* Execute logic */ 326 /** Issue to scala pipeline**/ 327 val canIssue = Wire(Bool()) 328 val allowIssue = io.out.ready 329 val doIssue = Wire(Bool()) 330 val issueCount = Mux(usNoSplit, 2.U,PopCount(doIssue)) // for dont need split unit-stride, issue two flow 331 332 // handshake 333 val thisPtr = deqPtr.value 334 canIssue := !issueUop.robIdx.needFlush(io.redirect) && deqPtr < enqPtr 335 doIssue := canIssue && allowIssue 336 when (!RegNext(io.redirect.valid) || distanceBetween(enqPtr, deqPtr) > flushNumReg) { 337 when ((splitIdx < (issueFlowNum - issueCount)) && doIssue) { 338 // The uop has not been entirly splited yet 339 splitIdx := splitIdx + issueCount 340 strideOffsetReg := strideOffsetReg + issueStride 341 }.otherwise { 342 when (doIssue) { 343 // The uop is done spliting 344 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 345 valid(deqPtr.value) := false.B 346 strideOffsetReg := 0.U 347 deqPtr := deqPtr + 1.U 348 } 349 } 350 }.otherwise { 351 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 352 strideOffsetReg := 0.U 353 } 354 355 // out connect 356 io.out.valid := canIssue && (vecActive || !issuePreIsSplit) // TODO: inactive uop do not send to pipeline 357} 358 359class VSSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = true){ 360 override lazy val bufferSize = SplitBufferSize 361 // split data 362 val flowData = GenVSData( 363 data = issueEntry.data.asUInt, 364 elemIdx = splitIdx, 365 alignedType = issueAlignedType 366 ) 367 val usSplitData = genUSSplitData(issueEntry.data.asUInt, splitIdx, vaddr(3,0)) 368 369 io.out.bits.uop.sqIdx := issueUop.sqIdx + splitIdx 370 371 // send data to sq 372 val vstd = io.vstd.get 373 vstd.valid := canIssue 374 vstd.bits.uop := issueUop 375 vstd.bits.data := Mux(!issuePreIsSplit, usSplitData, flowData) 376 vstd.bits.debug := DontCare 377 vstd.bits.vdIdx.get := DontCare 378 vstd.bits.vdIdxInField.get := DontCare 379 vstd.bits.mask.get := Mux(!issuePreIsSplit, usSplitMask, mask) 380 381} 382 383class VLSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = false){ 384 override lazy val bufferSize = SplitBufferSize 385 io.out.bits.uop.lqIdx := issueUop.lqIdx + splitIdx 386} 387 388class VSSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = true){ 389} 390 391class VLSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = false){ 392} 393 394class VLSplitImp(implicit p: Parameters) extends VLSUModule{ 395 val io = IO(new VSplitIO(isVStore=false)) 396 val splitPipeline = Module(new VLSplitPipelineImp()) 397 val splitBuffer = Module(new VLSplitBufferImp()) 398 // Split Pipeline 399 splitPipeline.io.in <> io.in 400 splitPipeline.io.redirect <> io.redirect 401 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 402 403 // Split Buffer 404 splitBuffer.io.in <> splitPipeline.io.out 405 splitBuffer.io.redirect <> io.redirect 406 io.out <> splitBuffer.io.out 407} 408 409class VSSplitImp(implicit p: Parameters) extends VLSUModule{ 410 val io = IO(new VSplitIO(isVStore=true)) 411 val splitPipeline = Module(new VSSplitPipelineImp()) 412 val splitBuffer = Module(new VSSplitBufferImp()) 413 // Split Pipeline 414 splitPipeline.io.in <> io.in 415 splitPipeline.io.redirect <> io.redirect 416 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 417 418 // Split Buffer 419 splitBuffer.io.in <> splitPipeline.io.out 420 splitBuffer.io.redirect <> io.redirect 421 io.out <> splitBuffer.io.out 422 io.vstd.get <> splitBuffer.io.vstd.get 423} 424 425