xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala (revision 039cdc35f5f3b68b6295ec5ace90f22a77322e02) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils._
23import utility._
24import xiangshan.ExceptionNO._
25import xiangshan._
26import xiangshan.backend.fu.PMPRespBundle
27import xiangshan.cache._
28import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp}
29
30trait HasL1PrefetchSourceParameter {
31  // l1 prefetch source related
32  def L1PfSourceBits = 3
33  def L1_HW_PREFETCH_NULL = 0.U
34  def L1_HW_PREFETCH_STRIDE = 1.U
35  def L1_HW_PREFETCH_STREAM = 2.U
36  def L1_HW_PREFETCH_STORE  = 3.U
37
38  def isFromL1Prefetch(value: UInt) = value =/= L1_HW_PREFETCH_NULL
39  def isFromStride(value: UInt)     = value === L1_HW_PREFETCH_STRIDE
40  def isFromStream(value: UInt)     = value === L1_HW_PREFETCH_STREAM
41}
42
43class L1PrefetchSource(implicit p: Parameters) extends XSBundle with HasL1PrefetchSourceParameter {
44  val value = UInt(L1PfSourceBits.W)
45}
46
47class L1PrefetchReq(implicit p: Parameters) extends XSBundle with HasDCacheParameters {
48  val paddr = UInt(PAddrBits.W)
49  val alias = UInt(2.W)
50  val confidence = UInt(1.W)
51  val is_store = Bool()
52  val pf_source = new L1PrefetchSource
53
54  // only index bit is used, do not use tag
55  def getVaddr(): UInt = {
56    Cat(alias, paddr(DCacheSameVPAddrLength-1, 0))
57  }
58
59  // when l1 cache prefetch req arrives at load unit:
60  // if (confidence == 1)
61  //   override load unit 2 load req
62  // else if (load unit 1/2 is available)
63  //   send prefetch req
64  // else
65  //   report prefetch !ready
66}
67
68class L1PrefetchHint(implicit p: Parameters) extends XSBundle with HasDCacheParameters {
69  val loadbusy = Bool()
70  val missqbusy = Bool()
71}
72
73class L1PrefetchFuzzer(implicit p: Parameters) extends DCacheModule{
74  val io = IO(new Bundle() {
75    // prefetch req interface
76    val req = Decoupled(new L1PrefetchReq())
77    // for fuzzer address gen
78    val vaddr = Input(UInt(VAddrBits.W))
79    val paddr = Input(UInt(PAddrBits.W))
80  })
81
82  // prefetch req queue is not provided, prefetcher must maintain its
83  // own prefetch req queue.
84  val rand_offset = LFSR64(seed=Some(123L))(5,0) << 6
85  val rand_addr_select = LFSR64(seed=Some(567L))(3,0) === 0.U
86
87  // use valid vaddr and paddr
88  val rand_vaddr = DelayN(io.vaddr, 2)
89  val rand_paddr = DelayN(io.paddr, 2)
90
91  io.req.bits.paddr := 0x80000000L.U + rand_offset
92  io.req.bits.alias := io.req.bits.paddr(13,12)
93  io.req.bits.confidence := LFSR64(seed=Some(789L))(4,0) === 0.U
94  io.req.bits.is_store := LFSR64(seed=Some(890L))(4,0) === 0.U
95  io.req.valid := LFSR64(seed=Some(901L))(3,0) === 0.U
96}