xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala (revision ffc9de54938a9574f465b83a71d5252cfd37cf30) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan.mem.prefetch
18
19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import utility.MemReqSource
23import xiangshan._
24import xiangshan.cache.mmu.TlbRequestIO
25import xiangshan.mem.{L1PrefetchReq, LdPrefetchTrainBundle}
26
27class PrefetcherIO()(implicit p: Parameters) extends XSBundle {
28  val ld_in = Flipped(Vec(exuParameters.LduCnt, ValidIO(new LdPrefetchTrainBundle())))
29  val tlb_req = new TlbRequestIO(nRespDups = 2)
30  val l2_req = ValidIO(new Bundle() {
31    val addr = UInt(PAddrBits.W)
32    val source = UInt(MemReqSource.reqSourceBits.W)
33  })
34  val l1_req = DecoupledIO(new L1PrefetchReq())
35  val enable = Input(Bool())
36}
37
38trait PrefetcherParams
39
40abstract class BasePrefecher()(implicit p: Parameters) extends XSModule {
41  val io = IO(new PrefetcherIO())
42}