xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala (revision 6639e9a467468f4e1b05a25a5de4500772aedeb1) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan.mem.prefetch
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config.Parameters
22import utility.MemReqSource
23import xiangshan._
24import xiangshan.cache.mmu.TlbRequestIO
25import xiangshan.mem.{LdPrefetchTrainBundle, StPrefetchTrainBundle, L1PrefetchReq}
26import xiangshan.backend._
27
28class L2PrefetchReq(implicit p: Parameters) extends XSBundle {
29  val addr = UInt(PAddrBits.W)
30  val source = UInt(MemReqSource.reqSourceBits.W)
31}
32
33class PrefetcherIO()(implicit p: Parameters) extends XSBundle {
34  val ld_in = Flipped(Vec(backendParams.LdExuCnt, ValidIO(new LdPrefetchTrainBundle())))
35  val st_in = Flipped(Vec(backendParams.StaExuCnt, ValidIO(new StPrefetchTrainBundle())))
36  val tlb_req = new TlbRequestIO(nRespDups = 2)
37  val l1_req = DecoupledIO(new L1PrefetchReq())
38  val l2_req = ValidIO(new L2PrefetchReq())
39  val l3_req = ValidIO(UInt(PAddrBits.W)) // TODO: l3 pf source
40  val enable = Input(Bool())
41}
42
43class PrefetchReqBundle()(implicit p: Parameters) extends XSBundle {
44  val vaddr       = UInt(VAddrBits.W)
45  val paddr       = UInt(PAddrBits.W)
46  val pc          = UInt(VAddrBits.W)
47  val miss        = Bool()
48  val pfHitStream = Bool()
49}
50
51trait PrefetcherParams
52
53abstract class BasePrefecher()(implicit p: Parameters) extends XSModule {
54  val io = IO(new PrefetcherIO())
55
56  io.l3_req.valid := false.B
57  io.l3_req.bits  := DontCare
58}