1*ffc9de54Swakafa/*************************************************************************************** 2*ffc9de54Swakafa * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3*ffc9de54Swakafa * Copyright (c) 2020-2021 Peng Cheng Laboratory 4*ffc9de54Swakafa * 5*ffc9de54Swakafa * XiangShan is licensed under Mulan PSL v2. 6*ffc9de54Swakafa * You can use this software according to the terms and conditions of the Mulan PSL v2. 7*ffc9de54Swakafa * You may obtain a copy of Mulan PSL v2 at: 8*ffc9de54Swakafa * http://license.coscl.org.cn/MulanPSL2 9*ffc9de54Swakafa * 10*ffc9de54Swakafa * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11*ffc9de54Swakafa * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12*ffc9de54Swakafa * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13*ffc9de54Swakafa * 14*ffc9de54Swakafa * See the Mulan PSL v2 for more details. 15*ffc9de54Swakafa ***************************************************************************************/ 16*ffc9de54Swakafa 17289fc2f9SLinJiaweipackage xiangshan.mem.prefetch 18289fc2f9SLinJiawei 19289fc2f9SLinJiaweiimport chisel3._ 20289fc2f9SLinJiaweiimport chisel3.util._ 21289fc2f9SLinJiaweiimport chipsalliance.rocketchip.config.Parameters 22*ffc9de54Swakafaimport utility.MemReqSource 23289fc2f9SLinJiaweiimport xiangshan._ 24289fc2f9SLinJiaweiimport xiangshan.cache.mmu.TlbRequestIO 25*ffc9de54Swakafaimport xiangshan.mem.{L1PrefetchReq, LdPrefetchTrainBundle} 26289fc2f9SLinJiawei 27289fc2f9SLinJiaweiclass PrefetcherIO()(implicit p: Parameters) extends XSBundle { 283af6aa6eSWilliam Wang val ld_in = Flipped(Vec(exuParameters.LduCnt, ValidIO(new LdPrefetchTrainBundle()))) 29289fc2f9SLinJiawei val tlb_req = new TlbRequestIO(nRespDups = 2) 30*ffc9de54Swakafa val l2_req = ValidIO(new Bundle() { 31*ffc9de54Swakafa val addr = UInt(PAddrBits.W) 32*ffc9de54Swakafa val source = UInt(MemReqSource.reqSourceBits.W) 33*ffc9de54Swakafa }) 34967327d8SLinJiawei val l1_req = DecoupledIO(new L1PrefetchReq()) 3585de5caeSLinJiawei val enable = Input(Bool()) 36289fc2f9SLinJiawei} 37289fc2f9SLinJiawei 38289fc2f9SLinJiaweitrait PrefetcherParams 39289fc2f9SLinJiawei 40289fc2f9SLinJiaweiabstract class BasePrefecher()(implicit p: Parameters) extends XSModule { 41289fc2f9SLinJiawei val io = IO(new PrefetcherIO()) 42289fc2f9SLinJiawei}