xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala (revision 289fc2f9291f65a873c97dd5ad2876aea033ce6f) 
1*289fc2f9SLinJiaweipackage xiangshan.mem.prefetch
2*289fc2f9SLinJiawei
3*289fc2f9SLinJiaweiimport chisel3._
4*289fc2f9SLinJiaweiimport chisel3.util._
5*289fc2f9SLinJiaweiimport chipsalliance.rocketchip.config.Parameters
6*289fc2f9SLinJiaweiimport xiangshan._
7*289fc2f9SLinJiaweiimport xiangshan.cache.mmu.TlbRequestIO
8*289fc2f9SLinJiaweiimport xiangshan.mem.LsPipelineBundle
9*289fc2f9SLinJiawei
10*289fc2f9SLinJiaweiclass PrefetcherIO()(implicit p: Parameters) extends XSBundle {
11*289fc2f9SLinJiawei  val ld_in = Flipped(Vec(exuParameters.LduCnt, ValidIO(new LsPipelineBundle())))
12*289fc2f9SLinJiawei  val tlb_req = new TlbRequestIO(nRespDups = 2)
13*289fc2f9SLinJiawei  val pf_addr = ValidIO(UInt(PAddrBits.W))
14*289fc2f9SLinJiawei}
15*289fc2f9SLinJiawei
16*289fc2f9SLinJiaweitrait PrefetcherParams
17*289fc2f9SLinJiawei
18*289fc2f9SLinJiaweiabstract class BasePrefecher()(implicit p: Parameters) extends XSModule {
19*289fc2f9SLinJiawei  val io = IO(new PrefetcherIO())
20*289fc2f9SLinJiawei}