1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9 10// Store Pipeline Stage 0 11// Generate addr, use addr to query DCache and DTLB 12class StoreUnit_S0 extends XSModule { 13 val io = IO(new Bundle() { 14 val in = Flipped(Decoupled(new ExuInput)) 15 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 16 val out = Decoupled(new LsPipelineBundle) 17 val dtlbReq = DecoupledIO(new TlbReq) 18 }) 19 20 // send req to dtlb 21 // val saddr = io.in.bits.src1 + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 22 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 23 val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 24 val saddr_hi = Mux(saddr_lo(12), 25 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+1.U), 26 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src1(VAddrBits-1, 12)), 27 ) 28 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 29 30 io.dtlbReq.bits.vaddr := saddr 31 io.dtlbReq.valid := io.in.valid 32 io.dtlbReq.bits.cmd := TlbCmd.write 33 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 34 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 35 36 io.out.bits := DontCare 37 io.out.bits.vaddr := saddr 38 39 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 40 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 41 io.out.bits.data := io.in.bits.src2 42 } // not not touch fp store raw data 43 io.out.bits.uop := io.in.bits.uop 44 io.out.bits.miss := DontCare 45 io.out.bits.rsIdx := io.rsIdx 46 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 47 io.out.valid := io.in.valid 48 io.in.ready := io.out.ready 49 50 // exception check 51 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 52 "b00".U -> true.B, //b 53 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 54 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 55 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 56 )) 57 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 58 59} 60 61// Load Pipeline Stage 1 62// TLB resp (send paddr to dcache) 63class StoreUnit_S1 extends XSModule { 64 val io = IO(new Bundle() { 65 val in = Flipped(Decoupled(new LsPipelineBundle)) 66 val out = Decoupled(new LsPipelineBundle) 67 // val fp_out = Decoupled(new LsPipelineBundle) 68 val lsq = ValidIO(new LsPipelineBundle) 69 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 70 val tlbFeedback = ValidIO(new TlbFeedback) 71 }) 72 73 val s1_paddr = io.dtlbResp.bits.paddr 74 val s1_tlb_miss = io.dtlbResp.bits.miss 75 val s1_mmio = io.dtlbResp.bits.mmio 76 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 77 78 io.in.ready := true.B 79 80 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 81 82 // Send TLB feedback to store issue queue 83 io.tlbFeedback.valid := io.in.valid 84 io.tlbFeedback.bits.hit := !s1_tlb_miss 85 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 86 XSDebug(io.tlbFeedback.valid, 87 "S1 Store: tlbHit: %d roqIdx: %d\n", 88 io.tlbFeedback.bits.hit, 89 io.tlbFeedback.bits.rsIdx 90 ) 91 92 93 // get paddr from dtlb, check if rollback is needed 94 // writeback store inst to lsq 95 io.lsq.valid := io.in.valid && !s1_tlb_miss// TODO: && ! FP 96 io.lsq.bits := io.in.bits 97 io.lsq.bits.paddr := s1_paddr 98 io.lsq.bits.miss := false.B 99 io.lsq.bits.mmio := s1_mmio && !s1_exception 100 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 101 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 102 103 // mmio inst with exception will be writebacked immediately 104 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 105 io.out.bits := io.lsq.bits 106 107 // encode data for fp store 108 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 109 io.lsq.bits.data := genWdata(ieee(io.in.bits.data), io.in.bits.uop.ctrl.fuOpType(1,0)) 110 } 111 112} 113 114class StoreUnit_S2 extends XSModule { 115 val io = IO(new Bundle() { 116 val in = Flipped(Decoupled(new LsPipelineBundle)) 117 val out = Decoupled(new LsPipelineBundle) 118 }) 119 120 io.in.ready := true.B 121 io.out.bits := io.in.bits 122 io.out.valid := io.in.valid 123 124} 125 126class StoreUnit_S3 extends XSModule { 127 val io = IO(new Bundle() { 128 val in = Flipped(Decoupled(new LsPipelineBundle)) 129 val stout = DecoupledIO(new ExuOutput) // writeback store 130 }) 131 132 io.in.ready := true.B 133 134 io.stout.valid := io.in.valid 135 io.stout.bits.uop := io.in.bits.uop 136 io.stout.bits.data := DontCare 137 io.stout.bits.redirectValid := false.B 138 io.stout.bits.redirect := DontCare 139 io.stout.bits.debug.isMMIO := io.in.bits.mmio 140 io.stout.bits.debug.paddr := DontCare 141 io.stout.bits.debug.isPerfCnt := false.B 142 io.stout.bits.fflags := DontCare 143 144} 145 146class StoreUnit extends XSModule { 147 val io = IO(new Bundle() { 148 val stin = Flipped(Decoupled(new ExuInput)) 149 val redirect = Flipped(ValidIO(new Redirect)) 150 val flush = Input(Bool()) 151 val tlbFeedback = ValidIO(new TlbFeedback) 152 val dtlb = new TlbRequestIO() 153 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 154 val lsq = ValidIO(new LsPipelineBundle) 155 val stout = DecoupledIO(new ExuOutput) // writeback store 156 }) 157 158 val store_s0 = Module(new StoreUnit_S0) 159 val store_s1 = Module(new StoreUnit_S1) 160 val store_s2 = Module(new StoreUnit_S2) 161 val store_s3 = Module(new StoreUnit_S3) 162 163 store_s0.io.in <> io.stin 164 store_s0.io.dtlbReq <> io.dtlb.req 165 store_s0.io.rsIdx := io.rsIdx 166 167 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 168 169 store_s1.io.lsq <> io.lsq // send result to sq 170 store_s1.io.dtlbResp <> io.dtlb.resp 171 store_s1.io.tlbFeedback <> io.tlbFeedback 172 173 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 174 175 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 176 177 store_s3.io.stout <> io.stout 178 179 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 180 XSDebug(cond, 181 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 182 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 183 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 184 p"data ${Hexadecimal(pipeline.data)} " + 185 p"mask ${Hexadecimal(pipeline.mask)}\n" 186 ) 187 } 188 189 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 190 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 191 192} 193