1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.backend.rob.DebugLsInfoBundle 28import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 29import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 30 31class StoreUnit(implicit p: Parameters) extends XSModule with HasDCacheParameters { 32 val io = IO(new Bundle() { 33 val redirect = Flipped(ValidIO(new Redirect)) 34 val stin = Flipped(Decoupled(new ExuInput)) 35 val issue = Valid(new ExuInput) 36 val tlb = new TlbRequestIO() 37 val dcache = new DCacheStoreIO 38 val pmp = Flipped(new PMPRespBundle()) 39 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 40 val isFirstIssue = Input(Bool()) 41 val lsq = ValidIO(new LsPipelineBundle) 42 val lsq_replenish = Output(new LsPipelineBundle()) 43 val feedback_slow = ValidIO(new RSFeedback) 44 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 45 // provide prefetch info to sms 46 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 47 val stld_nuke_query = Valid(new StoreNukeQueryIO) 48 val stout = DecoupledIO(new ExuOutput) // writeback store 49 // store mask, send to sq in store_s0 50 val st_mask_out = Valid(new StoreMaskBundle) 51 val debug_ls = Output(new DebugLsInfoBundle) 52 }) 53 54 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 55 56 // Pipeline 57 // -------------------------------------------------------------------------------- 58 // stage 0 59 // -------------------------------------------------------------------------------- 60 // generate addr, use addr to query DCache and DTLB 61 val s0_iss_valid = io.stin.valid 62 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 63 val s0_valid = s0_iss_valid || s0_prf_valid 64 val s0_use_flow_rs = s0_iss_valid 65 val s0_use_flow_prf = !s0_iss_valid && s0_prf_valid 66 val s0_in = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 67 val s0_isFirstIssue = Mux(s0_use_flow_rs, io.isFirstIssue, false.B) 68 val s0_rsIdx = Mux(s0_use_flow_rs, io.rsIdx, 0.U) 69 val s0_size = Mux(s0_use_flow_rs, LSUOpType.size(s0_in.uop.ctrl.fuOpType), 3.U) 70 val s0_mem_idx = Mux(s0_use_flow_rs, s0_in.uop.sqIdx.value, 0.U) 71 val s0_rob_idx = Mux(s0_use_flow_rs, s0_in.uop.robIdx, 0.U.asTypeOf(s0_in.uop.robIdx)) 72 val s0_pc = Mux(s0_use_flow_rs, s0_in.uop.cf.pc, 0.U) 73 val s0_instr_type = Mux(s0_use_flow_rs, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 74 val s0_wlineflag = Mux(s0_use_flow_rs, s0_in.uop.ctrl.fuOpType === LSUOpType.cbo_zero, false.B) 75 val s0_out = Wire(new LsPipelineBundle) 76 val s0_kill = s0_in.uop.robIdx.needFlush(io.redirect) 77 val s0_can_go = s1_ready 78 val s0_fire = s0_valid && !s0_kill && s0_can_go 79 80 // generate addr 81 // val saddr = s0_in.bits.src(0) + SignExt(s0_in.bits.uop.ctrl.imm(11,0), VAddrBits) 82 val imm12 = WireInit(s0_in.uop.ctrl.imm(11,0)) 83 val saddr_lo = s0_in.src(0)(11,0) + Cat(0.U(1.W), imm12) 84 val saddr_hi = Mux(saddr_lo(12), 85 Mux(imm12(11), s0_in.src(0)(VAddrBits-1, 12), s0_in.src(0)(VAddrBits-1, 12)+1.U), 86 Mux(imm12(11), s0_in.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), s0_in.src(0)(VAddrBits-1, 12)), 87 ) 88 val s0_saddr = Cat(saddr_hi, saddr_lo(11,0)) 89 val isHsv = WireInit(LSUOpType.isHsv(io.in.bits.uop.ctrl.fuOpType)) 90 val s0_vaddr = Mux(s0_use_flow_rs, s0_saddr, io.prefetch_req.bits.vaddr) 91 val s0_mask = Mux(s0_use_flow_rs, genVWmask(s0_saddr, s0_in.uop.ctrl.fuOpType(1,0)), 3.U) 92 93 io.tlb.req.valid := s0_valid 94 io.tlb.req.bits.vaddr := s0_vaddr 95 io.tlb.req.bits.cmd := TlbCmd.write 96 io.dtlbReq.bits.hyperinst := isHsv 97 io.dtlbReq.bits.hlvx := false.B 98 io.tlb.req.bits.size := s0_size 99 io.tlb.req.bits.kill := false.B 100 io.tlb.req.bits.memidx.is_ld := false.B 101 io.tlb.req.bits.memidx.is_st := true.B 102 io.tlb.req.bits.memidx.idx := s0_mem_idx 103 io.tlb.req.bits.debug.robIdx := s0_rob_idx 104 io.tlb.req.bits.no_translate := false.B 105 io.tlb.req.bits.debug.pc := s0_pc 106 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 107 io.tlb.req_kill := false.B 108 109 // Dcache access here: not **real** dcache write 110 // just read meta and tag in dcache, to find out the store will hit or miss 111 112 // NOTE: The store request does not wait for the dcache to be ready. 113 // If the dcache is not ready at this time, the dcache is not queried. 114 // But, store prefetch request will always wait for dcache to be ready to make progress. 115 io.dcache.req.valid := s0_fire 116 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 117 io.dcache.req.bits.vaddr := s0_vaddr 118 io.dcache.req.bits.instrtype := s0_instr_type 119 120 s0_out := DontCare 121 s0_out.vaddr := s0_vaddr 122 // Now data use its own io 123 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.ctrl.fuOpType(1,0)) 124 s0_out.data := s0_in.src(1) // FIXME: remove data from pipeline 125 s0_out.uop := s0_in.uop 126 s0_out.miss := false.B 127 s0_out.rsIdx := s0_rsIdx 128 s0_out.mask := s0_mask 129 s0_out.isFirstIssue := s0_isFirstIssue 130 s0_out.isHWPrefetch := s0_use_flow_prf 131 s0_out.wlineflag := s0_wlineflag 132 when(s0_valid && s0_isFirstIssue) { 133 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 134 } 135 136 // exception check 137 val s0_addr_aligned = LookupTree(s0_in.uop.ctrl.fuOpType(1,0), List( 138 "b00".U -> true.B, //b 139 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 140 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 141 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 142 )) 143 s0_out.uop.cf.exceptionVec(storeAddrMisaligned) := Mux(s0_use_flow_rs, !s0_addr_aligned, false.B) 144 145 io.st_mask_out.valid := s0_use_flow_rs 146 io.st_mask_out.bits.mask := s0_out.mask 147 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 148 149 io.stin.ready := s1_ready 150 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid 151 152 // Pipeline 153 // -------------------------------------------------------------------------------- 154 // stage 1 155 // -------------------------------------------------------------------------------- 156 // TLB resp (send paddr to dcache) 157 val s1_valid = RegInit(false.B) 158 val s1_in = RegEnable(s0_out, s0_fire) 159 val s1_out = Wire(new LsPipelineBundle) 160 val s1_kill = Wire(Bool()) 161 val s1_can_go = s2_ready 162 val s1_fire = s1_valid && !s1_kill && s1_can_go 163 164 // mmio cbo decoder 165 val s1_mmio_cbo = s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_clean || 166 s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_flush || 167 s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_inval 168 val s1_paddr = io.tlb.resp.bits.paddr(0) 169 val s1_gpaddr = io.dtlbResp.bits.gpaddr(0) 170 val s1_tlb_miss = io.tlb.resp.bits.miss 171 val s1_mmio = s1_mmio_cbo 172 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.cf.exceptionVec, staCfg).asUInt.orR 173 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || s1_tlb_miss 174 175 s1_ready := !s1_valid || s1_kill || s2_ready 176 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 177 when (s0_fire) { s1_valid := true.B } 178 .elsewhen (s1_fire) { s1_valid := false.B } 179 .elsewhen (s1_kill) { s1_valid := false.B } 180 181 // st-ld violation dectect request. 182 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 183 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 184 io.stld_nuke_query.bits.paddr := s1_paddr 185 io.stld_nuke_query.bits.mask := s1_in.mask 186 187 // issue 188 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 189 io.issue.bits := RegEnable(s0_in, s0_valid) 190 191 192 // Send TLB feedback to store issue queue 193 // Store feedback is generated in store_s1, sent to RS in store_s2 194 val s1_feedback = Wire(Valid(new RSFeedback)) 195 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 196 s1_feedback.bits.hit := !s1_tlb_miss 197 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 198 s1_feedback.bits.rsIdx := s1_out.rsIdx 199 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 200 s1_feedback.bits.dataInvalidSqIdx := DontCare 201 XSDebug(s1_feedback.valid, 202 "S1 Store: tlbHit: %d robIdx: %d\n", 203 s1_feedback.bits.hit, 204 s1_feedback.bits.rsIdx 205 ) 206 207 io.feedback_slow := s1_feedback 208 209 // get paddr from dtlb, check if rollback is needed 210 // writeback store inst to lsq 211 s1_out := s1_in 212 s1_out.paddr := s1_paddr 213 io.out.bits.gpaddr := s1_gpaddr 214 s1_out.miss := false.B 215 s1_out.mmio := s1_mmio 216 s1_out.tlbMiss := s1_tlb_miss 217 s1_out.atomic := s1_mmio 218 s1_out.uop.cf.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 219 s1_out.uop.cf.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 220 io.out.bits.uop.cf.exceptionVec(storeGuestPageFault) := io.dtlbResp.bits.excp(0).gpf.st 221 222 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch 223 io.lsq.bits := s1_out 224 io.lsq.bits.miss := s1_tlb_miss 225 226 // kill dcache write intent request when tlb miss or exception 227 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 228 io.dcache.s1_paddr := s1_paddr 229 230 // write below io.out.bits assign sentence to prevent overwriting values 231 val s1_tlb_memidx = io.tlb.resp.bits.memidx 232 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 233 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 234 s1_out.uop.debugInfo.tlbRespTime := GTimer() 235 } 236 237 // Pipeline 238 // -------------------------------------------------------------------------------- 239 // stage 2 240 // -------------------------------------------------------------------------------- 241 // mmio check 242 val s2_valid = RegInit(false.B) 243 val s2_in = RegEnable(s1_out, s1_fire) 244 val s2_out = Wire(new LsPipelineBundle) 245 val s2_kill = Wire(Bool()) 246 val s2_can_go = s3_ready 247 val s2_fire = s2_valid && !s2_kill && s2_can_go 248 249 s2_ready := !s2_valid || s2_kill || s3_ready 250 when (s1_fire) { s2_valid := true.B } 251 .elsewhen (s2_fire) { s2_valid := false.B } 252 .elsewhen (s2_kill) { s2_valid := false.B } 253 254 val s2_pmp = WireInit(io.pmp) 255 256 val s2_exception = ExceptionNO.selectByFu(s2_out.uop.cf.exceptionVec, staCfg).asUInt.orR 257 val s2_mmio = s2_in.mmio || s2_pmp.mmio 258 s2_kill := (s2_mmio && !s2_exception) || s2_in.uop.robIdx.needFlush(io.redirect) 259 260 s2_out := s2_in 261 s2_out.mmio := s2_mmio && !s2_exception 262 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 263 s2_out.uop.cf.exceptionVec(storeAccessFault) := s2_in.uop.cf.exceptionVec(storeAccessFault) || s2_pmp.st 264 265 // kill dcache write intent request when mmio or exception 266 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 267 io.dcache.s2_pc := s2_out.uop.cf.pc 268 // TODO: dcache resp 269 io.dcache.resp.ready := true.B 270 271 // feedback tlb miss to RS in store_s2 272 io.feedback_slow.valid := RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) 273 io.feedback_slow.bits := RegNext(s1_feedback.bits) 274 275 // mmio and exception 276 io.lsq_replenish := s2_out 277 278 // prefetch related 279 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 280 281 // RegNext prefetch train for better timing 282 // ** Now, prefetch train is valid at store s3 ** 283 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true) 284 // override miss bit 285 io.prefetch_train.bits.miss := RegNext(io.dcache.resp.bits.miss) 286 // TODO: add prefetch and access bit 287 io.prefetch_train.bits.meta_prefetch := false.B 288 io.prefetch_train.bits.meta_access := false.B 289 if(EnableStorePrefetchSMS) { 290 io.prefetch_train.valid := RegNext(s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch) 291 }else { 292 io.prefetch_train.valid := false.B 293 } 294 295 // Pipeline 296 // -------------------------------------------------------------------------------- 297 // stage 3 298 // -------------------------------------------------------------------------------- 299 // store write back 300 val s3_valid = RegInit(false.B) 301 val s3_in = RegEnable(s2_out, s2_fire) 302 val s3_out = Wire(new ExuOutput) 303 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 304 val s3_can_go = s3_ready 305 val s3_fire = s3_valid && !s3_kill && s3_can_go 306 307 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch } 308 .elsewhen (s3_fire) { s3_valid := false.B } 309 .elsewhen (s3_kill) { s3_valid := false.B } 310 311 // wb: writeback 312 val SelectGroupSize = RollbackGroupSize 313 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 314 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 315 316 s3_out := DontCare 317 s3_out.uop := s3_in.uop 318 s3_out.data := DontCare 319 s3_out.redirectValid := false.B 320 s3_out.redirect := DontCare 321 s3_out.debug.isMMIO := s3_in.mmio 322 s3_out.debug.paddr := s3_in.paddr 323 s3_out.debug.vaddr := s3_in.vaddr 324 s3_out.debug.isPerfCnt := false.B 325 s3_out.fflags := DontCare 326 327 // Pipeline 328 // -------------------------------------------------------------------------------- 329 // stage x 330 // -------------------------------------------------------------------------------- 331 // delay TotalSelectCycles - 2 cycle(s) 332 val TotalDelayCycles = TotalSelectCycles - 2 333 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 334 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 335 val sx_in = Wire(Vec(TotalDelayCycles + 1, new ExuOutput)) 336 337 // backward ready signal 338 s3_ready := sx_ready.head 339 for (i <- 0 until TotalDelayCycles + 1) { 340 if (i == 0) { 341 sx_valid(i) := s3_valid 342 sx_in(i) := s3_out 343 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 344 } else { 345 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 346 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 347 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 348 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 349 350 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 351 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 352 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 353 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 354 } 355 } 356 val sx_last_valid = sx_valid.takeRight(1).head 357 val sx_last_ready = sx_ready.takeRight(1).head 358 val sx_last_in = sx_in.takeRight(1).head 359 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 360 361 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) 362 io.stout.bits := sx_last_in 363 io.stout.bits.redirectValid := false.B 364 365 io.debug_ls := DontCare 366 io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 367 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 368 369 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 370 XSDebug(cond, 371 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 372 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 373 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 374 p"data ${Hexadecimal(pipeline.data)} " + 375 p"mask ${Hexadecimal(pipeline.mask)}\n" 376 ) 377 } 378 379 printPipeLine(s0_out, s0_valid, "S0") 380 printPipeLine(s1_out, s1_valid, "S1") 381 382 // perf cnt 383 XSPerfAccumulate("s0_in_valid", s0_valid) 384 XSPerfAccumulate("s0_in_fire", s0_fire) 385 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 386 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_saddr(VAddrBits-1, 12) === s0_in.src(0)(VAddrBits-1, 12)) 387 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_saddr(VAddrBits-1, 12) =/= s0_in.src(0)(VAddrBits-1, 12)) 388 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_saddr(VAddrBits-1, 12) === s0_in.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 389 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_saddr(VAddrBits-1, 12) =/= s0_in.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 390 391 XSPerfAccumulate("s1_in_valid", s1_valid) 392 XSPerfAccumulate("s1_in_fire", s1_fire) 393 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 394 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 395 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 396 // end 397}