1package xiangshan.mem 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils._ 7import xiangshan._ 8import xiangshan.backend.decode.ImmUnion 9import xiangshan.cache._ 10 11// Store Pipeline Stage 0 12// Generate addr, use addr to query DCache and DTLB 13class StoreUnit_S0(implicit p: Parameters) extends XSModule { 14 val io = IO(new Bundle() { 15 val in = Flipped(Decoupled(new ExuInput)) 16 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 17 val isFirstIssue = Input(Bool()) 18 val out = Decoupled(new LsPipelineBundle) 19 val dtlbReq = DecoupledIO(new TlbReq) 20 }) 21 22 // send req to dtlb 23 // val saddr = io.in.bits.src1 + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 24 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 25 val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 26 val saddr_hi = Mux(saddr_lo(12), 27 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+1.U), 28 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src1(VAddrBits-1, 12)), 29 ) 30 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 31 32 io.dtlbReq.bits.vaddr := saddr 33 io.dtlbReq.valid := io.in.valid 34 io.dtlbReq.bits.cmd := TlbCmd.write 35 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 36 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 37 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 38 39 io.out.bits := DontCare 40 io.out.bits.vaddr := saddr 41 42 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 43 io.out.bits.uop := io.in.bits.uop 44 io.out.bits.miss := DontCare 45 io.out.bits.rsIdx := io.rsIdx 46 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 47 io.out.valid := io.in.valid 48 io.in.ready := io.out.ready 49 50 // exception check 51 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 52 "b00".U -> true.B, //b 53 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 54 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 55 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 56 )) 57 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 58 59 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src1(VAddrBits-1, 12)) 60 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src1(VAddrBits-1, 12)) 61 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src1(VAddrBits-1, 12) && io.isFirstIssue) 62 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src1(VAddrBits-1, 12) && io.isFirstIssue) 63} 64 65// Load Pipeline Stage 1 66// TLB resp (send paddr to dcache) 67class StoreUnit_S1(implicit p: Parameters) extends XSModule { 68 val io = IO(new Bundle() { 69 val in = Flipped(Decoupled(new LsPipelineBundle)) 70 val out = Decoupled(new LsPipelineBundle) 71 val lsq = ValidIO(new LsPipelineBundle) 72 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 73 val tlbFeedback = ValidIO(new TlbFeedback) 74 }) 75 76 val s1_paddr = io.dtlbResp.bits.paddr 77 val s1_tlb_miss = io.dtlbResp.bits.miss 78 val s1_mmio = io.dtlbResp.bits.mmio 79 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 80 81 io.in.ready := true.B 82 83 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 84 85 // Send TLB feedback to store issue queue 86 io.tlbFeedback.valid := io.in.valid 87 io.tlbFeedback.bits.hit := !s1_tlb_miss 88 io.tlbFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 89 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 90 XSDebug(io.tlbFeedback.valid, 91 "S1 Store: tlbHit: %d roqIdx: %d\n", 92 io.tlbFeedback.bits.hit, 93 io.tlbFeedback.bits.rsIdx 94 ) 95 96 97 // get paddr from dtlb, check if rollback is needed 98 // writeback store inst to lsq 99 io.lsq.valid := io.in.valid && !s1_tlb_miss 100 io.lsq.bits := io.in.bits 101 io.lsq.bits.paddr := s1_paddr 102 io.lsq.bits.miss := false.B 103 io.lsq.bits.mmio := s1_mmio && !s1_exception 104 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 105 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 106 107 // mmio inst with exception will be writebacked immediately 108 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 109 io.out.bits := io.lsq.bits 110} 111 112class StoreUnit_S2(implicit p: Parameters) extends XSModule { 113 val io = IO(new Bundle() { 114 val in = Flipped(Decoupled(new LsPipelineBundle)) 115 val out = Decoupled(new LsPipelineBundle) 116 }) 117 118 io.in.ready := true.B 119 io.out.bits := io.in.bits 120 io.out.valid := io.in.valid 121 122} 123 124class StoreUnit_S3(implicit p: Parameters) extends XSModule { 125 val io = IO(new Bundle() { 126 val in = Flipped(Decoupled(new LsPipelineBundle)) 127 val stout = DecoupledIO(new ExuOutput) // writeback store 128 }) 129 130 io.in.ready := true.B 131 132 io.stout.valid := io.in.valid 133 io.stout.bits.uop := io.in.bits.uop 134 io.stout.bits.data := DontCare 135 io.stout.bits.redirectValid := false.B 136 io.stout.bits.redirect := DontCare 137 io.stout.bits.debug.isMMIO := io.in.bits.mmio 138 io.stout.bits.debug.paddr := DontCare 139 io.stout.bits.debug.isPerfCnt := false.B 140 io.stout.bits.fflags := DontCare 141 142} 143 144class StoreUnit(implicit p: Parameters) extends XSModule { 145 val io = IO(new Bundle() { 146 val stin = Flipped(Decoupled(new ExuInput)) 147 val redirect = Flipped(ValidIO(new Redirect)) 148 val flush = Input(Bool()) 149 val tlbFeedback = ValidIO(new TlbFeedback) 150 val dtlb = new TlbRequestIO() 151 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 152 val isFirstIssue = Input(Bool()) 153 val lsq = ValidIO(new LsPipelineBundle) 154 val stout = DecoupledIO(new ExuOutput) // writeback store 155 }) 156 157 val store_s0 = Module(new StoreUnit_S0) 158 val store_s1 = Module(new StoreUnit_S1) 159 val store_s2 = Module(new StoreUnit_S2) 160 val store_s3 = Module(new StoreUnit_S3) 161 162 store_s0.io.in <> io.stin 163 store_s0.io.dtlbReq <> io.dtlb.req 164 store_s0.io.rsIdx := io.rsIdx 165 store_s0.io.isFirstIssue := io.isFirstIssue 166 167 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 168 169 store_s1.io.lsq <> io.lsq // send result to sq 170 store_s1.io.dtlbResp <> io.dtlb.resp 171 store_s1.io.tlbFeedback <> io.tlbFeedback 172 173 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 174 175 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 176 177 store_s3.io.stout <> io.stout 178 179 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 180 XSDebug(cond, 181 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 182 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 183 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 184 p"data ${Hexadecimal(pipeline.data)} " + 185 p"mask ${Hexadecimal(pipeline.mask)}\n" 186 ) 187 } 188 189 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 190 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 191 192} 193