1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9 10// Store Pipeline Stage 0 11// Generate addr, use addr to query DCache and DTLB 12class StoreUnit_S0 extends XSModule { 13 val io = IO(new Bundle() { 14 val in = Flipped(Decoupled(new ExuInput)) 15 val out = Decoupled(new LsPipelineBundle) 16 val dtlbReq = DecoupledIO(new TlbReq) 17 }) 18 19 // send req to dtlb 20 val saddr_old = io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN) 21 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 22 val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 23 val saddr_hi = Mux(imm12(11), 24 Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)), 25 Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12)) 26 ) 27 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 28 when(io.in.fire() && saddr(VAddrBits-1,0) =/= (io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN))(VAddrBits-1,0)){ 29 printf("saddr %x saddr_old %x\n", saddr, saddr_old(VAddrBits-1,0)) 30 } 31 32 io.dtlbReq.bits.vaddr := saddr 33 io.dtlbReq.valid := io.in.valid 34 io.dtlbReq.bits.cmd := TlbCmd.write 35 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 36 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 37 38 io.out.bits := DontCare 39 io.out.bits.vaddr := saddr 40 41 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 42 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 43 io.out.bits.data := io.in.bits.src2 44 } // not not touch fp store raw data 45 io.out.bits.uop := io.in.bits.uop 46 io.out.bits.miss := DontCare 47 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 48 io.out.valid := io.in.valid 49 io.in.ready := io.out.ready 50 51 // exception check 52 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 53 "b00".U -> true.B, //b 54 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 55 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 56 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 57 )) 58 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 59 60} 61 62// Load Pipeline Stage 1 63// TLB resp (send paddr to dcache) 64class StoreUnit_S1 extends XSModule { 65 val io = IO(new Bundle() { 66 val in = Flipped(Decoupled(new LsPipelineBundle)) 67 val out = Decoupled(new LsPipelineBundle) 68 // val fp_out = Decoupled(new LsPipelineBundle) 69 val lsq = ValidIO(new LsPipelineBundle) 70 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 71 val tlbFeedback = ValidIO(new TlbFeedback) 72 }) 73 74 val s1_paddr = io.dtlbResp.bits.paddr 75 val s1_tlb_miss = io.dtlbResp.bits.miss 76 77 io.in.ready := true.B 78 79 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 80 81 // Send TLB feedback to store issue queue 82 io.tlbFeedback.valid := io.in.valid 83 io.tlbFeedback.bits.hit := !s1_tlb_miss 84 io.tlbFeedback.bits.roqIdx := io.in.bits.uop.roqIdx 85 XSDebug(io.tlbFeedback.valid, 86 "S1 Store: tlbHit: %d roqIdx: %d\n", 87 io.tlbFeedback.bits.hit, 88 io.tlbFeedback.bits.roqIdx.asUInt 89 ) 90 91 92 // get paddr from dtlb, check if rollback is needed 93 // writeback store inst to lsq 94 io.lsq.valid := io.in.valid && !s1_tlb_miss// TODO: && ! FP 95 io.lsq.bits := io.in.bits 96 io.lsq.bits.paddr := s1_paddr 97 io.lsq.bits.miss := false.B 98 io.lsq.bits.mmio := io.dtlbResp.bits.mmio 99 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 100 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 101 102 // mmio inst with exception will be writebacked immediately 103 val hasException = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 104 io.out.valid := io.in.valid && (!io.out.bits.mmio || hasException) && !s1_tlb_miss 105 io.out.bits := io.lsq.bits 106 107 // encode data for fp store 108 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 109 io.lsq.bits.data := genWdata(ieee(io.in.bits.data), io.in.bits.uop.ctrl.fuOpType(1,0)) 110 } 111 112} 113 114class StoreUnit_S2 extends XSModule { 115 val io = IO(new Bundle() { 116 val in = Flipped(Decoupled(new LsPipelineBundle)) 117 val out = Decoupled(new LsPipelineBundle) 118 }) 119 120 io.in.ready := true.B 121 io.out.bits := io.in.bits 122 io.out.valid := io.in.valid 123 124} 125 126class StoreUnit_S3 extends XSModule { 127 val io = IO(new Bundle() { 128 val in = Flipped(Decoupled(new LsPipelineBundle)) 129 val stout = DecoupledIO(new ExuOutput) // writeback store 130 }) 131 132 io.in.ready := true.B 133 134 io.stout.valid := io.in.valid 135 io.stout.bits.uop := io.in.bits.uop 136 io.stout.bits.data := DontCare 137 io.stout.bits.redirectValid := false.B 138 io.stout.bits.redirect := DontCare 139 io.stout.bits.brUpdate := DontCare 140 io.stout.bits.debug.isMMIO := io.in.bits.mmio 141 io.stout.bits.debug.isPerfCnt := false.B 142 io.stout.bits.fflags := DontCare 143 144} 145 146class StoreUnit extends XSModule { 147 val io = IO(new Bundle() { 148 val stin = Flipped(Decoupled(new ExuInput)) 149 val redirect = Flipped(ValidIO(new Redirect)) 150 val tlbFeedback = ValidIO(new TlbFeedback) 151 val dtlb = new TlbRequestIO() 152 val lsq = ValidIO(new LsPipelineBundle) 153 val stout = DecoupledIO(new ExuOutput) // writeback store 154 }) 155 156 val store_s0 = Module(new StoreUnit_S0) 157 val store_s1 = Module(new StoreUnit_S1) 158 val store_s2 = Module(new StoreUnit_S2) 159 val store_s3 = Module(new StoreUnit_S3) 160 161 store_s0.io.in <> io.stin 162 store_s0.io.dtlbReq <> io.dtlb.req 163 164 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 165 166 store_s1.io.lsq <> io.lsq // send result to sq 167 store_s1.io.dtlbResp <> io.dtlb.resp 168 store_s1.io.tlbFeedback <> io.tlbFeedback 169 170 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 171 172 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 173 174 store_s3.io.stout <> io.stout 175 176 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 177 XSDebug(cond, 178 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 179 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 180 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 181 p"data ${Hexadecimal(pipeline.data)} " + 182 p"mask ${Hexadecimal(pipeline.mask)}\n" 183 ) 184 } 185 186 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 187 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 188 189} 190