1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.fu.FuType._ 30import xiangshan.backend.ctrlblock.DebugLsInfoBundle 31import xiangshan.backend.fu.NewCSR._ 32import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp, Pbmt} 33import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 34 35class StoreUnit(implicit p: Parameters) extends XSModule 36 with HasDCacheParameters 37 with HasVLSUParameters 38 { 39 val io = IO(new Bundle() { 40 val redirect = Flipped(ValidIO(new Redirect)) 41 val csrCtrl = Flipped(new CustomCSRCtrlIO) 42 val stin = Flipped(Decoupled(new MemExuInput)) 43 val issue = Valid(new MemExuInput) 44 // misalignBuffer issue path 45 val misalign_stin = Flipped(Decoupled(new LsPipelineBundle)) 46 val misalign_stout = Valid(new SqWriteBundle) 47 val tlb = new TlbRequestIO() 48 val dcache = new DCacheStoreIO 49 val pmp = Flipped(new PMPRespBundle()) 50 val lsq = ValidIO(new LsPipelineBundle) 51 val lsq_replenish = Output(new LsPipelineBundle()) 52 val feedback_slow = ValidIO(new RSFeedback) 53 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 54 // provide prefetch info to sms 55 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 56 // speculative for gated control 57 val s1_prefetch_spec = Output(Bool()) 58 val s2_prefetch_spec = Output(Bool()) 59 val stld_nuke_query = Valid(new StoreNukeQueryIO) 60 val stout = DecoupledIO(new MemExuOutput) // writeback store 61 val vecstout = DecoupledIO(new VecPipelineFeedbackIO(isVStore = true)) 62 // store mask, send to sq in store_s0 63 val st_mask_out = Valid(new StoreMaskBundle) 64 val debug_ls = Output(new DebugLsInfoBundle) 65 // vector 66 val vecstin = Flipped(Decoupled(new VecPipeBundle(isVStore = true))) 67 val vec_isFirstIssue = Input(Bool()) 68 // writeback to misalign buffer 69 val misalign_buf = Valid(new LsPipelineBundle) 70 // trigger 71 val fromCsrTrigger = Input(new CsrTriggerBundle) 72 }) 73 74 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 75 76 // Pipeline 77 // -------------------------------------------------------------------------------- 78 // stage 0 79 // -------------------------------------------------------------------------------- 80 // generate addr, use addr to query DCache and DTLB 81 val s0_iss_valid = io.stin.valid 82 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 83 val s0_vec_valid = io.vecstin.valid 84 val s0_ma_st_valid = io.misalign_stin.valid 85 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid || s0_ma_st_valid 86 val s0_use_flow_ma = s0_ma_st_valid 87 val s0_use_flow_vec = s0_vec_valid && !s0_ma_st_valid 88 val s0_use_flow_rs = s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 89 val s0_use_flow_prf = s0_prf_valid && !s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 90 val s0_use_non_prf_flow = s0_use_flow_rs || s0_use_flow_vec || s0_use_flow_ma 91 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 92 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 93 val s0_uop = Mux( 94 s0_use_flow_ma, 95 io.misalign_stin.bits.uop, 96 Mux( 97 s0_use_flow_rs, 98 s0_stin.uop, 99 s0_vecstin.uop 100 ) 101 ) 102 val s0_isFirstIssue = Mux( 103 s0_use_flow_ma, 104 false.B, 105 s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 106 ) 107 val s0_size = Mux(s0_use_non_prf_flow, s0_uop.fuOpType(2,0), 0.U)// may broken if use it in feature 108 val s0_mem_idx = Mux(s0_use_non_prf_flow, s0_uop.sqIdx.value, 0.U) 109 val s0_rob_idx = Mux(s0_use_non_prf_flow, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 110 val s0_pc = Mux(s0_use_non_prf_flow, s0_uop.pc, 0.U) 111 val s0_instr_type = Mux(s0_use_non_prf_flow, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 112 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 113 val s0_out = Wire(new LsPipelineBundle) 114 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 115 val s0_can_go = s1_ready 116 val s0_fire = s0_valid && !s0_kill && s0_can_go 117 val s0_is128bit = Mux(s0_use_flow_ma, io.misalign_stin.bits.is128bit, is128Bit(s0_vecstin.alignedType)) 118 // vector 119 val s0_vecActive = !s0_use_flow_vec || s0_vecstin.vecActive 120 // val s0_flowPtr = s0_vecstin.flowPtr 121 // val s0_isLastElem = s0_vecstin.isLastElem 122 val s0_secondInv = s0_vecstin.usSecondInv 123 val s0_elemIdx = s0_vecstin.elemIdx 124 val s0_alignedType = s0_vecstin.alignedType 125 val s0_mBIndex = s0_vecstin.mBIndex 126 val s0_vecBaseVaddr = s0_vecstin.basevaddr 127 128 // generate addr 129 val s0_saddr = s0_stin.src(0) + SignExt(s0_uop.imm(11,0), VAddrBits) 130 val s0_fullva = Wire(UInt(XLEN.W)) 131 val s0_vaddr = Mux( 132 s0_use_flow_ma, 133 io.misalign_stin.bits.vaddr, 134 Mux( 135 s0_use_flow_rs, 136 s0_saddr, 137 Mux( 138 s0_use_flow_vec, 139 s0_vecstin.vaddr(VAddrBits - 1, 0), 140 io.prefetch_req.bits.vaddr 141 ) 142 ) 143 ) 144 s0_fullva := Mux( 145 s0_use_flow_rs, 146 s0_stin.src(0) + SignExt(s0_uop.imm(11,0), XLEN), 147 Mux( 148 s0_use_flow_vec, 149 s0_vecstin.vaddr, 150 s0_vaddr 151 ) 152 ) 153 154 val s0_mask = Mux( 155 s0_use_flow_ma, 156 io.misalign_stin.bits.mask, 157 Mux( 158 s0_use_flow_rs, 159 genVWmask128(s0_saddr, s0_uop.fuOpType(2,0)), 160 Mux( 161 s0_use_flow_vec, 162 s0_vecstin.mask, 163 // -1.asSInt.asUInt 164 Fill(VLEN/8, 1.U(1.W)) 165 ) 166 ) 167 ) 168 169 io.tlb.req.valid := s0_valid 170 io.tlb.req.bits.vaddr := s0_vaddr 171 io.tlb.req.bits.fullva := s0_fullva 172 io.tlb.req.bits.checkfullva := s0_use_flow_rs || s0_use_flow_vec 173 io.tlb.req.bits.cmd := TlbCmd.write 174 io.tlb.req.bits.isPrefetch := s0_use_flow_prf 175 io.tlb.req.bits.size := s0_size 176 io.tlb.req.bits.kill := false.B 177 io.tlb.req.bits.memidx.is_ld := false.B 178 io.tlb.req.bits.memidx.is_st := true.B 179 io.tlb.req.bits.memidx.idx := s0_mem_idx 180 io.tlb.req.bits.debug.robIdx := s0_rob_idx 181 io.tlb.req.bits.no_translate := false.B 182 io.tlb.req.bits.debug.pc := s0_pc 183 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 184 io.tlb.req_kill := false.B 185 io.tlb.req.bits.hyperinst := LSUOpType.isHsv(s0_uop.fuOpType) 186 io.tlb.req.bits.hlvx := false.B 187 io.tlb.req.bits.pmp_addr := DontCare 188 189 // Dcache access here: not **real** dcache write 190 // just read meta and tag in dcache, to find out the store will hit or miss 191 192 // NOTE: The store request does not wait for the dcache to be ready. 193 // If the dcache is not ready at this time, the dcache is not queried. 194 // But, store prefetch request will always wait for dcache to be ready to make progress. 195 io.dcache.req.valid := s0_fire 196 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 197 io.dcache.req.bits.vaddr := s0_vaddr 198 io.dcache.req.bits.instrtype := s0_instr_type 199 200 s0_out := DontCare 201 s0_out.vaddr := s0_vaddr 202 s0_out.fullva := s0_fullva 203 // Now data use its own io 204 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.fuOpType(1,0)) 205 s0_out.data := s0_stin.src(1) 206 s0_out.uop := s0_uop 207 s0_out.miss := false.B 208 s0_out.mask := s0_mask 209 s0_out.isFirstIssue := s0_isFirstIssue 210 s0_out.isHWPrefetch := s0_use_flow_prf 211 s0_out.wlineflag := s0_wlineflag 212 s0_out.isvec := s0_use_flow_vec 213 s0_out.is128bit := s0_is128bit 214 s0_out.vecActive := s0_vecActive 215 s0_out.usSecondInv := s0_secondInv 216 s0_out.elemIdx := s0_elemIdx 217 s0_out.alignedType := s0_alignedType 218 s0_out.mbIndex := s0_mBIndex 219 s0_out.vecBaseVaddr := s0_vecBaseVaddr 220 when(s0_valid && s0_isFirstIssue) { 221 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 222 } 223 s0_out.isFrmMisAlignBuf := s0_use_flow_ma 224 225 // exception check 226 val s0_addr_aligned = LookupTree(Mux(s0_use_flow_vec, s0_vecstin.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 227 "b00".U -> true.B, //b 228 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 229 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 230 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 231 )) 232 // if vector store sends 128-bit requests, its address must be 128-aligned 233 XSError(s0_use_flow_vec && s0_out.vaddr(3, 0) =/= 0.U && s0_vecstin.alignedType(2), "unit stride 128 bit element is not aligned!") 234 s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_non_prf_flow, (!s0_addr_aligned || s0_vecstin.uop.exceptionVec(storeAddrMisaligned) && s0_vecActive), false.B) 235 236 io.st_mask_out.valid := s0_use_flow_rs || s0_use_flow_vec 237 io.st_mask_out.bits.mask := s0_out.mask 238 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 239 240 io.stin.ready := s1_ready && s0_use_flow_rs 241 io.vecstin.ready := s1_ready && s0_use_flow_vec 242 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 243 io.misalign_stin.ready := s1_ready && s0_use_flow_ma 244 245 // Pipeline 246 // -------------------------------------------------------------------------------- 247 // stage 1 248 // -------------------------------------------------------------------------------- 249 // TLB resp (send paddr to dcache) 250 val s1_valid = RegInit(false.B) 251 val s1_in = RegEnable(s0_out, s0_fire) 252 val s1_out = Wire(new LsPipelineBundle) 253 val s1_kill = Wire(Bool()) 254 val s1_can_go = s2_ready 255 val s1_fire = s1_valid && !s1_kill && s1_can_go 256 val s1_vecActive = RegEnable(s0_out.vecActive, true.B, s0_fire) 257 val s1_frm_mabuf = s1_in.isFrmMisAlignBuf 258 259 // mmio cbo decoder 260 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 261 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 262 s1_in.uop.fuOpType === LSUOpType.cbo_inval 263 val s1_vaNeedExt = io.tlb.resp.bits.excp(0).vaNeedExt 264 val s1_isHyper = io.tlb.resp.bits.excp(0).isHyper 265 val s1_paddr = io.tlb.resp.bits.paddr(0) 266 val s1_gpaddr = io.tlb.resp.bits.gpaddr(0) 267 val s1_isForVSnonLeafPTE = io.tlb.resp.bits.isForVSnonLeafPTE 268 val s1_tlb_miss = io.tlb.resp.bits.miss 269 val s1_mmio = s1_mmio_cbo 270 val s1_pbmt = io.tlb.resp.bits.pbmt(0) 271 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 272 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 273 // val s1_isLastElem = RegEnable(s0_isLastElem, false.B, s0_fire) 274 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || (s1_tlb_miss && !s1_isvec && !s1_frm_mabuf) 275 276 s1_ready := !s1_valid || s1_kill || s2_ready 277 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 278 when (s0_fire) { s1_valid := true.B } 279 .elsewhen (s1_fire) { s1_valid := false.B } 280 .elsewhen (s1_kill) { s1_valid := false.B } 281 282 // st-ld violation dectect request. 283 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_frm_mabuf 284 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 285 io.stld_nuke_query.bits.paddr := s1_paddr 286 io.stld_nuke_query.bits.mask := s1_in.mask 287 io.stld_nuke_query.bits.matchLine := s1_in.isvec && s1_in.is128bit 288 289 // issue 290 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec && !s1_frm_mabuf 291 io.issue.bits := RegEnable(s0_stin, s0_valid) 292 293 294 // Send TLB feedback to store issue queue 295 // Store feedback is generated in store_s1, sent to RS in store_s2 296 val s1_feedback = Wire(Valid(new RSFeedback)) 297 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 298 s1_feedback.bits.hit := !s1_tlb_miss 299 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 300 s1_feedback.bits.robIdx := s1_out.uop.robIdx 301 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 302 s1_feedback.bits.dataInvalidSqIdx := DontCare 303 s1_feedback.bits.sqIdx := s1_out.uop.sqIdx 304 s1_feedback.bits.lqIdx := s1_out.uop.lqIdx 305 306 XSDebug(s1_feedback.valid, 307 "S1 Store: tlbHit: %d robIdx: %d\n", 308 s1_feedback.bits.hit, 309 s1_feedback.bits.robIdx.value 310 ) 311 312 // io.feedback_slow := s1_feedback 313 314 // get paddr from dtlb, check if rollback is needed 315 // writeback store inst to lsq 316 s1_out := s1_in 317 s1_out.paddr := s1_paddr 318 s1_out.gpaddr := s1_gpaddr 319 s1_out.vaNeedExt := s1_vaNeedExt 320 s1_out.isHyper := s1_isHyper 321 s1_out.miss := false.B 322 s1_out.mmio := s1_mmio 323 s1_out.tlbMiss := s1_tlb_miss 324 s1_out.atomic := s1_mmio 325 s1_out.isForVSnonLeafPTE := s1_isForVSnonLeafPTE 326 when (!s1_out.isvec && RegNext(io.tlb.req.bits.checkfullva) && 327 (s1_out.uop.exceptionVec(storePageFault) || 328 s1_out.uop.exceptionVec(storeAccessFault) || 329 s1_out.uop.exceptionVec(storeGuestPageFault))) { 330 s1_out.uop.exceptionVec(storeAddrMisaligned) := false.B 331 } 332 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_vecActive 333 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_vecActive 334 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st && s1_vecActive 335 336 // trigger 337 val storeTrigger = Module(new MemTrigger(MemType.STORE)) 338 storeTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 339 storeTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 340 storeTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 341 storeTrigger.io.fromCsrTrigger.debugMode := io.fromCsrTrigger.debugMode 342 storeTrigger.io.fromLoadStore.vaddr := s1_in.vaddr 343 storeTrigger.io.fromLoadStore.isVectorUnitStride := s1_in.isvec && s1_in.is128bit 344 storeTrigger.io.fromLoadStore.mask := s1_in.mask 345 346 val s1_trigger_action = storeTrigger.io.toLoadStore.triggerAction 347 val s1_trigger_debug_mode = TriggerAction.isDmode(s1_trigger_action) 348 val s1_trigger_breakpoint = TriggerAction.isExp(s1_trigger_action) 349 350 s1_out.uop.flushPipe := false.B 351 s1_out.uop.trigger := s1_trigger_action 352 s1_out.uop.exceptionVec(breakPoint) := s1_trigger_breakpoint 353 s1_out.vecVaddrOffset := Mux( 354 s1_trigger_debug_mode || s1_trigger_breakpoint, 355 storeTrigger.io.toLoadStore.triggerVaddr - s1_in.vecBaseVaddr, 356 s1_in.vaddr + genVFirstUnmask(s1_in.mask).asUInt - s1_in.vecBaseVaddr , 357 ) 358 s1_out.vecTriggerMask := Mux(s1_trigger_debug_mode || s1_trigger_breakpoint, storeTrigger.io.toLoadStore.triggerMask, 0.U) 359 360 // scalar store and scalar load nuke check, and also other purposes 361 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch && !s1_frm_mabuf 362 io.lsq.bits := s1_out 363 io.lsq.bits.miss := s1_tlb_miss 364 365 // goto misalignBuffer 366 io.misalign_buf.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && GatedValidRegNext(io.csrCtrl.hd_misalign_st_enable) && !s1_in.isvec 367 io.misalign_buf.bits := io.lsq.bits 368 369 // kill dcache write intent request when tlb miss or exception 370 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 371 io.dcache.s1_paddr := s1_paddr 372 373 // write below io.out.bits assign sentence to prevent overwriting values 374 val s1_tlb_memidx = io.tlb.resp.bits.memidx 375 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 376 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 377 s1_out.uop.debugInfo.tlbRespTime := GTimer() 378 } 379 380 // Pipeline 381 // -------------------------------------------------------------------------------- 382 // stage 2 383 // -------------------------------------------------------------------------------- 384 // mmio check 385 val s2_valid = RegInit(false.B) 386 val s2_in = RegEnable(s1_out, s1_fire) 387 val s2_out = Wire(new LsPipelineBundle) 388 val s2_kill = Wire(Bool()) 389 val s2_can_go = s3_ready 390 val s2_fire = s2_valid && !s2_kill && s2_can_go 391 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 392 val s2_frm_mabuf = s2_in.isFrmMisAlignBuf 393 val s2_pbmt = RegEnable(s1_pbmt, s1_fire) 394 val s2_trigger_debug_mode = RegEnable(s1_trigger_debug_mode, false.B, s1_fire) 395 val s2_mis_align = GatedValidRegNext(io.csrCtrl.hd_misalign_st_enable) && !s2_in.isvec && 396 s2_in.uop.exceptionVec(storeAddrMisaligned) && !s2_in.uop.exceptionVec(breakPoint) && !s2_trigger_debug_mode 397 398 s2_ready := !s2_valid || s2_kill || s3_ready 399 when (s1_fire) { s2_valid := true.B } 400 .elsewhen (s2_fire) { s2_valid := false.B } 401 .elsewhen (s2_kill) { s2_valid := false.B } 402 403 val s2_pmp = WireInit(io.pmp) 404 405 val s2_exception = RegNext(s1_feedback.bits.hit) && 406 (s2_trigger_debug_mode || ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR) 407 val s2_mmio = (s2_in.mmio || s2_pmp.mmio || Pbmt.isUncache(s2_pbmt)) && RegNext(s1_feedback.bits.hit) 408 s2_kill := ((s2_mmio && !s2_exception) && !s2_in.isvec) || s2_in.uop.robIdx.needFlush(io.redirect) 409 410 s2_out := s2_in 411 s2_out.af := s2_out.uop.exceptionVec(storeAccessFault) 412 s2_out.mmio := s2_mmio && !s2_exception 413 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 414 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || 415 s2_pmp.st || 416 (s2_in.isvec && s2_pmp.mmio && RegNext(s1_feedback.bits.hit)) 417 ) && s2_vecActive 418 s2_out.uop.vpu.vstart := s2_in.vecVaddrOffset >> s2_in.uop.vpu.veew 419 420 // kill dcache write intent request when mmio or exception 421 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 422 io.dcache.s2_pc := s2_out.uop.pc 423 // TODO: dcache resp 424 io.dcache.resp.ready := true.B 425 426 // feedback tlb miss to RS in store_s2 427 val feedback_slow_valid = WireInit(false.B) 428 feedback_slow_valid := s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect) && !s1_out.isvec && !s1_frm_mabuf 429 io.feedback_slow.valid := GatedValidRegNext(feedback_slow_valid) 430 io.feedback_slow.bits := RegEnable(s1_feedback.bits, feedback_slow_valid) 431 432 val s2_vecFeedback = RegNext(!s1_out.uop.robIdx.needFlush(io.redirect) && s1_feedback.bits.hit && s1_feedback.valid) && s2_in.isvec 433 434 val s2_misalign_stout = WireInit(0.U.asTypeOf(io.misalign_stout)) 435 s2_misalign_stout.valid := s2_valid && s2_can_go && s2_frm_mabuf 436 s2_misalign_stout.bits.mmio := s2_out.mmio 437 s2_misalign_stout.bits.vaddr := s2_out.vaddr 438 s2_misalign_stout.bits.isHyper := s2_out.isHyper 439 s2_misalign_stout.bits.paddr := s2_out.paddr 440 s2_misalign_stout.bits.gpaddr := s2_out.gpaddr 441 s2_misalign_stout.bits.isForVSnonLeafPTE := s2_out.isForVSnonLeafPTE 442 s2_misalign_stout.bits.need_rep := RegEnable(s1_tlb_miss, s1_fire) 443 s2_misalign_stout.bits.uop.exceptionVec := s2_out.uop.exceptionVec 444 io.misalign_stout := s2_misalign_stout 445 446 // mmio and exception 447 io.lsq_replenish := s2_out 448 io.lsq_replenish.af := s2_out.af && s2_valid && !s2_kill 449 450 // prefetch related 451 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 452 453 // RegNext prefetch train for better timing 454 // ** Now, prefetch train is valid at store s3 ** 455 val s2_prefetch_train_valid = WireInit(false.B) 456 s2_prefetch_train_valid := s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch 457 if(EnableStorePrefetchSMS) { 458 io.s1_prefetch_spec := s1_fire 459 io.s2_prefetch_spec := s2_prefetch_train_valid 460 io.prefetch_train.valid := RegNext(s2_prefetch_train_valid) 461 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = s2_prefetch_train_valid) 462 }else { 463 io.s1_prefetch_spec := false.B 464 io.s2_prefetch_spec := false.B 465 io.prefetch_train.valid := false.B 466 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = false.B) 467 } 468 // override miss bit 469 io.prefetch_train.bits.miss := RegEnable(io.dcache.resp.bits.miss, s2_prefetch_train_valid) 470 // TODO: add prefetch and access bit 471 io.prefetch_train.bits.meta_prefetch := false.B 472 io.prefetch_train.bits.meta_access := false.B 473 474 // Pipeline 475 // -------------------------------------------------------------------------------- 476 // stage 3 477 // -------------------------------------------------------------------------------- 478 // store write back 479 val s3_valid = RegInit(false.B) 480 val s3_in = RegEnable(s2_out, s2_fire) 481 val s3_out = Wire(new MemExuOutput(isVector = true)) 482 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 483 val s3_can_go = s3_ready 484 val s3_fire = s3_valid && !s3_kill && s3_can_go 485 val s3_vecFeedback = RegEnable(s2_vecFeedback, s2_fire) 486 487 // store misalign will not writeback to rob now 488 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch && !s2_mis_align && !s2_frm_mabuf } 489 .elsewhen (s3_fire) { s3_valid := false.B } 490 .elsewhen (s3_kill) { s3_valid := false.B } 491 492 // wb: writeback 493 val SelectGroupSize = RollbackGroupSize 494 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 495 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 496 497 s3_out := DontCare 498 s3_out.uop := s3_in.uop 499 s3_out.data := DontCare 500 s3_out.debug.isMMIO := s3_in.mmio 501 s3_out.debug.paddr := s3_in.paddr 502 s3_out.debug.vaddr := s3_in.vaddr 503 s3_out.debug.isPerfCnt := false.B 504 505 // Pipeline 506 // -------------------------------------------------------------------------------- 507 // stage x 508 // -------------------------------------------------------------------------------- 509 // delay TotalSelectCycles - 2 cycle(s) 510 val TotalDelayCycles = TotalSelectCycles - 2 511 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 512 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 513 val sx_in = Wire(Vec(TotalDelayCycles + 1, new VecMemExuOutput(isVector = true))) 514 515 // backward ready signal 516 s3_ready := sx_ready.head 517 for (i <- 0 until TotalDelayCycles + 1) { 518 if (i == 0) { 519 sx_valid(i) := s3_valid 520 sx_in(i).output := s3_out 521 sx_in(i).vecFeedback := s3_vecFeedback 522 sx_in(i).mmio := s3_in.mmio 523 sx_in(i).usSecondInv := s3_in.usSecondInv 524 sx_in(i).elemIdx := s3_in.elemIdx 525 sx_in(i).alignedType := s3_in.alignedType 526 sx_in(i).mbIndex := s3_in.mbIndex 527 sx_in(i).mask := s3_in.mask 528 sx_in(i).vaddr := s3_in.fullva 529 sx_in(i).vaNeedExt := s3_in.vaNeedExt 530 sx_in(i).gpaddr := s3_in.gpaddr 531 sx_in(i).isForVSnonLeafPTE := s3_in.isForVSnonLeafPTE 532 sx_in(i).vecTriggerMask := s3_in.vecTriggerMask 533 sx_ready(i) := !s3_valid(i) || sx_in(i).output.uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 534 } else { 535 val cur_kill = sx_in(i).output.uop.robIdx.needFlush(io.redirect) 536 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 537 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 538 val prev_fire = sx_valid(i-1) && !sx_in(i-1).output.uop.robIdx.needFlush(io.redirect) && sx_ready(i) 539 540 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 541 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 542 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 543 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 544 } 545 } 546 val sx_last_valid = sx_valid.takeRight(1).head 547 val sx_last_ready = sx_ready.takeRight(1).head 548 val sx_last_in = sx_in.takeRight(1).head 549 sx_last_ready := !sx_last_valid || sx_last_in.output.uop.robIdx.needFlush(io.redirect) || io.stout.ready 550 551 io.stout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isStore(sx_last_in.output.uop.fuType) 552 io.stout.bits := sx_last_in.output 553 io.stout.bits.uop.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, StaCfg) 554 555 io.vecstout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isVStore(sx_last_in.output.uop.fuType) 556 // TODO: implement it! 557 io.vecstout.bits.mBIndex := sx_last_in.mbIndex 558 io.vecstout.bits.hit := sx_last_in.vecFeedback 559 io.vecstout.bits.isvec := true.B 560 io.vecstout.bits.sourceType := RSFeedbackType.tlbMiss 561 io.vecstout.bits.flushState := DontCare 562 io.vecstout.bits.trigger := sx_last_in.output.uop.trigger 563 io.vecstout.bits.mmio := sx_last_in.mmio 564 io.vecstout.bits.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, VstuCfg) 565 io.vecstout.bits.usSecondInv := sx_last_in.usSecondInv 566 io.vecstout.bits.vecFeedback := sx_last_in.vecFeedback 567 io.vecstout.bits.elemIdx := sx_last_in.elemIdx 568 io.vecstout.bits.alignedType := sx_last_in.alignedType 569 io.vecstout.bits.mask := sx_last_in.mask 570 io.vecstout.bits.vaddr := sx_last_in.vaddr 571 io.vecstout.bits.vaNeedExt := sx_last_in.vaNeedExt 572 io.vecstout.bits.gpaddr := sx_last_in.gpaddr 573 io.vecstout.bits.isForVSnonLeafPTE := sx_last_in.isForVSnonLeafPTE 574 io.vecstout.bits.vstart := sx_last_in.output.uop.vpu.vstart 575 io.vecstout.bits.vecTriggerMask := sx_last_in.vecTriggerMask 576 // io.vecstout.bits.reg_offset.map(_ := DontCare) 577 // io.vecstout.bits.elemIdx.map(_ := sx_last_in.elemIdx) 578 // io.vecstout.bits.elemIdxInsideVd.map(_ := DontCare) 579 // io.vecstout.bits.vecdata.map(_ := DontCare) 580 // io.vecstout.bits.mask.map(_ := DontCare) 581 // io.vecstout.bits.alignedType.map(_ := sx_last_in.alignedType) 582 583 io.debug_ls := DontCare 584 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 585 io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 586 587 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 588 XSDebug(cond, 589 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 590 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 591 p"op ${Binary(pipeline.uop.fuOpType)} " + 592 p"data ${Hexadecimal(pipeline.data)} " + 593 p"mask ${Hexadecimal(pipeline.mask)}\n" 594 ) 595 } 596 597 printPipeLine(s0_out, s0_valid, "S0") 598 printPipeLine(s1_out, s1_valid, "S1") 599 600 // perf cnt 601 XSPerfAccumulate("s0_in_valid", s0_valid) 602 XSPerfAccumulate("s0_in_fire", s0_fire) 603 XSPerfAccumulate("s0_vecin_fire", s0_fire && s0_use_flow_vec) 604 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 605 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 606 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 607 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 608 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 609 610 XSPerfAccumulate("s1_in_valid", s1_valid) 611 XSPerfAccumulate("s1_in_fire", s1_fire) 612 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 613 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 614 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 615 // end 616} 617