1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9 10// Store Pipeline Stage 0 11// Generate addr, use addr to query DCache and DTLB 12class StoreUnit_S0 extends XSModule { 13 val io = IO(new Bundle() { 14 val in = Flipped(Decoupled(new ExuInput)) 15 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 16 val out = Decoupled(new LsPipelineBundle) 17 val dtlbReq = DecoupledIO(new TlbReq) 18 }) 19 20 // send req to dtlb 21 val saddr = io.in.bits.src1 + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 22 // val saddr_old = io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN) 23 // val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 24 // val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 25 // val saddr_hi = Mux(imm12(11), 26 // Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)), 27 // Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12)) 28 // ) 29 // val saddr = Cat(saddr_hi, saddr_lo(11,0)) 30 // when(io.in.fire() && saddr(VAddrBits-1,0) =/= (io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN))(VAddrBits-1,0)){ 31 // printf("saddr %x saddr_old %x\n", saddr, saddr_old(VAddrBits-1,0)) 32 // } 33 34 io.dtlbReq.bits.vaddr := saddr 35 io.dtlbReq.valid := io.in.valid 36 io.dtlbReq.bits.cmd := TlbCmd.write 37 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 38 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 39 40 io.out.bits := DontCare 41 io.out.bits.vaddr := saddr 42 43 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 44 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 45 io.out.bits.data := io.in.bits.src2 46 } // not not touch fp store raw data 47 io.out.bits.uop := io.in.bits.uop 48 io.out.bits.miss := DontCare 49 io.out.bits.rsIdx := io.rsIdx 50 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 51 io.out.valid := io.in.valid 52 io.in.ready := io.out.ready 53 54 // exception check 55 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 56 "b00".U -> true.B, //b 57 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 58 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 59 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 60 )) 61 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 62 63} 64 65// Load Pipeline Stage 1 66// TLB resp (send paddr to dcache) 67class StoreUnit_S1 extends XSModule { 68 val io = IO(new Bundle() { 69 val in = Flipped(Decoupled(new LsPipelineBundle)) 70 val out = Decoupled(new LsPipelineBundle) 71 // val fp_out = Decoupled(new LsPipelineBundle) 72 val lsq = ValidIO(new LsPipelineBundle) 73 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 74 val tlbFeedback = ValidIO(new TlbFeedback) 75 }) 76 77 val s1_paddr = io.dtlbResp.bits.paddr 78 val s1_tlb_miss = io.dtlbResp.bits.miss 79 val s1_mmio = io.dtlbResp.bits.mmio 80 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 81 82 io.in.ready := true.B 83 84 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 85 86 // Send TLB feedback to store issue queue 87 io.tlbFeedback.valid := io.in.valid 88 io.tlbFeedback.bits.hit := !s1_tlb_miss 89 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 90 XSDebug(io.tlbFeedback.valid, 91 "S1 Store: tlbHit: %d roqIdx: %d\n", 92 io.tlbFeedback.bits.hit, 93 io.tlbFeedback.bits.rsIdx 94 ) 95 96 97 // get paddr from dtlb, check if rollback is needed 98 // writeback store inst to lsq 99 io.lsq.valid := io.in.valid && !s1_tlb_miss// TODO: && ! FP 100 io.lsq.bits := io.in.bits 101 io.lsq.bits.paddr := s1_paddr 102 io.lsq.bits.miss := false.B 103 io.lsq.bits.mmio := s1_mmio && !s1_exception 104 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 105 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 106 107 // mmio inst with exception will be writebacked immediately 108 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 109 io.out.bits := io.lsq.bits 110 111 // encode data for fp store 112 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 113 io.lsq.bits.data := genWdata(ieee(io.in.bits.data), io.in.bits.uop.ctrl.fuOpType(1,0)) 114 } 115 116} 117 118class StoreUnit_S2 extends XSModule { 119 val io = IO(new Bundle() { 120 val in = Flipped(Decoupled(new LsPipelineBundle)) 121 val out = Decoupled(new LsPipelineBundle) 122 }) 123 124 io.in.ready := true.B 125 io.out.bits := io.in.bits 126 io.out.valid := io.in.valid 127 128} 129 130class StoreUnit_S3 extends XSModule { 131 val io = IO(new Bundle() { 132 val in = Flipped(Decoupled(new LsPipelineBundle)) 133 val stout = DecoupledIO(new ExuOutput) // writeback store 134 }) 135 136 io.in.ready := true.B 137 138 io.stout.valid := io.in.valid 139 io.stout.bits.uop := io.in.bits.uop 140 io.stout.bits.data := DontCare 141 io.stout.bits.redirectValid := false.B 142 io.stout.bits.redirect := DontCare 143 io.stout.bits.debug.isMMIO := io.in.bits.mmio 144 io.stout.bits.debug.isPerfCnt := false.B 145 io.stout.bits.fflags := DontCare 146 147} 148 149class StoreUnit extends XSModule { 150 val io = IO(new Bundle() { 151 val stin = Flipped(Decoupled(new ExuInput)) 152 val redirect = Flipped(ValidIO(new Redirect)) 153 val flush = Input(Bool()) 154 val tlbFeedback = ValidIO(new TlbFeedback) 155 val dtlb = new TlbRequestIO() 156 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 157 val lsq = ValidIO(new LsPipelineBundle) 158 val stout = DecoupledIO(new ExuOutput) // writeback store 159 }) 160 161 val store_s0 = Module(new StoreUnit_S0) 162 val store_s1 = Module(new StoreUnit_S1) 163 val store_s2 = Module(new StoreUnit_S2) 164 val store_s3 = Module(new StoreUnit_S3) 165 166 store_s0.io.in <> io.stin 167 store_s0.io.dtlbReq <> io.dtlb.req 168 store_s0.io.rsIdx := io.rsIdx 169 170 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 171 172 store_s1.io.lsq <> io.lsq // send result to sq 173 store_s1.io.dtlbResp <> io.dtlb.resp 174 store_s1.io.tlbFeedback <> io.tlbFeedback 175 176 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 177 178 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 179 180 store_s3.io.stout <> io.stout 181 182 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 183 XSDebug(cond, 184 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 185 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 186 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 187 p"data ${Hexadecimal(pipeline.data)} " + 188 p"mask ${Hexadecimal(pipeline.mask)}\n" 189 ) 190 } 191 192 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 193 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 194 195} 196