1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9 10// Store Pipeline Stage 0 11// Generate addr, use addr to query DCache and DTLB 12class StoreUnit_S0 extends XSModule { 13 val io = IO(new Bundle() { 14 val in = Flipped(Decoupled(new ExuInput)) 15 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 16 val out = Decoupled(new LsPipelineBundle) 17 val dtlbReq = DecoupledIO(new TlbReq) 18 }) 19 20 // send req to dtlb 21 val saddr_old = io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN) 22 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 23 val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 24 val saddr_hi = Mux(imm12(11), 25 Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)), 26 Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12)) 27 ) 28 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 29 when(io.in.fire() && saddr(VAddrBits-1,0) =/= (io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN))(VAddrBits-1,0)){ 30 printf("saddr %x saddr_old %x\n", saddr, saddr_old(VAddrBits-1,0)) 31 } 32 33 io.dtlbReq.bits.vaddr := saddr 34 io.dtlbReq.valid := io.in.valid 35 io.dtlbReq.bits.cmd := TlbCmd.write 36 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 37 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 38 39 io.out.bits := DontCare 40 io.out.bits.vaddr := saddr 41 42 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 43 io.out.bits.uop := io.in.bits.uop 44 io.out.bits.miss := DontCare 45 io.out.bits.rsIdx := io.rsIdx 46 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 47 io.out.valid := io.in.valid 48 io.in.ready := io.out.ready 49 50 // exception check 51 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 52 "b00".U -> true.B, //b 53 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 54 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 55 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 56 )) 57 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 58 59} 60 61// Load Pipeline Stage 1 62// TLB resp (send paddr to dcache) 63class StoreUnit_S1 extends XSModule { 64 val io = IO(new Bundle() { 65 val in = Flipped(Decoupled(new LsPipelineBundle)) 66 val out = Decoupled(new LsPipelineBundle) 67 val lsq = ValidIO(new LsPipelineBundle) 68 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 69 val tlbFeedback = ValidIO(new TlbFeedback) 70 }) 71 72 val s1_paddr = io.dtlbResp.bits.paddr 73 val s1_tlb_miss = io.dtlbResp.bits.miss 74 val s1_mmio = io.dtlbResp.bits.mmio 75 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 76 77 io.in.ready := true.B 78 79 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 80 81 // Send TLB feedback to store issue queue 82 io.tlbFeedback.valid := io.in.valid 83 io.tlbFeedback.bits.hit := !s1_tlb_miss 84 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 85 XSDebug(io.tlbFeedback.valid, 86 "S1 Store: tlbHit: %d roqIdx: %d\n", 87 io.tlbFeedback.bits.hit, 88 io.tlbFeedback.bits.rsIdx 89 ) 90 91 92 // get paddr from dtlb, check if rollback is needed 93 // writeback store inst to lsq 94 io.lsq.valid := io.in.valid && !s1_tlb_miss 95 io.lsq.bits := io.in.bits 96 io.lsq.bits.paddr := s1_paddr 97 io.lsq.bits.miss := false.B 98 io.lsq.bits.mmio := s1_mmio && !s1_exception 99 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 100 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 101 102 // mmio inst with exception will be writebacked immediately 103 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 104 io.out.bits := io.lsq.bits 105} 106 107class StoreUnit_S2 extends XSModule { 108 val io = IO(new Bundle() { 109 val in = Flipped(Decoupled(new LsPipelineBundle)) 110 val out = Decoupled(new LsPipelineBundle) 111 }) 112 113 io.in.ready := true.B 114 io.out.bits := io.in.bits 115 io.out.valid := io.in.valid 116 117} 118 119class StoreUnit_S3 extends XSModule { 120 val io = IO(new Bundle() { 121 val in = Flipped(Decoupled(new LsPipelineBundle)) 122 val stout = DecoupledIO(new ExuOutput) // writeback store 123 }) 124 125 io.in.ready := true.B 126 127 io.stout.valid := io.in.valid 128 io.stout.bits.uop := io.in.bits.uop 129 io.stout.bits.data := DontCare 130 io.stout.bits.redirectValid := false.B 131 io.stout.bits.redirect := DontCare 132 io.stout.bits.debug.isMMIO := io.in.bits.mmio 133 io.stout.bits.debug.paddr := DontCare 134 io.stout.bits.debug.isPerfCnt := false.B 135 io.stout.bits.fflags := DontCare 136 137} 138 139class StoreUnit extends XSModule { 140 val io = IO(new Bundle() { 141 val stin = Flipped(Decoupled(new ExuInput)) 142 val redirect = Flipped(ValidIO(new Redirect)) 143 val flush = Input(Bool()) 144 val tlbFeedback = ValidIO(new TlbFeedback) 145 val dtlb = new TlbRequestIO() 146 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 147 val lsq = ValidIO(new LsPipelineBundle) 148 val stout = DecoupledIO(new ExuOutput) // writeback store 149 }) 150 151 val store_s0 = Module(new StoreUnit_S0) 152 val store_s1 = Module(new StoreUnit_S1) 153 val store_s2 = Module(new StoreUnit_S2) 154 val store_s3 = Module(new StoreUnit_S3) 155 156 store_s0.io.in <> io.stin 157 store_s0.io.dtlbReq <> io.dtlb.req 158 store_s0.io.rsIdx := io.rsIdx 159 160 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 161 162 store_s1.io.lsq <> io.lsq // send result to sq 163 store_s1.io.dtlbResp <> io.dtlb.resp 164 store_s1.io.tlbFeedback <> io.tlbFeedback 165 166 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 167 168 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 169 170 store_s3.io.stout <> io.stout 171 172 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 173 XSDebug(cond, 174 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 175 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 176 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 177 p"data ${Hexadecimal(pipeline.data)} " + 178 p"mask ${Hexadecimal(pipeline.mask)}\n" 179 ) 180 } 181 182 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 183 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 184 185} 186